NXP LPC2109, LPC2119, LPC2129 Technical data

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers; 64/128/256 kB ISP/IAP
flash with 10-bit ADC and CAN

Rev. 06 — 10 December 2007 Product data sheet

1. General description

The LPC2109/2119/2129 are based on a 16/32-bit ARM7TDMI-S CPU with real-time
emulation and embedded trace support, together with 64/128/256 kB of embedded
high-speed flash memory. A 128-bit wide memory interface and a unique accelerator
architecture enable 32-bit code execution at maximum clock rate. For critical code size
applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with
minimal performance penalty.

With their compact 64-pin package, low power consumption, various 32-bit timers,
4-channel 10-bit ADC, two advanced CAN channels, PWM channels and 46 fast GPIO
lines with up to nine external interrupt pins these microcontrollers are particularly suitable
for automotive and industrial control applications, as well as medical systems and
fault-tolerant maintenance buses. With a wide range of additional serial communications
interfaces, they are also suited for communication gateways and protocol converters as
well as many other general-purpose applications.

2. Features

2.1 Key features brought by LPC2109/2119/2129/01 devices

2.2 Key features common for all devices

Remark: Throughout the data sheet, the term LPC2109/2119/2129 will apply to devices

with and without the /00 or /01 suffixes. The /00 or the /01 suffix will be used to
differentiate from other devices only when necessary.

n FastGPIOports enableport pin toggling up to 3.5 times fasterthantheoriginaldevice.

They also allow for a port pin to be read at any time regardless of its function.

n Dedicated result registers for ADC(s) reduce interrupt overhead. The ADC pads are

5 V tolerant when configured for digital I/O function(s).

n UART0/1 include fractional baud rate generator, auto-bauding capabilities and

handshake flow-control fully implemented in hardware.

n Buffered SSP serial controller supporting SPI, 4-wire SSI, and Microwire formats.
n SPI programmable data length and master mode enhancement.
n Diversified Code Read Protection (CRP) enables different security levels to be

implemented. This feature is available in LPC2109/2119/2129/00 devices as well.

n General purpose timers can operate as external event counters.

n 16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.
n 8/16 kB on-chip static RAM.

NXP Semiconductors

n 64/128/256 kB on-chip flash program memory. 128-bit wide interface/accelerator

n In-System Programming (ISP) and In-Application Programming (IAP) via on-chip

n EmbeddedICE-RT interface enables breakpoints and watch points. Interrupt service

n Embedded Trace Macrocell (ETM) enables non-intrusive high speed real-time tracing

n Two interconnected CAN interfaces (one for LPC2109) with advanced acceptance

n Four-channel 10-bit A/D converter with conversion time as low as 2.44 µs.
n Multiple serial interfaces including two UARTs(16C550), Fast I2C-bus (400 kbit/s) and

n 60 MHz maximum CPU clock available from programmable on-chip Phase-Locked

n Vectored Interrupt Controller with configurable priorities and vector addresses.
n Two 32-bit timers (with four capture and four compare channels), PWM unit (six

n Up to forty-six 5 V tolerant general purpose I/O pins. Up to nine edge or level sensitive

n On-chip crystal oscillator with an operating range of 1 MHz to 30 MHz.
n Two low power modes, Idle and Power-down.
n Processor wake-up from Power-down mode via external interrupt.
n Individual enable/disable of peripheral functions for power optimization.
n Dual power supply:

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

enables high speed 60 MHz operation.

bootloader software. Flash programming takes 1 ms per 512 B line. Single sector or
full chip erase takes 400 ms.

routines can continue to execute while the foreground task is debugged with the
on-chip RealMonitor software.

of instruction execution.

filters.

two SPIs.

Loop with settling time of 100 µs.

outputs), Real-Time Clock (RTC) and watchdog.

external interrupt pins available.

u CPU operating voltage range of 1.65 V to 1.95 V (1.8 V ± 0.15 V).
u I/O power supply range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O pads.

3. Ordering information

Table 1. Ordering information

Type number Package

Name Description Version

LPC2109FBD64/00 LQFP64 plastic low profile quad flat package; 64 leads;

body 10 × 10 × 1.4 mm

LPC2109FBD64/01 LQFP64 plastic low profile quad flat package; 64 leads;

body 10 × 10 × 1.4 mm

LPC2119FBD64 LQFP64 plastic low profile quad flat package; 64 leads;

body 10 × 10 × 1.4 mm

LPC2119FBD64/00 LQFP64 plastic low profile quad flat package; 64 leads;

body 10 × 10 × 1.4 mm

LPC2119FBD64/01 LQFP64 plastic low profile quad flat package; 64 leads;

body 10 × 10 × 1.4 mm

LPC2109_2119_2129_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 10 December 2007 2 of 44

SOT314-2

SOT314-2

SOT314-2

SOT314-2

SOT314-2

NXP Semiconductors

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

Table 1. Ordering information

Type number Package

Name Description Version

LPC2129FBD64 LQFP64 plastic low profile quad flat package; 64 leads;

LPC2129FBD64/00 LQFP64 plastic low profile quad flat package; 64 leads;

LPC2129FBD64/01 LQFP64 plastic low profile quad flat package; 64 leads;

…continued

body 10 × 10 × 1.4 mm

body 10 × 10 × 1.4 mm

body 10 × 10 × 1.4 mm

3.1 Ordering options

Table 2. Ordering options

Type number Flash

memory

LPC2109FBD64/00 64 kB 8 kB 1 channel no −40 °C to +85 °C
LPC2109FBD64/01 64 kB 8 kB 1 channel yes −40 °C to +85 °C
LPC2119FBD64 128 kB 16 kB 2 channels no −40 °C to +85 °C
LPC2119FBD64/00 128 kB 16 kB 2 channels no −40 °C to +85 °C
LPC2119FBD64/01 128 kB 16 kB 2 channels yes −40 °C to +85 °C
LPC2129FBD64 256 kB 16 kB 2 channels no −40 °C to +85 °C
LPC2129FBD64/00 256 kB 16 kB 2 channels no −40 °C to +85 °C
LPC2129FBD64/01 256 kB 16 kB 2 channels yes −40 °C to +85 °C

RAM CAN Fast GPIO/

SSP/
Enhanced
UART,ADC,
Timer

Temperature range

SOT314-2

SOT314-2

SOT314-2

LPC2109_2119_2129_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 10 December 2007 3 of 44

NXP Semiconductors

4. Block diagram

TRST

TMS

(2)

(2)

TCK

TDI

(2)

(2)

TDO

RTCK

(2)

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

XTAL2

XTAL1

RESET

P0[30:27],

P0[25:0]

P1[31:16]

EINT[3:0]

4 × CAP0
4 × CAP1
4 × MAT0
4 × MAT1

AIN[3:0]

P0[30:27],

P0[25:0]

P1[31:16]

LPC2109
LPC2119
LPC2129

HIGH-SPEED

(4)

GPI/O

46 PINS TOTAL

ARM7 LOCAL BUS

INTERNAL

SRAM

CONTROLLER

8/16 kB

SRAM

(1)

(1)
(1)
(1)
(1)

(1)

TIMER 0/TIMER 1

A/D CONVERTER

INTERNAL

FLASH

CONTROLLER

64/128/256 kB

FLASH

EXTERNAL

INTERRUPTS

CAPTURE/
COMPARE

GENERAL

PURPOSE I/O

TEST/DEBUG

INTERFACE

ARM7TDMI-S

AHB BRIDGE

AHB TO APB

BRIDGE

PLL

system

MODULE

clock

EMULA TION TRA CE

INTERRUPT

CONTROLLER

AMBA Advanced High-performance

Bus (AHB)

APB

DIVIDER

2

I

C-BUS SERIAL

INTERFACE

SPI1/SSP

(4)

SERIAL

INTERFACE

SPI0 SERIAL

INTERFACE

UART0/UART1

WATCHDOG

TIMER

SYSTEM

FUNCTIONS

VECTORED

AHB

DECODER

V

DD(3V3)

V

DD(1V8)

V

SS

SCL

SDA

SCK1
MOSI1
MISO1
SSEL1

SCK0
MOSI0
MISO0
SSEL0

TXD[1:0]
RXD[1:0]

DSR1
RTS1
DCD1

(1)

(1)

(1)

(1)
(1)
(1)

(1)

(1)
(1)
(1)

(1)
(1)

, DTR1

(1)

(1)

(1)

, CTS1
, RI1

(1)

,

(1)

,

(1)

PWM[6:1]

RD[2:1]

TD[2:1]

(1)

(1)
(1)

CAN INTERFACE 1 AND 2
ACCEPTANCE FILTERS

PWM0

(3)

SYSTEM

CONTROL

REAL-TIME CLOCK

002aad172

(1) Shared with GPIO.
(2) When test/debug interface is used, GPIO/other functions sharing these pins are not available.
(3) Only 1 for LPC2109.
(4) SSP interface and high-speed GPIO are available on LPC2109/01, LPC2119/01, and LPC2129/01 only.

Fig 1. Block diagram

LPC2109_2119_2129_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 10 December 2007 4 of 44

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5. Pinning information

5.1 Pinning

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

DDA(1V8)

P1[27]/TDO

V

646362616059585756555453525150

P0[21]/PWM5/CAP1[3] P1[20]/TRACESYNC

P0[22]/CAP0[0]/MAT0[0] P0[17]/CAP1[2]/SCK1/MAT1[2]

P0[23]/RD2

P1[19]/TRACEPKT3 P0[15]/RI1/EINT2

P0[24]/TD2

V

DDA(3V3)

P1[18]/TRACEPKT2 P0[14]/DCD1/EINT1

P0[25]/RD1 P1[22]/PIPESTAT1

P0[27]/AIN0/CAP0[1]/MAT0[1] P0[12]/DSR1/MAT1[0]

P1[17]/TRACEPKT1 P0[11]/CTS1/CAP1[1]
P0[28]/AIN1/CAP0[2]/MAT0[2] P1[23]/PIPESTAT2
P0[29]/AIN2/CAP0[3]/MAT0[3] P0[10]/RTS1/CAP1[0]

P0[30]/AIN3/EINT3/CAP0[0] P0[9]/RXD1/PWM6/EINT3

P1[16]/TRACEPKT0 P0[8]/TXD1/PWM4

1
2

(1)

3
4

(1)

5
6

V

SS

7
8
9

10

TD1 P0[13]/DTR1/MAT1[1]

11
12
13
14
15
16

171819202122232425262728293031

SS

V

DD(1V8)

V

P0[0]/TXD0/PWM1 XTAL1

P1[31]/TRST XTAL2

P0[1]/RXD0/PWM3/EINT0 P1[28]/TDI

SSA

SSA(PLL)

V

LPC2109
LPC2119
LPC2129

DD(3V3)

V

P0[2]/SCL/CAP0[0] V

P1[29]/TCK

(2)

SS

V

P1[26]/RTCK RESET

P1[25]/EXTIN0 P0[18]/CAP1[3]/MISO1/MAT1[3]

P0[4]/SCK0/CAP0[1] P0[19]/MAT1[2]/MOSI1/CAP1[2]

P0[5]/MISO0/MAT0[1] P1[30]/TMS

P0[3]/SDA/MAT0[0]/EINT1 P0[20]/MAT1[3]/SSEL1/EINT3

DD(3V3)

SS

P0[6]/MOSI0/CAP0.2 V

P0[7]/SSEL0/PWM2/EINT2 V

DD(1V8)

49

32

P1[24]/TRACECLK V

48
47
46

P0[16]/EINT0/MAT0[2]/CAP0[2]
45
44

P1[21]/PIPESTAT0
43

V

DD(3V3)

42

V

SS

41
40
39
38
37
36
35
34
33

002aad173

(1) No TD2 and RD2 for LPC2109.
(2) Pin configuration is identical for devices with and without /00 and /01 suffixes.

Fig 2. Pin configuration

LPC2109_2119_2129_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 10 December 2007 5 of 44

NXP Semiconductors

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

5.2 Pin description

Table 3. Pin description

Symbol Pin Type Description

P0[0] to P0[31] I/O Port 0 is a 32-bit bidirectional I/O port with individual direction controls for each bit.

The operation of port 0 pins depends upon the pin function selected via the Pin
Connect Block. Pins 26 and 31 of port 0 are not available.

P0[0]/TXD0/
PWM1

P0[1]/RXD0/
PWM3/EINT0

P0[2]/SCL/
CAP0[0]

P0[3]/SDA/
MAT0[0]/EINT1

P0[4]/SCK0/
CAP0[1]

P0[5]/MISO0/
MAT0[1]

P0[6]/MOSI0/
CAP0[2]

P0[7]/SSEL0/
PWM2/EINT2

P0[8]/TXD1/
PWM4

P0[9]/RXD1/
PWM6/EINT3

P0[10]/RTS1/
CAP1[0]

P0[11]/CTS1/
CAP1[1]

P0[12]/DSR1/
MAT1[0]

P0[13]/DTR1/
MAT1[1]

P0[14]/DCD1/
EINT1

19 O TXD0 — Transmitter output for UART0.

O PWM1 — Pulse Width Modulator output 1.

21 I RXD0 — Receiver input for UART0.

O PWM3 — Pulse Width Modulator output 3.
I EINT0 — External interrupt 0 input

2

22 I/O SCL — I

I CAP0[0] — Capture input for Timer 0, channel 0.

26 I/O SDA — I

O MAT0[0] — Match output for Timer0, channel 0.
I EINT1 — External interrupt 1 input.

27 I/O SCK0 — Serial clock for SPI0. SPI clock output from master or input to slave.

I CAP0[1] — Capture input for Timer 0, channel 1.

29 I/O MISO0 — Master In Slave OUT for SPI0. Data input to SPI master or data output

from SPI slave.

O MAT0[1] — Match output for Timer0, channel 1.

30 I/O MOSI0 — Master Out Slave In for SPI0. Data output from SPI master or data input

to SPI slave.

I CAP0[2] — Capture input for Timer 0, channel 2.

31 I SSEL0 — Slave Select for SPI0. Selects the SPI interface as a slave.

O PWM2 — Pulse Width Modulator output 2.
I EINT2 — External interrupt 2 input.

33 O TXD1 — Transmitter output for UART1.

O PWM4 — Pulse Width Modulator output 4.

34 I RXD1 — Receiver input for UART1.

O PWM6 — Pulse Width Modulator output 6.
I EINT3 — External interrupt 3 input.

35 O RTS1 — Request to Send output for UART1.

I CAP1[0] — Capture input for Timer 1, channel 0.

37 I CTS1 — Clear to Send input for UART1.

I CAP1[1] — Capture input for Timer 1, channel 1.

38 I DSR1 — Data Set Ready input for UART1.

O MAT1[0] — Match output for Timer1, channel 0.

39 O DTR1 — Data Terminal Ready output for UART1.

O MAT1[1] — Match output for Timer1, channel 1.

41 I DCD1 — Data Carrier Detect input for UART1.

I EINT1 — External interrupt 1 input.

Note: LOW on this pin while
control of the part after reset.

C-bus clock input/output. Open-drain output (for I2C-bus compliance).

2

C-bus data input/output. Open-drain output (for I2C-bus compliance).

RESET is LOW forces on-chip bootloader to take

LPC2109_2119_2129_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 10 December 2007 6 of 44

NXP Semiconductors

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

Table 3. Pin description

Symbol Pin Type Description

P0[15]/RI1/EINT2 45 I RI1 — Ring Indicator input for UART1.

P0[16]/EINT0/
MAT0[2]/CAP0[2]

P0[17]/CAP1[2]/
SCK1/MAT1[2]

P0[18]/CAP1[3]/
MISO1/MAT1[3]

P0[19]/MAT1[2]/
MOSI1/CAP1[2]

P0[20]/MAT1[3]/
SSEL1/EINT3

P0[21]/PWM5/
CAP1[3]

P0[22]/CAP0[0]/
MAT0[0]

P0[23]/RD2 3 I CAN2 receiver input (not available on LPC2109).
P0[24]/TD2 5 O CAN2 transmitter output (not available on LPC2109).
P0[25]/RD1 9 I CAN1 receiver input.
P0[27]/AIN0/

CAP0[1]/MAT0[1]

P0[28]/AIN1/
CAP0[2]/MAT0[2]

P0[29]/AIN2/
CAP0[3]/MAT0[3]

P0[30]/AIN3/
EINT3/CAP0[0]

P1[0] to P1[31] I/O Port 1 is a 32-bit bidirectional I/O port with individual direction controls for each bit.

46 I EINT0 — External interrupt 0 input.

47 I CAP1[2] — Capture input for Timer 1, channel 2.

53 I CAP1[3] — Capture input for Timer 1, channel 3.

54 O MAT1[2] — Match output for Timer 1, channel 2.

55 O MAT1[3] — Match output for Timer 1, channel 3.

1OPWM5 — Pulse Width Modulator output 5.

2ICAP0[0] — Capture input for Timer 0, channel 0.

11 I AIN0 — A/D converter, input 0. This analog input is always connected to its pin.

13 I AIN1 — A/D converter, input 1. This analog input is always connected to its pin.

14 I AIN2 — A/D converter, input 2. This analog input is always connected to its pin.

15 I AIN3 — A/D converter, input 3. This analog input is always connected to its pin.

…continued

I EINT2 — External interrupt 2 input.

O MAT0[2] — Match output for Timer0, channel 2.
I CAP0[2] — Capture input for Timer 0, channel 2.

[1]

I/O SCK1 — Serial Clock for SPI1/SSP

slave.

O MAT1[2] — Match output for Timer1, channel 2.

I/O MISO1 — Master In Slave Out for SPI1/SSP

output from SPI slave.

O MAT1[3] — Match output for Timer1, channel 3.

I/O MOSI1 — Master OutSlaveIn for SPI1/SSP

input to SPI slave.

I CAP1[2] — Capture input for Timer 1, channel 2.

I SSEL1 — Slave Select for SPI1/SSP
I EINT3 — External interrupt 3 input.

I CAP1[3] — Capture input for Timer 1, channel 3.

O MAT0[0] — Match output for Timer 0, channel 0.

I CAP0[1] — Capture input for Timer 0, channel 1.
O MAT0[1] — Match output for Timer 0, channel 1.

I CAP0[2] — Capture input for Timer 0, channel 2.
O MAT0[2] — Match output for Timer 0, channel 2.

I CAP0[3] — Capture input for Timer 0, Channel 3.
O MAT0[3] — Match output for Timer 0, channel 3.

I EINT3 — External interrupt 3 input.
I CAP0[0] — Capture input for Timer 0, channel 0.

The operation of port 1 pins depends upon the pin function selected via the Pin
Connect Block. Pins 0 through 15 of port 1 are not available.

. SPI clock output from master or input to

[1]

[1]

. Data input to SPI master or data

[1]

. Data output from SPI master or data

. Selects the SPI interface as a slave.

LPC2109_2119_2129_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 10 December 2007 7 of 44

NXP Semiconductors

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

Table 3. Pin description

…continued

Symbol Pin Type Description

P1[16]/

16 O Trace Packet, bit 0. Standard I/O port with internal pull-up.

TRACEPKT0
P1[17]/

12 O Trace Packet, bit 1. Standard I/O port with internal pull-up.

TRACEPKT1
P1[18]/

8 O Trace Packet, bit 2. Standard I/O port with internal pull-up.

TRACEPKT2
P1[19]/

4 O Trace Packet, bit 3. Standard I/O port with internal pull-up.

TRACEPKT3
P1[20]/

TRACESYNC

48 O Trace Synchronization. Standard I/O port with internal pull-up.

Note: LOW on this pin while

RESET is LOW, enables pins P1[25:16] to operate as

Trace port after reset.

P1[21]/

44 O Pipeline Status, bit 0. Standard I/O port with internal pull-up.

PIPESTAT0
P1[22]/

40 O Pipeline Status, bit 1. Standard I/O port with internal pull-up.

PIPESTAT1
P1[23]/

36 O Pipeline Status, bit 2. Standard I/O port with internal pull-up.

PIPESTAT2
P1[24]/

32 O Trace Clock. Standard I/O port with internal pull-up.

TRACECLK
P1[25]/EXTIN0 28 I External Trigger Input. Standard I/O with internal pull-up.
P1[26]/RTCK 24 I/O Returned Test Clock output. Extra signal added to the JTAG port. Assists debugger

synchronization when processor frequency varies. Bidirectional pin with internal
pull-up.

Note: LOW on this pin while

RESET is LOW, enables pins P1[31:26] to operate as

Debug port after reset.
P1[27]/TDO 64 O Test Data out for JTAG interface.
P1[28]/TDI 60 I Test Data in for JTAG interface.

1

P1[29]/TCK 56 I Test Clock for JTAG interface. This clock must be slower than

⁄6 of the CPU clock

(CCLK) for the JTAG interface to operate.
P1[30]/TMS 52 I Test Mode Select for JTAG interface.

TRST 20 I Test Reset for JTAG interface.

P1[31]/
TD1 10 O CAN1 transmitter output.
RESET 57 I External reset input; a LOW on this pin resets the device, causing I/O ports and

peripherals to take on their default states, and processor execution to begin at

address 0. TTL with hysteresis, 5 V tolerant.
XTAL1 62 I Input to the oscillator circuit and internal clock generator circuits.
XTAL2 61 O Output from the oscillator amplifier.
V

SS

6, 18, 25,

I Ground: 0 V reference.

42, 50

V

SSA

59 I Analog ground; 0 V reference. This should nominally be the same voltage as VSS,

but should be isolated to minimize noise and error.
V

SSA(PLL)

V

DD(1V8)

58 I PLL analog ground; 0 V reference. This should nominally be the same voltage as

V

, but should be isolated to minimize noise and error.

SS

17, 49 I 1.8 V core power supply; this is the power supply voltage for internal circuitry.

LPC2109_2119_2129_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 10 December 2007 8 of 44

NXP Semiconductors

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

Table 3. Pin description

…continued

Symbol Pin Type Description

V

DDA(1V8)

63 I Analog 1.8 V core power supply; this is the power supply voltage for internal

circuitry. This should be nominally the same voltage as V

isolated to minimize noise and error.
V

DD(3V3)

V

DDA(3V3)

[1] SSP interface available on LPC2109/01, LPC2119/01, and LPC2129/01 only.

23, 43, 51 I 3.3 V pad power supply; this is the power supply voltage for the I/O ports.
7 I Analog 3.3 V pad power supply; this should be nominally the same voltage as

V

but should be isolated to minimize noise and error.

DD(3V3)

DD(1V8)

but should be

LPC2109_2119_2129_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 10 December 2007 9 of 44

NXP Semiconductors

6. Functional description

Details of the LPC2109/2119/2129 systems and peripheral functions are described in the
following sections.

6.1 Architectural overview

The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed Complex
Instruction Set Computers. This simplicity results in a high instruction throughput and
impressive real-time interrupt response from a small and cost-effective processor core.

Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as
Thumb, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:

• The standard 32-bit ARM set.

• A 16-bit Thumb set.

The Thumb set’s 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16-bit processor using 16-bit registers. This is possible because Thumb code
operates on the same 32-bit register set as ARM code.

Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the
performance of an equivalent ARM processor connected to a 16-bit memory system.

6.2 On-chip flash program memory

The LPC2109/2119/2129 incorporate a 64/128/256 kB flash memory system,
respectively. This memory may be used for both code and data storage. Programming of
the flash memory may be accomplished in several ways. It may be programmed In
System via the serial port. The application program may also erase and/or program the
flash while the application is running, allowing a great degree of flexibility for data storage
field firmware upgrades, etc. When on-chip bootloader is used, 60/120/248 kB of flash
memory is available for user code.

The LPC2109/2119/2129 flash memoryprovides a minimum of 100000 erase/write cycles
and 20 years of data retention.

On-chip bootloader (as of revision 1.60) provides Code Read Protection (CRP) for the
LPC2109/2119/2129 on-chip flash memory. When the CRP is enabled, the JTAG debug
port and ISP commands accessing either the on-chip RAM or flash memory are disabled.

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Product data sheet Rev. 06 — 10 December 2007 10 of 44

NXP Semiconductors

However, the ISP flash erase command can be executed at any time (no matter whether
the CRP is on or off). Removal of CRP is achieved by erasure of full on-chip user flash.
With the CRP off, full access to the chip via the JTAG and/or ISP is restored.

6.3 On-chip static RAM

On-chip static RAM may be used for code and/or data storage. The SRAM may be
accessed as 8 bit, 16 bit, and 32 bit. The LPC2109/2119/2129 provide 8 kB of static RAM
for the LPC2109 and 16 kB for the LPC2119 and LPC2129.

6.4 Memory map

The LPC2109/2119/2129 memory maps incorporate several distinct regions, as shown in

Figure 3.

In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either
flash memory (the default) or on-chip static RAM. This is described in Section 6.18

“System control”.

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

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Product data sheet Rev. 06 — 10 December 2007 11 of 44

NXP Semiconductors

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

4.0 GB

3.75 GB

3.5 GB

3.0 GB

2.0 GB

1.0 GB

AHB PERIPHERALS

APB PERIPHERALS

RESERVED ADDRESS SPACE

BOOT BLOCK (RE-MAPPED FROM

ON-CHIP FLASH MEMORY)

RESERVED ADDRESS SPACE

16 kB ON-CHIP STATIC RAM (LPC2119/2129)

8 kB ON-CHIP STATIC RAM (LPC2109)

0xFFFF FFFF
0xF000 0000

0xEFFF FFFF
0xE000 0000

0xDFFF FFFF

0xC000 0000

0x8000 0000
0x7FFF FFFF

0x7FFF E000
0x7FFF DFFF

0x4000 4000
0x4000 3FFF

0x4000 1FFF
0x4000 0000

0x3FFF FFFF

RESERVED ADDRESS SPACE

0x0004 0000
0x0003 FFFF

0x0002 0000
0x0001 FFFF

0x0001 0000
0x0000 FFFF

0x0000 0000

002aad174

0.0 GB

256 kB ON-CHIP FLASH MEMORY (LPC2129)

128 kB ON-CHIP FLASH MEMORY (LPC2119)

64 kB ON-CHIP FLASH MEMORY (LPC2109)

Fig 3. LPC2109/2119/2129 memory map

6.5 Interrupt controller

The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and
categorizes them as Fast Interrupt reQuest (FIQ), vectored Interrupt Request (IRQ), and
non-vectored IRQ as defined by programmable settings. The programmable assignment
scheme means that priorities of interrupts from the various peripherals can be dynamically
assigned and adjusted.

FIQ has the highest priority. If more than one request is assigned to FIQ, the VIC
combines the requests to produce the FIQ signal to the ARM processor. The fastest
possible FIQ latency is achieved when only one request is classified as FIQ because then
the FIQ service routine can simply start dealing with that device. But if more than one
request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC
that identifies which FIQ source(s) is (are) requesting an interrupt.

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Product data sheet Rev. 06 — 10 December 2007 12 of 44

NXP Semiconductors

Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned
to this category. Any of the interrupt requests can be assigned to any of the 16 vectored
IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.

Non-vectored IRQs have the lowest priority.
The VIC combines the requests from all the vectored and non-vectored IRQs to produce

the IRQ signal to the ARM processor. The IRQ service routine can start by reading a
register from the VIC and jumping there. If any of the vectored IRQs are requesting, the
VIC provides the address of the highest-priority requesting IRQs service routine,
otherwise it provides the address of a default routine that is shared by all the non-vectored
IRQs. The default routine can read another VIC register to see what IRQs are active.

6.5.1 Interrupt sources

Table 4 lists the interrupt sources for each peripheralfunction. Each peripheraldevice has

one interrupt line connected to the Vectored Interrupt Controller, but may have several
internal interrupt flags. Individual interrupt flags may also represent more than one
interrupt source.

Table 4. Interrupt sources

Block Flag(s) VIC channel #

WDT Watchdog Interrupt (WDINT) 0

- Reserved for software interrupts only 1
ARM Core EmbeddedICE, DbgCommRx 2
ARM Core EmbeddedICE, DbgCommTx 3
Timer 0 Match 0 to 3 (MR0, MR1, MR2, MR3)

Timer 1 Match 0 to 3 (MR0, MR1, MR2, MR3)

UART0 Rx Line Status (RLS)

UART1 Rx Line Status (RLS)

PWM0 Match 0 to 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6) 8

2

C-bus SI (state change) 9

I
SPI0 SPIF, MODF 10
SPI1 and SSP
PLL PLL Lock (PLOCK) 12
RTC RTCCIF (Counter Increment), RTCALF (Alarm) 13

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

Capture 0 to 3 (CR0, CR1, CR2, CR3)

Capture 0 to 3 (CR0, CR1, CR2, CR3)

Transmit Holding Register empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)

Transmit Holding Register empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)
Modem Status Interrupt (MSI)

[1]

SPIF, MODF and TXRIS, RXRIS, RTRIS, RORRIS 11

4

5

6

7

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Product data sheet Rev. 06 — 10 December 2007 13 of 44

NXP Semiconductors

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

Table 4. Interrupt sources

Block Flag(s) VIC channel #

System Control External Interrupt 0 (EINT0) 14

External Interrupt 1 (EINT1) 15
External Interrupt 2 (EINT2) 16

External Interrupt 3 (EINT3) 17
ADC A/D Converter 18
CAN CAN1, CAN2 and Acceptance Filter 19 to 23

[1] SSP interface available on LPC2109/01, LPC2119/01, and LPC2129/01 only.

…continued

6.6 Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on-chip peripherals. Peripherals should be connected to the appropriate pins
prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any
enabled peripheral function that is not mapped to a related pin should be considered
undefined.

6.7 General purpose parallel I/O (GPIO) and Fast I/O

Device pins that are not connected to a specific peripheral function are controlled by the
parallel I/O registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of the
output register may be read back, as well as the current state of the port pins.

6.7.1 Features

• Bit-level set and clear registers allow a single instruction set or clear of any number of

bits in one port.

• Direction control of individual bits.

• Separate control of output set and clear.

• All I/O default to inputs after reset.

6.7.2 Features added with the Fast GPIO set of registers available on
LPC2109/2119/2129/01 only

• Fast GPIO registers are relocated to the ARM local bus for the fastest possible I/O

timing, enabling port pin toggling up to 3.5 times faster than earlier LPC2000 devices.

• Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

• All Fast GPIO registers are byte addressable.

• Entire port value can be written in one instruction.

• Ports are accessible via either the legacy group of registers (GPIOs) or the group of

registers providing accelerated port access (Fast GPIOs).

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6.8 10-bit ADC

The LPC2109/2119/2129 each contain a single 10-bit successive approximation ADC with
four multiplexed channels.

6.8.1 Features

• Measurement range of 0 V to 3 V.

• Capable of performing more than 400000 10-bit samples per second.

• Burst conversion mode for single or multiple inputs.

• Optional conversion on transition on input pin or Timer Match signal.

6.8.2 ADC features available in LPC2109/2119/2129/01 only

• Every analog input has a dedicated result register to reduce interrupt overhead.

• Every analog input can generate an interrupt once the conversion is completed.

• The ADC pads are 5 V tolerant when configured for digital I/O function(s).

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

6.9 CAN controllers and acceptance filter

The LPC2119 and LPC2129 each contain two CAN controllers, while the LPC2109 has
one CAN controller. The CAN is a serial communications protocol which efficiently
supports distributed real-time control with a very high level of security. Its domain of
application ranges from high-speed networks to low-cost multiplex wiring.

6.9.1 Features

• Data rates up to 1 Mbit/s on each bus.

• 32-bit register and RAM access.

• Compatible with CAN specification 2.0B, ISO 11898-1.

• Global Acceptance Filter recognizes 11-bit and 29-bit Rx identifiers for all CAN buses.

• Acceptance Filter can provide FullCAN-style automatic reception for selected

Standard identifiers.

6.10 UARTs

The LPC2109/2119/2129 each contain two UARTs. In addition to standard transmit and
receive data lines, the UART1 also provides a full modem control handshake interface.

6.10.1 Features

• 16 B Receive and Transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

• Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

• Transmission FIFO control enables implementation of software (XON/XOFF) flow

control on both UARTs.

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NXP Semiconductors

• UART1 is equipped with standard modem interface signals. This module also

6.10.2 UART features available in LPC2109/2119/2129/01 only

Compared to previous LPC2000 microcontrollers, UARTs in LPC2109/2119/2129/01
introduce a fractional baud rate generator for both UARTs, enablingthese microcontrollers
to achieve standard baud rates such as 115200 Bd with any crystal frequency above
2 MHz. In addition, auto-CTS/RTS flow-control functions are fully implemented in
hardware.

• Fractional baud rate generator enables standard baud rates such as 115200 Bd to be

• Auto-bauding.

• Auto-CTS/RTS flow-control fully implemented in hardware.

6.11 I2C-bus serial I/O controller

The I2C-bus is a bidirectional bus for inter-IC control using only two wires: a serial clock
line (SCL), and a serial data line (SDA). Each device is recognized by a unique address
and can operate as either a receiver-only device (e.g. an LCD driver or a transmitter with
the capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus; it can be
controlled by more than one bus master connected to it.

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

provides full support for hardware flow control (auto-CTS/RTS).

achieved with any crystal frequency above 2 MHz.

The I2C-bus implemented in LPC2109/2119/2129 supports a bit rate up to 400 kbit/s (Fast
I2C-bus).

6.11.1 Features

• Standard I

• Easy to configure as Master, Slave, or Master/Slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

• The I

2

C-bus compliant interface.

2

C-bus may be used for test and diagnostic purposes.

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Product data sheet Rev. 06 — 10 December 2007 16 of 44

NXP Semiconductors

6.12 SPI serial I/O controller

The LPC2109/2119/2129 each contain two SPIs. The SPI is a full duplex serial interface,
designed to be able to handle multiple masters and slaves connected to a given bus. Only
a single master and a single slave can communicate on the interface during a given data
transfer. During a data transfer the master always sends a byte of data to the slave, and
the slave always sends a byte of data to the master.

6.12.1 Features

• Compliant with Serial Peripheral Interface (SPI) specification.

• Synchronous, Serial, Full Duplex communication.

• Combined SPI master and slave.

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

• Maximum data bit rate of

1

⁄8 of the input clock rate.

6.12.2 Features available in LPC2109/2119/2129/01 only

• Eight to 16 bits per frame.

• When the SPI interface is used in Master mode, the SSELn pin is not needed (can be

used for a different function).

6.13 SSP controller (LPC2109/2119/2129/01 only)

Remark: This peripheral is available in LPC2109/2119/2129/01 only.

The SSP is a controller capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can
interact with multiple masters and slaves on the bus. Only a single master and a single
slave can communicate on the bus during a given data transfer. Data transfers are in
principle full duplex, with frames of four to 16 bits of data flowing from the master to the
slave and from the slave to the master.

While the SSP and SPI1 peripherals share the same physical pins, it is not possible to
have both of these two peripherals active at the same time. Application can switch on the
fly from SPI1 to SSP and back.

6.13.1 Features

• Compatible with Motorola’s SPI, Texas Instrument’s 4-wire SSI, and National

Semiconductor’s Microwire buses.

• Synchronous serial communication.

• Master or slave operation.

• 8-frame FIFOs for both transmit and receive.

• Four to 16 bits per frame.

6.14 General purpose timers

The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an
externally supplied clock and optionally generate interrupts or perform other actions at
specified timer values, based on four match registers. It also includes four capture inputs

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Product data sheet Rev. 06 — 10 December 2007 17 of 44

NXP Semiconductors

to trap the timer value when an input signal transitions, optionally generating an interrupt.
Multiple pins can be selected to perform a single capture or match function, providing an
application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.

6.14.1 Features

• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

• Timer or external event counter operation

• Four 32-bit capture channels per timer that can take a snapshot of the timer value

• Four 32-bit match registers that allow:

• Four external outputs per timer corresponding to match registers, with the following

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

when an input signal transitions. A capture event may also optionally generate an
interrupt.

– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.

capabilities:

– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.

6.14.2 Features available in LPC2109/2119/2129/01 only

The LPC2109/2119/2129/01 can count external events on one of the capture inputs if the
external pulse lasts at least one half of the period of the PCLK. In this configuration,
unused capture lines can be selected as regular timer capture inputs, or used as external
interrupts.

• Timer can count cycles of either the peripheral clock (PCLK) or an externally supplied

clock.

• When counting cycles of an externally supplied clock, only one of the timer’s capture

inputs can be selected as the timer’s clock. The rate of such a clock is limited to
PCLK / 4. Duration of HIGH/LOW levels on the selected CAP input cannot be shorter
than 1 / (2PCLK).

6.15 Watchdog timer

The purpose of the watchdog is to reset the microcontroller within a reasonable amount of
time if it enters an erroneous state. When enabled, the watchdog will generate a system
reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined
amount of time.

6.15.1 Features

• Internally resets chip if not periodically reloaded.

• Debug mode.

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NXP Semiconductors

• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be

• Incorrect/incomplete feed sequence causes reset/interrupt if enabled.

• Flag to indicate watchdog reset.

• Programmable 32-bit timer with internal pre-scaler.

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

disabled.

• Selectable time period from (T

T

cy(PCLK)

× 4.

6.16 Real-time clock

The RTC is designed to provide a set of counters to measure time when normal or idle
operating mode is selected. The RTC has been designed to use little power, making it
suitable for battery powered systems where the CPU is not running continuously (Idle
mode).

6.16.1 Features

• Measures the passage of time to maintain a calendar and clock.

• Ultra low power design to support battery powered systems.

• Provides Seconds, Minutes, Hours, Dayof Month, Month, Year,Day of Week, and Day

of Year.

• Programmable reference clock divider allows adjustment of the RTC to match various

crystal frequencies.

6.17 Pulse width modulator

The PWM is based on the standard Timer block and inherits all of its features, although
only the PWM function is pinned out on the LPC2109/2119/2129. The Timer is designed
to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or
perform other actions when specified timer values occur,based on seven match registers.
The PWM function is also based on match register events.

cy(PCLK)

× 256 × 4) to (T

cy(PCLK)

× 232× 4) in multiples of

The ability to separately control rising and falling edge locations allows the PWM to be
used for more applications. For instance, multi-phase motor control typically requires three
non-overlapping PWM outputs with individual control of all three pulse widths and
positions.

Two match registers can be used to provide a single edge controlled PWM output. One
match register (MR0) controls the PWM cycle rate, by resetting the count upon match.
The other match register controls the PWM edge position. Additional single edge
controlled PWM outputs require only one match register each, since the repetition rate is
the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a
rising edge at the beginning of each PWM cycle, when an MR0 match occurs.

LPC2109_2119_2129_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 10 December 2007 19 of 44

NXP Semiconductors

Three match registers can be used to provide a PWM output with both edges controlled.
Again, the MR0 match register controls the PWM cycle rate. The other match registers
control the two PWM edge positions. Additional double edge controlled PWM outputs
require only two match registers each, since the repetition rate is the same for all PWM
outputs.

With double edge controlled PWM outputs, specific match registers control the rising and
falling edge of the output. This allows both positive going PWM pulses (when the rising
edge occurs prior to the falling edge), and negative going PWM pulses (when the falling
edge occurs prior to the rising edge).

6.17.1 Features

• Seven match registers allow up to six single edge controlled or three double edge

• The match registers also allow:

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

controlled PWM outputs, or a mix of both types.

– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.

• Supports single edge controlled and/or double edge controlled PWM outputs. Single

edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the
output is a constant LOW. Double edge controlled PWM outputs can have either edge
occur at any position within a cycle. This allows for both positive going and negative
going pulses.

• Pulse period and width can be any number of timer counts. This allows complete

flexibility in the trade-off between resolution and repetition rate. All PWM outputs will
occur at the same repetition rate.

• Double edge controlled PWM outputs can be programmed to be either positive going

or negative going pulses.

• Match register updates are synchronized with pulse outputs to prevent generation of

erroneous pulses. Software must ‘release’ new match values before they can become
effective.

• May be used as a standard timer if the PWM mode is not enabled.

• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

6.18 System control

6.18.1 Crystal oscillator

The oscillator supports crystals in the range of 1 MHz to 30 MHz. The oscillator output
frequency is called f
purposes of rate equations, etc.. f
running and connected. Refer to Section 6.18.2 “PLL” for additional information.

LPC2109_2119_2129_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 10 December 2007 20 of 44

and the ARM processor clock frequency is referred to as CCLK for

osc

and CCLK are the same value unless the PLL is

osc

NXP Semiconductors

6.18.2 PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled
Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the
multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper
frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so
there is an additional divider in the loop to keep the CCO within its frequency range while
the PLL is providing the desired output frequency. The output divider may be set to divide
by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2,
it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and
bypassed following a chip Reset and may be enabled by software. The program must
configure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a
clock source. The PLL settling time is 100 µs.

6.18.3 Reset and wake-up timer

Reset has two sources on the LPC2109/2119/2129: the RESET pin and Watchdog Reset.
The RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of
chip Reset by any source starts the Wake-up Timer (see Wake-up Timer description
below), causing the internal chip reset to remain asserted until the external Reset is
de-asserted, the oscillator is running, a fixed number of clocks have passed, and the
on-chip flash controller has completed its initialization.

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

When the internal Reset is removed, the processor begins executing at address 0, which
is the Reset vector. At that point, all of the processor and peripheral registers have been
initialized to predetermined values.

The wake-up timer ensures that the oscillator and other analog functions required for chip
operation are fully functional before the processor is allowed to execute instructions. This
is important at power on, all types of Reset, and whenever any of the aforementioned
functions are turned off for any reason. Since the oscillator and other functions are turned
off during Power-down mode, any wake-up of the processor from Power-down mode
makes use of the Wake-up Timer.

The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is
safe to begin code execution. When power is applied to the chip, or some event caused
the chip to exit Power-down mode, some time is required for the oscillator to produce a
signal of sufficient amplitude to drive the clock logic. The amount of time depends on
many factors, including the rate of VDD ramp (in the case of power on), the type of crystal
and its electrical characteristics (if a quartz crystal is used), as well as any other external
circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing
ambient conditions.

6.18.4 Code security (Code Read Protection - CRP)

This feature of the LPC2109/2119/2129 allows the user to enable different levels of
security in the system so that access to the on-chip flash and use of the JTAG and ISP
can be restricted. When needed, CRP is invokedby programming a specific pattern into a
dedicated flash location. IAP commands are not affected by the CRP.

There are three levels of the Code Read Protection.

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Product data sheet Rev. 06 — 10 December 2007 21 of 44

NXP Semiconductors

CRP1 disables access to chip via the JTAG and allows partial flash update (excluding
flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is
required and flash field updates are needed but all sectors can not be erased.

CRP2 disables access to chip via the JTAG and only allows full flash erase and update
using a reduced set of the ISP commands.

Running an application with level CRP3 selected fully disables any access to chip via the
JTAG pins and the ISP. This mode effectively disables ISP override using P0[14] pin, too. It
is up to the user’s application to provide (if needed) flash update mechanism using IAP
calls or call reinvoke ISP command to enable flash update via UART0.

CAUTION

Remark: Devices without the suffix /00 or /01 have only a security level equivalent to

CRP2 available.

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.

6.18.5 External interrupt inputs

The LPC2109/2119/2129 include up to nine edge or level sensitive External Interrupt
Inputs as selectable pin functions. When the pins are combined, external events can be
processed as four independent interrupt signals. The External Interrupt Inputs can
optionally be used to wake up the processor from Power-down mode.

6.18.6 Memory mapping control

The Memory Mapping Control alters the mapping of the interrupt vectors that appear
beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip
flash memory, or to the on-chip static RAM. This allows code running in different memory
spaces to have control of the interrupts.

6.18.7 Power control

The LPC2109/2119/2129 support two reduced power modes: Idle mode and Power-down
mode. In Idle mode, execution of instructions is suspended until either a Reset or interrupt
occurs. Peripheral functions continue operation during Idle mode and may generate
interrupts to cause the processor to resume execution. Idle mode eliminates power used
by the processor itself, memory systems and related controllers, and internal buses.

In Power-downmode, the oscillator is shut down and the chip receives no internal clocks.
The processor state and registers, peripheral registers, and internal SRAM values are
preserved throughout Power-down mode and the logic levels of chip output pins remain
static. The Power-downmode can be terminated and normal operation resumed by either
a Reset or certain specific interrupts that are able to function without clocks. Since all
dynamic operation of the chip is suspended, Power-down mode reduces chip power
consumption to nearly zero.

A Power Control for Peripherals feature allows individual peripherals to be turned off if
they are not needed in the application, resulting in additional power savings.

LPC2109_2119_2129_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 10 December 2007 22 of 44

NXP Semiconductors

6.18.8 APB

The APB divider determines the relationship between the processor clock (CCLK) and the
clock used by peripheral devices (PCLK). The APB divider serves two purposes. The first
is to provide peripherals with the desired PCLK via APB so that they can operate at the
speed chosen for the ARM processor. In order to achieve this, the APB may be slowed
down to1⁄2 to1⁄4 of the processor clock rate. Because the APB must work properly at
power-up (and its timing cannot be altered if it does not work since the APB divider control
registers reside on the APB), the default condition at reset is for the APB to run at1⁄4of the
processor clock rate. The second purpose of the APB divider is to allow power savings
when an application does not require any peripherals to run at the full processor rate.
Because the APB divider is connected to the PLL output, the PLL remains active (if it was
running) during Idle mode.

6.19 Emulation and debugging

The LPC2109/2119/2129 support emulation and debugging via a JTAGserial port.A trace
port allows tracing program execution.Debugging and trace functions are multiplexedonly
with GPIOs on Port 1. This means that all communication, timer and interface peripherals
residing on Port 0 are availableduring the developmentand debugging phase as they are
when the application is run in the embedded system itself.

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

6.19.1 EmbeddedICE

Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of
the target system requires a host computer running the debugger software and an
EmbeddedICE protocol convertor.EmbeddedICE protocol convertor converts the Remote
Debug Protocol commands to the JTAG data needed to access the ARM core.

The ARM core has a Debug Communication Channel function built-in. The debug
communication channel allows a program running on the target to communicate with the
host debugger or another separate host without stopping the program flow or even
entering the debug state. The debug communication channel is accessed as a
co-processor 14 by the program running on the ARM7TDMI-S core. The debug
communication channel allows the JTAG port to be used for sending and receiving data
without affecting the normal program flow. The debug communication channel data and
control registers are mapped in to addresses in the EmbeddedICE logic.

The JTAG clock (TCK) must be slower than1⁄6 of the CPU clock (CCLK) for the JTAG
interface to operate.

6.19.2 Embedded trace macrocell

Since the LPC2109/2119/2129 have significant amounts of on-chip memory, it is not
possible to determine how the processor core is operating simply by observing the
external pins. The ETM provides real-time trace capability fordeeply embedded processor
cores. It outputs information about processor execution to the trace port.

The ETM is connected directly to the ARM core and not to the main AMBA system bus. It
compresses the trace information and exports it through a narrow trace port. An external
trace port analyzer must capture the trace information under software debugger control.
Instruction trace (or PC trace) shows the flow of executionof the processor and provides a
list of all the instructions that were executed. Instruction trace is significantly compressed
by only broadcasting branch addresses as well as a set of status signals that indicate the

LPC2109_2119_2129_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 10 December 2007 23 of 44

NXP Semiconductors

pipeline status on a cycle by cycle basis. Trace information generation can be controlled
by selecting the trigger resource. Trigger resources include address comparators,
counters and sequencers. Since trace information is compressed the software debugger
requires a static image of the code being executed. Self-modifying code can not be traced
because of this restriction.

6.19.3 RealMonitor

RealMonitor is a configurable software module, developed by ARM Inc., which enables
real time debug. It is a lightweight debug monitor that runs in the background while users
debug their foreground application. It communicates with the host using the DCC (Debug
Communications Channel), which is present in the EmbeddedICE logic. The
LPC2109/2119/2129 contain a specific configuration of RealMonitor software
programmed into the on-chip flash memory.

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

LPC2109_2119_2129_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 10 December 2007 24 of 44

NXP Semiconductors

7. Limiting values

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

[1]

Symbol Parameter Conditions Min Max Unit

V

DD(1V8)

V

DD(3V3)

V

DDA(3V3)

V

IA

V

I

I

DD

I

SS

T

j

T

stg

P

tot(pack)

supply voltage (1.8 V)
supply voltage (3.3 V)
analog supply voltage (3.3 V) −0.5 +4.6 V
analog input voltage −0.5 +5.1 V
input voltage 5 V tolerant I/O pins

other I/O pins
supply current
ground current
junction temperature - 150 °C
storage temperature
total power dissipation (per

package)

based on package heat

transfer, not devicepower

[2]

−0.5 +2.5 V

[3]

−0.5 +3.6 V

[4][5]

−0.5 +6.0 V

[4][6]

−0.5 V

[7][8]

- 100 mA

[8][9]

- 100 mA

[10]

−65 +150 °C

DD(3V3)

+ 0.5 V

- 1.5 W

consumption

V

esd

electrostatic discharge voltage human body model; all

[11]

−2000 +2000 V

pins

[1] The following applies to Table 5:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless

otherwise noted.
[2] Internal rail.
[3] External rail.
[4] Including voltage on outputs in 3-state mode.
[5] Only valid when the V
[6] Not to exceed 4.6 V.
[7] Per supply pin.
[8] The peak current is limited to 25 times the corresponding maximum current.
[9] Per ground pin.
[10] Dependent on package type.
[11] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

supply voltage is present.

DD(3V3)

LPC2109_2119_2129_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 10 December 2007 25 of 44

NXP Semiconductors

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

8. Static characteristics

Table 6. Static characteristics

T

=−40°C to +85°C for industrial applications, unless otherwise specified.

amb

Symbol Parameter Conditions Min Typ

V

DD(1V8)

V

DD(3V3)

V

DDA(3V3)

supply voltage (1.8 V)
supply voltage (3.3 V)
analog supply voltage

(3.3 V)

Standard port pins,

I

IL

I

IH

I

OZ

LOW-level input current VI= 0 V; no pull-up - - 3 µA
HIGH-level input current VI=V
OFF-state output current VO=0V; VO=V

RESET, RTCK

; no pull-down - - 3 µA

DD(3V3)

;

DD(3V3)

no pull-up/down

I

latch

V
V
V
V
V
V
V
I

OH

I

OL

I

OHS

I
O
IH
IL
hys
OH
OL

I/O latch-up current −(0.5V

(1.5V

DD(3V3)

input voltage
output voltage output active 0 - V
HIGH-level input voltage 2.0 - - V
LOW-level input voltage - - 0.8 V
hysteresis voltage - 0.4 - V
HIGH-level output voltage IOH= −4 mA
LOW-level output voltage IOL= 4 mA
HIGH-level output current VOH=V
LOW-level output current VOL= 0.4 V
HIGH-level short-circuit

VOH=0V

DD(3V3)

); Tj < 125 °C

DD(3V3)

) < VI <

− 0.4 V

output current

I

OLS

LOW-level short-circuit

VOL=V

DD(3V3)

output current

I

pd

I

pu

pull-down current VI=5V
pull-up current VI=0V

V

DD(3V3)

< VI < 5 V

Power consumption LPC2109/00, LPC2119, LPC2119/00, LPC2129, LPC2129/00

I

DD(act)

active mode supply
current

V

DD(1V8)

= 1.8 V;
CCLK = 60 MHz;
T

=25°C; code

amb

while(1){}

executed from flash; all

I

DD(pd)

Power-down mode supply
current

peripherals enabled via
PCONP
configured to run

V
T

V
T

DD(1V8)

=25°C

amb
DD(1V8)

=85°C

amb

[11]

register but not

= 1.8 V;

= 1.8 V;

[2]

1.65 1.8 1.95 V

[3]

3.0 3.3 3.6 V

2.5 3.3 3.6 V

--3µA

100 - - mA

[4][5][6]

0 - 5.5 V

[7]

V

[7]

- - 0.4 V

[7]

−4 --mA

[7]

4 --mA

[8]

--−45 mA

[8]

- - 50 mA

[9]

10 50 150 µA

[10]

−15 −50 −85 µA

[9]

000µA

− 0.4 - - V

DD(3V3)

-60-mA

-10-µA

- 110 500 µA

[1]

Max Unit

DD(3V3)

V

LPC2109_2119_2129_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 10 December 2007 26 of 44

NXP Semiconductors

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

Table 6. Static characteristics

T

=−40°C to +85°C for industrial applications, unless otherwise specified.

amb

…continued

Symbol Parameter Conditions Min Typ

Power consumption LPC2109/01, LPC2119/01, LPC2129/01

I

DD(act)

active mode supply
current

V

DD(1V8)

= 1.8 V;
CCLK = 60 MHz;
T

=25°C; code

amb

- 41.5 - mA

while(1){}

executed from flash; all

I

DD(idle)

I

DD(pd)

Idle mode supply current V

Power-down mode supply
current

2

C-bus pins

I

V

IH

V

IL

V

hys

V

OL

I

LI

HIGH-level input voltage 0.7V
LOW-level input voltage - - 0.3V
hysteresis voltage - 0.5V
LOW-level output voltage I
input leakage current VI=V

Oscillator pins

V

i(XTAL1)

input voltage on pin
XTAL1

V

o(XTAL2)

output voltage on pin
XTAL2

peripherals enabled via
PCONP
configured to run

CCLK = 60 MHz;
T

executed from flash; all
peripherals enabled via
PCONP
configured to run

V
T

V
T

V

[11]

register but not

= 1.8 V;

DD(1V8)

=25°C;

amb

[11]

register but not

= 1.8 V;

DD(1V8)

=25°C

amb

= 1.8 V;

DD(1V8)

=85°C

amb

= 3 mA

OLS

DD(3V3)

= 5 V - 10 22 µA

I

-9-mA

-10-µA

- - 180 µA

DD(3V3)

[7]

- - 0.4 V

[12]

-24µA

--V

0 - 1.8 V

0 - 1.8 V

[1]

DD(3V3)

Max Unit

DD(3V3)

V

-V

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.
[2] Internal rail.
[3] External rail.
[4] Including voltage on outputs in 3-state mode.
[5] V
[6] 3-state outputs go into 3-state mode when V
[7] Accounts for 100 mV voltage drop in all supply lines.
[8] Only allowed for a short time period.
[9] Minimum condition for VI= 4.5 V, maximum condition for VI= 5.5 V.
[10] Applies to P1[25:16].
[11] See
[12] To VSS.

LPC2109_2119_2129_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 10 December 2007 27 of 44

supply voltages must be present.

DD(3V3)

LPC2119/2129/2194/2292/2294 User Manual

DD(3V3)

is grounded.

.

NXP Semiconductors

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

Table 7. ADC static characteristics

V

= 2.5 V to 3.6 V unless otherwise specified; T

DDA

4.5 MHz.

Symbol Parameter Conditions Min Typ Max Unit

V

IA

C

ia

analog input voltage 0 - V
analog input

capacitance

E

D

differential linearity

error
E
E
E
E

L(adj)
O
G
T

integral non-linearity

offset error

gain error

absolute error

=−40°C to +85°C unless otherwise specified. ADC frequency

amb

DDA

--1pF

[1][2][3]

--±1 LSB

[1][4]

--±2 LSB

[1][5]

--±3 LSB

[1][6]

--±0.5 %

[1][7]

--±4 LSB

V

[1] Conditions: V
[2] The ADC is monotonic, there are no missing codes.
[3] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 4.
[4] The integral non-linearity (E

appropriate adjustment of gain and offset errors. See Figure 4.

[5] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the

ideal curve. See Figure 4.

[6] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset

error, and the straight line which fits the ideal transfer curve. See Figure 4.

[7] The absolute voltage error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the

non-calibrated ADC and the ideal transfer curve. See Figure 4.

SSA

=0V, V

= 3.3 V.

DDA

) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

L(adj)

LPC2109_2119_2129_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 10 December 2007 28 of 44

NXP Semiconductors

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

code

out

1023

1022

1021

1020

1019

1018

offset

error

(2)

7

(1)

6

5

(5)

4

(4)

3

(3)

2

gain
error

E

E

O

G

1

0

offset

error

E

O

1 LSB
(ideal)

7123456

VIA (LSB

ideal

10241018 1019 1020 1021 1022 1023

)

− V

V

DDA

1 LSB =

SSA

1024

002aaa668

(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential linearity error (ED).
(4) Integral non-linearity (E

L(adj)

).

(5) Center of a step of the actual transfer curve.

Fig 4. ADC characteristics

LPC2109_2119_2129_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 10 December 2007 29 of 44

NXP Semiconductors

8.1 Power consumption measurements for LPC2109/01, LPC2119/01, LPC2129/01 devices

The power consumption measurements represent typical values for the given conditions.
The peripherals were enabled through the PCONP register, but for these measurements,
the peripherals were not configured to run. Peripherals were disabled through the PCONP
register.Refer to the
PCONP register.

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

LPC2119/2129/2194/2292/2294 User Manual

for a description of the

45

I

DD(act)

(mA)

35

25

15

5

12 60442820 5236

Test conditions: Active mode entered executing code from on-chip flash; PCLK =
T

=25°C; core voltage 1.8 V.

amb

Fig 5. Typical LPC2109/01 I

45

I

DD(act)

(mA)

35

all peripherals enabled
all peripherals disabled

measured at different frequencies

DD(act)

60 MHz

48 MHz

CCLK

002aad127

frequency (MHz)

⁄4;

002aad128

25

15

12 MHz

5

1.65 1.951.851.751.70 1.901.80

Test conditions: Active mode entered executing code from on-chip flash; PCLK =
T

= 25 °C; core voltage 1.8 V; all peripherals enabled.

amb

Fig 6. Typical LPC2109/01 I

LPC2109_2119_2129_6 © NXP B.V. 2007. All rights reserved.

measured at different voltages

DD(act)

CCLK

⁄4;

voltage (V)

Product data sheet Rev. 06 — 10 December 2007 30 of 44

NXP Semiconductors

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

10

I

DD(idle)

(mA)

8

6

4

2

0

12 60442820 5236

Test conditions: Idle mode entered executing code from on-chip flash; PCLK =
T

= 25 °C; core voltage 1.8 V.

amb

Fig 7. Typical LPC2109/01 I

10

I

DD(idle)

(mA)

7.5

all peripherals enabled
all peripherals disabled

measured at different frequencies

DD(idle)

60 MHz

48 MHz

CCLK

002aad129

frequency (MHz)

⁄4;

002aad130

5.0

2.5

0

1.65 1.951.851.751.70 1.901.80

Test conditions: Idle mode entered executing code from on-chip flash; PCLK =
T

=25°C; core voltage 1.8 V; all peripherals enabled.

amb

Fig 8. Typical LPC2109/01 I

LPC2109_2119_2129_6 © NXP B.V. 2007. All rights reserved.

measured at different voltages

DD(idle)

12 MHz

CCLK

voltage (V)

⁄4;

Product data sheet Rev. 06 — 10 December 2007 31 of 44

NXP Semiconductors

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

45

I

DD(act)

(mA)

35

all peripherals enabled

25

15

5

12 60442820 5236

all peripherals disabled

Test conditions: Active mode entered executing code from on-chip flash; PCLK =
T

=25°C; core voltage 1.8 V.

amb

Fig 9. Typical LPC2119/01 and LPC2129/01 I

50

I

DD(act)

(mA)

40

measured at different frequencies

DD(act)

60 MHz

48 MHz

CCLK

002aad131

frequency (MHz)

⁄4;

002aad132

30

20

10

0

1.65 1.951.851.751.70 1.901.80

Test conditions: Active mode entered executing code from on-chip flash; PCLK =
T

= 25 °C; core voltage 1.8 V; all peripherals enabled.

amb

Fig 10. Typical LPC2119/01 and LPC2129/01 I

12 MHz

measured at different voltages

DD(act)

CCLK

voltage (V)

⁄4;

LPC2109_2119_2129_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 10 December 2007 32 of 44

NXP Semiconductors

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

10

I

DD(idle)

(mA)

8

all peripherals enabled

6

4

2

0

12 60442820 5236

all peripherals disabled

Test conditions: Idle mode entered executing code from on-chip flash; PCLK =
T

= 25 °C; core voltage 1.8 V.

amb

Fig 11. Typical LPC2119/01 and LPC2129/01 I

10

I

DD(idle)

(mA)

8

measured at different frequencies

DD(idle)

60 MHz

48 MHz

CCLK

002aad133

frequency (MHz)

⁄4;

002aad134

6

4

2

0

1.65 1.951.851.751.70 1.901.80

Test conditions: Idle mode entered executing code from on-chip flash; PCLK =
T

=25°C; core voltage 1.8 V; all peripherals enabled.

amb

Fig 12. Typical LPC2119/01 and LPC2129/01 I

12 MHz

measured at different voltages

DD(idle)

CCLK

voltage (V)

⁄4;

LPC2109_2119_2129_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 10 December 2007 33 of 44

NXP Semiconductors

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

45

I

DD(act)

(mA)

35

25

15

5

1.65 1.951.851.751.70 1.901.80

60 MHz

48 MHz

12 MHz

Test conditions: Active mode entered executing code from on-chip flash; PCLK =
Temp = 25 °C; core voltage 1.8 V; all peripherals disabled.

Fig 13. Typical LPC2109/01, LPC2119/01, and LPC2129/01 I

8

I

DD(idle)

(mA)

6

60 MHz

CCLK

⁄4;

measured at different voltages

DD(act)

002aad135

voltage (V)

002aad136

48 MHz

4

2

0

1.65 1.951.851.751.70 1.901.80

12 MHz

Test conditions: Idle mode entered executing code from on-chip flash; PCLK =
Temp = 25 °C; core voltage 1.8 V; all peripherals disabled.

Fig 14. Typical LPC2109/01, LPC2119/01, and LPC2129/01 I

CCLK

⁄4;

measured at different voltages

DD(idle)

voltage (V)

LPC2109_2119_2129_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 10 December 2007 34 of 44

NXP Semiconductors

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

45

I

DD(act)

(mA)

35

25

15

5

−40 856010 35−15

60 MHz

48 MHz

12 MHz

Test conditions: Active mode entered executing code from on-chip flash; PCLK =
core voltage 1.8 V; all peripherals disabled.

Fig 15. Typical LPC2109/01, LPC2119/01, and LPC2129/01 I

I

DD(idle)

(mA)

6

5

60 MHz

48 MHz

CCLK

⁄4;

measured at different temperatures

DD(act)

002aad137

temperature (°C)

002aad138

4

3

2

1

−40 856010 35−15

12 MHz

Test conditions: Idle mode entered executing code from on-chip flash; PCLK =
core voltage 1.8 V; all peripherals disabled.

Fig 16. Typical LPC2109/01, LPC2119/01, and LPC2129/01 I

CCLK

⁄4;

measured at different temperatures

DD(idle)

temperature (°C)

LPC2109_2119_2129_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 10 December 2007 35 of 44

NXP Semiconductors

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

200

I

DD(pd)

(µA)

160

120

80

40

0

−40 856010 35−15

Test conditions: Power-down mode entered executing code from on-chip flash.

Fig 17. Typical LPC2109/01, LPC2119/01, and LPC2129/01 core power-down current I

temperatures

Table 8. Typical LPC2109/01 peripheral power consumption in active mode

Core voltage 1.8 V; T

=25°C; all measurements inµA; PCLK =

amb

Peripheral CCLK = 12 MHz CCLK = 48 MHz CCLK = 60 MHz

Timer0 43 141 184
Timer1 46 150 180
UART0 98 320 398
UART1 103 351 421
PWM0 103 341 407

2

C-bus 9 37 53

I
SPI0/1 6 27 29
RTC165578
ADC 33 128 167
CAN1 230 764 914

002aad139

1.95 V

1.8 V

1.65 V

temperature (°C)

measured at different

DD(pd)

CCLK

⁄

.

4

Table 9. Typical LPC2119/01 and LPC2129/01 peripheral power consumption in active

mode

Core voltage 1.8 V; T

=25°C; all measurements inµA; PCLK =

amb

CCLK

⁄

.

4

Peripheral CCLK = 12 MHz CCLK = 48 MHz CCLK = 60 MHz

Timer0 43 141 184
Timer1 46 150 180
UART0 98 320 398
UART1 103 351 421
PWM0 103 341 407

2

C-bus 9 37 53

I
SPI0/1 6 27 29

LPC2109_2119_2129_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 10 December 2007 36 of 44

NXP Semiconductors

Table 9. Typical LPC2119/01 and LPC2129/01 peripheral power consumption in active

Core voltage 1.8 V; T

Peripheral CCLK = 12 MHz CCLK = 48 MHz CCLK = 60 MHz

RTC165578
ADC 33 128 167
CAN1/2 229 771 914

mode

…continued

=25°C; all measurements inµA; PCLK =

amb

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

CCLK

⁄

.

4

LPC2109_2119_2129_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 10 December 2007 37 of 44

NXP Semiconductors

9. Dynamic characteristics

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

Table 10. Dynamic characteristics

T

=−40°C to +85°C for industrial applications; V

amb

DD(1V8)

, V

over specified ranges.

DD(3V3)

[1]

Symbol Parameter Conditions Min Typ Max Unit

External clock

f

osc

oscillator frequency supplied by an external

1 - 50 MHz

oscillator (signal generator)
external clock frequency

1 - 30 MHz
supplied by an external
crystal oscillator

external clock frequency if

10 - 25 MHz
on-chip PLL is used

external clock frequency if

10 - 25 MHz
on-chip bootloader is used
for initial code download

T

cy(clk)

t

CHCX

t

CLCX

t

CLCH

t

CHCL

clock cycle time 20 - 1000 ns
clock HIGH time T
clock LOW time T

× 0.4 - - ns

cy(clk)

× 0.4 - - ns

cy(clk)

clock rise time - - 5 ns
clock fall time - - 5 ns

Port pins (except P0[2] and P0[3])

t

r

t

f

2

C-bus pins (P0[2] and P0[3])

I

t

f

rise time - 10 - ns
fall time - 10 - ns

fall time VIH to V

IL

[2]

20 + 0.1 × Cb--ns

[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Bus capacitance Cb in pF, from 10 pF to 400 pF.

LPC2109_2119_2129_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 10 December 2007 38 of 44

NXP Semiconductors

9.1 Timing

Fig 18. External clock timing

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

− 0.5 V

V

DD

0.45 V

0.2V

0.2V

DD

+ 0.9 V

DD

− 0.1 V

t

CHCL

t

CLCX

T

cy(clk)

t

CHCX

t

CLCH

002aaa907

LPC2109_2119_2129_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 10 December 2007 39 of 44

NXP Semiconductors

10. Package outline

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm

c

y

X

A

48 33

49

64

pin 1 index

1

16

Z

32

E

e

H

E

E

w M

b

p

17

A

2

A

A

1

detail X

SOT314-2

(A )

3

θ

L

p

L

Z

e

DIMENSIONS (mm are the original dimensions)

A

UNIT

mm

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE
VERSION

SOT314-2 MS-026136E10

A1A2A3bpcE

max.

0.20

0.05

1.45

1.35

IEC JEDEC JEITA

1.6

b

0.25

w M

p

D

H

D

0.27

0.17

D

(1)

(1) (1)(1)

D

0.18

0.12

10.1

10.1

9.9

9.9

REFERENCES

v M

A

B

v M

B

0 2.5 5 mm

scale

eHELL

H

D

12.15

12.15

0.5

11.85

11.85

0.75

0.45

Zywv θ

p

0.12 0.11 0.2

EUROPEAN

PROJECTION

Z

D

1.45

1.05

E

1.45

7

1.05

0

ISSUE DATE

00-01-19
03-02-25

o
o

Fig 19. Package outline SOT314-2 (LQFP64)

LPC2109_2119_2129_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 10 December 2007 40 of 44

NXP Semiconductors

11. Abbreviations

Table 11. Abbreviations

Acronym Description

ADC Analog-to-Digital Converter
AMBA Advanced Microcontroller Bus Architecture
APB Advanced Peripheral Bus
CAN Controller Area Network
CPU Central Processing Unit
DCC Debug Communications Channel
FIFO First In, First Out
GPIO General Purpose Input/Output
I/O Input/Output
PLL Phase-Locked Loop
PWM Pulse Width Modulator
RAM Random Access Memory
SPI Serial Peripheral Interface
SRAM Static Random Access Memory
SSI Synchronous Serial Interface
SSP Synchronous Serial Port
TTL Transistor-Transistor Logic
UART Universal Asynchronous Receiver/Transmitter

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

LPC2109_2119_2129_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 10 December 2007 41 of 44

NXP Semiconductors

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

12. Revision history

Table 12. Revision history

Document ID Release date Data sheet status Change notice Supersedes

LPC2109_2119_2129_6 20071210 Product data sheet - LPC2109_2119_2129_5
Modifications:

LPC2109_2119_2129_5 20070627 Product data sheet - LPC2119_2129_4
LPC2119_2129_4 20060714 Product data sheet - LPC2119_2129-03
LPC2119_2129-03 20041222 Product data - LPC2119_2129-02
LPC2119_2129-02 20040202 Preliminary data - LPC2119_2129-01
LPC2119_2129-01 20031118 Preliminary data - -

• Type number LPC2109FBD64/01 has been added.

• Type number LPC2119FBD64/01 has been added.

• Type number LPC2129FBD64/01 has been added.

• Details introduced with /01 devices on new peripherals/features (Fast I/O Ports, SSP, CRP)

and enhancements to existing ones (UART0/1, Timers, ADC, and SPI) have been added.

• Power measurements for LPC2109/2119/2129/01 devices have been added.

• Description of JTAG pin TCK has been updated.

LPC2109_2119_2129_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 10 December 2007 42 of 44

NXP Semiconductors

13. Legal information

13.1 Data sheet status

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

Document status

Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] Theproduct status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL

[1][2]

Product status

13.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.

13.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However,NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.

Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected

[3]

http://www.nxp.com.

Definition

to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.

Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at

http://www.nxp.com/profile/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyanceor implication of any license under any copyrights, patents
or other industrial or intellectual property rights.

13.4 Trademarks

Notice: All referenced brands, product names, servicenames and trademarks
are the property of their respective owners.

I2C-bus — logo is a trademark of NXP B.V.

14. Contact information

For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [e-mail]

LPC2109_2119_2129_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 10 December 2007 43 of 44

NXP Semiconductors

15. Contents

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

1 General description . . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.1 Key features brought by LPC2109/2119/2129/01

devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.2 Key features common for all devices . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

3.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3

4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

6 Functional description . . . . . . . . . . . . . . . . . . 10

6.1 Architectural overview. . . . . . . . . . . . . . . . . . . 10

6.2 On-chip flash program memory . . . . . . . . . . . 10

6.3 On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 11

6.4 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 11

6.5 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 12

6.5.1 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 13

6.6 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 14

6.7 General purpose parallel I/O (GPIO) and

Fast I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.7.2 Features added with the Fast GPIO set of
registers available on LPC2109/2119/2129/01

only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.8 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.8.2 ADCfeaturesavailablein LPC2109/2119/2129/01

only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.9 CAN controllers and acceptance filter . . . . . . 15

6.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.10 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.10.2 UART features available in

LPC2109/2119/2129/01 only . . . . . . . . . . . . . 16

6.11 I

2

C-bus serial I/O controller . . . . . . . . . . . . . . 16

6.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.12 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 17

6.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.12.2 Features available in LPC2109/2119/2129/01

only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.13 SSP controller (LPC2109/2119/2129/01 only) 17

6.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.14 General purpose timers . . . . . . . . . . . . . . . . . 17

6.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.14.2 Features available in LPC2109/2119/2129/01

only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.15 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 18

6.15.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.16 Real-time clock. . . . . . . . . . . . . . . . . . . . . . . . 19

6.16.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.17 Pulse width modulator . . . . . . . . . . . . . . . . . . 19

6.17.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.18 System control . . . . . . . . . . . . . . . . . . . . . . . . 20

6.18.1 Crystal oscillator. . . . . . . . . . . . . . . . . . . . . . . 20

6.18.2 PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.18.3 Reset and wake-up timer. . . . . . . . . . . . . . . . 21

6.18.4 Code security (Code Read Protection - CRP) 21

6.18.5 External interrupt inputs. . . . . . . . . . . . . . . . . 22

6.18.6 Memory mapping control . . . . . . . . . . . . . . . . 22

6.18.7 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.18.8 APB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.19 Emulation and debugging. . . . . . . . . . . . . . . . 23

6.19.1 EmbeddedICE . . . . . . . . . . . . . . . . . . . . . . . . 23

6.19.2 Embedded trace macrocell . . . . . . . . . . . . . . 23

6.19.3 RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 25

8 Static characteristics . . . . . . . . . . . . . . . . . . . 26

8.1 Power consumption measurements for
LPC2109/01, LPC2119/01, LPC2129/01

devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

9 Dynamic characteristics . . . . . . . . . . . . . . . . . 38

9.1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 40

11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 41

12 Revision history . . . . . . . . . . . . . . . . . . . . . . . 42

13 Legal information . . . . . . . . . . . . . . . . . . . . . . 43

13.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 43

13.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

13.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 43

13.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 43

14 Contact information . . . . . . . . . . . . . . . . . . . . 43

15 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.

© NXP B.V. 2007. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [e-mail]

Date of release: 10 December 2007

Document identifier: LPC2109_2119_2129_6