NXP LPC 2103 FBD48 Datasheet

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers; 8 kB/16 kB/32 kB
flash with ISP/IAP, fast ports and 10-bit ADC

Rev. 04 — 2 June 2009 Product data sheet

1. General description

The LPC2101/02/03 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with
real-time emulation that combines the microcontroller with 8 kB, 16 kB or 32 kB of
embedded high-speed flash memory. A 128-bit wide memory interface and a unique
accelerator architecture enable 32-bit code execution at the maximum clock rate. For
critical performance in interrupt service routines and DSP algorithms, this increases
performance up to 30 % over Thumb mode. For critical code size applications, the
alternative 16-bit Thumb mode reduces code by more than 30 % with minimal
performance penalty.

Due to their tiny size and low power consumption, the LPC2101/02/03 are ideal for
applications where miniaturization is a key requirement. A blendof serial communications
interfaces ranging from multiple UARTs, SPI to SSP and two I2C-buses, combined with
on-chip SRAM of 2 kB/4 kB/8 kB, make these devices very well suited for communication
gateways and protocol converters. The superior performance also makes these devices
suitable for use as math coprocessors. Various 32-bit and 16-bit timers, an improved
10-bit ADC, PWM features through output match on all timers,and32 fastGPIO lines with
up to nine edge or level sensitive external interrupt pins make these microcontrollers
particularly suitable for industrial control and medical systems.

2. Features

2.1 Enhanced features

2.2 Key features

Enhanced features are available in parts LPC2101/02/03 labelled Revision A and higher:

n Deep power-down mode with option to retain SRAM memory and/or RTC.
n Three levels of flash Code Read Protection (CRP) implemented.

n 16-bit/32-bit ARM7TDMI-S microcontroller in tiny LQFP48 and HVQFN48 packages.
n 2 kB/4 kB/8 kB of on-chip static RAM and 8 kB/16 kB/32 kB of on-chip flash program

memory. 128-bit wide interface/accelerator enables high-speed 70 MHz operation.

n ISP/IAP via on-chip bootloader software. Single flash sector or full chip erase in

100 ms and programming of 256 bytes in 1 ms.

n EmbeddedICE-RT offers real-time debugging with the on-chip RealMonitor software.
n The 10-bit ADC provides eight analog inputs, with conversion times as low as 2.44 µs

per channel and dedicated result registers to minimize interrupt overhead.

n Two 32-bit timers/external event counters with combined seven capture and seven

compare channels.

NXP Semiconductors

n Two 16-bit timers/external event counters with combined three capture and seven

n Low power Real-Time Clock (RTC) with independent power and dedicated 32 kHz

n Multiple serial interfaces including two UARTs (16C550), two Fast I2C-buses

n Vectored interrupt controller with configurable priorities and vector addresses.
n Up to thirty-two, 5 V tolerant fast general purpose I/O pins.
n Up to 13 edge or level sensitive external interrupt pins available.
n 70 MHz maximum CPU clock available from programmable on-chip PLL with a

n On-chip integrated oscillator operates with an external crystal in the range from 1 MHz

n Power saving modes include Idle mode, Power-down mode with RTC active, and

n Individual enable/disable of peripheral functions as well as peripheral clock scaling for

n Processor wake-up from Power-down and Deep power-down (Revision A and higher)

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

compare channels.

clock input.

(400 kbit/s), SPI and SSP with buffering and variable data length capabilities.

possible input frequency of 10 MHz to 25 MHz and a settling time of 100 µs.

to 25 MHz.

Power-down mode.

additional power optimization.

mode via external interrupt or RTC.

3. Ordering information

Table 1. Ordering information

Type number Package

Name Description Version

LPC2101FBD48 LQFP48 plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2
LPC2102FBD48 LQFP48 plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2
LPC2103FBD48 LQFP48 plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2
LPC2102FHN48 HVQFN48 plastic thermal enhanced very thin quad flat package; no leads;

48 terminals; body 7 × 7 × 0.85 mm

LPC2103FHN48 HVQFN48 plastic thermal enhanced very thin quad flat package; no leads;

48 terminals; body 7 × 7 × 0.85 mm

LPC2103FHN48H HVQFN48 plastic thermal enhanced very thin quad flat package; no leads;

48 terminals; body 6 × 6 × 0.85 mm

3.1 Ordering options

Table 2. Ordering options

Type number Flash memory RAM ADC Temperature

LPC2101FBD48 8 kB 2 kB 8 inputs −40 to +85
LPC2102FBD48 16 kB 4 kB 8 inputs −40 to +85
LPC2103FBD48 32 kB 8 kB 8 inputs −40 to +85
LPC2102FHN48 16 kB 4 kB 8 inputs −40 to +85
LPC2103FHN48 32 kB 8 kB 8 inputs −40 to +85
LPC2103FHN48H 32 kB 8 kB 8 inputs −40 to +85

SOT619-7

SOT619-7

SOT778-3

range (°C)

LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 04 — 2 June 2009 2 of 37

NXP Semiconductors

4. Block diagram

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

P0[31:0]

EINT2 to
EINT0

3 × CAP0
4 × CAP1
3 × CAP2
3 × MAT0
4 × MAT1
3 × MAT2
4 × MAT3

AD0[7:0]

TMS

TRST

LPC2101/2102/2103

HIGH SPEED

GENERAL

PURPOSE I/O

ARM7 local bus

INTERNAL

SRAM

CONTROLLER

2 kB/4 kB/

8 kB SRAM

(1)

(1)
(1)
(1)
(1)
(1)
(1)
(1)

CAPTURE/COMPARE

EXTERNAL COUNTER

8 kB

BOOT ROM

MEMORY

ACCELERATOR

8 kB/16 kB/

32 kB FLASH

EXTERNAL

INTERRUPTS

TIMER 0/TIMER 1/

TIMER 2/TIMER 3

ADC

TEST/DEBUG

INTERFACE

ARM7TDMI-S

AHB BRIDGE

AHB TO APB

TDI

TCK

BRIDGE

TDO

system

clock

AMBA AHB

(Advanced High-performance Bus)

APB (ARM

peripheral bus)

XTAL2 V

XTAL1

PLL

2

C-BUS SERIAL

I

INTERFACES 0 AND 1

SPI AND SSP

SERIAL INTERFACES

UART0/UART1

RST V

SYSTEM

FUNCTIONS

VECTORED

INTERRUPT

CONTROLLER

DD(3V3)

V

DD(1V8)

SS

SCL0, SCL1

SDA0, SDA1

SCK0, SCK1
MOSI0, MOSI1
MISO0, MISO1
SSEL0, SSEL1

TXD0, TXD1
RXD0, RXD1

DSR1, CTS1,
RTS1, DTR1
DCD1, RI1

(1)

(1)

(1)

(1)
(1)
(1)

(1)

(1)

P0[31:0]

GENERAL

PURPOSE I/O

WATCHDOG

TIMER

REAL-TIME CLOCK

SYSTEM CONTROL

002aab814

RTCX1
RTCX2
VBAT

(1) Pins shared with GPIO.

Fig 1. Block diagram

LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 04 — 2 June 2009 3 of 37

NXP Semiconductors

5. Pinning information

5.1 Pinning

Single-chip 16-bit/32-bit microcontrollers

SS

DDA

P0.14/DCD1/SCK1/EINT1

4847464544434241403938

DD(3V3)

V

LPC2101/02/03

P0.25/AD0.6

P0.12/DSR1/MAT1.0/AD0.5
37

P0.19/MAT1.2/MISO1 P0.11/CTS1/CAP1.1/AD0.4
P0.20/MAT1.3/MOSI1 P0.10/RTS1/CAP1.0/AD0.3
P0.21/SSEL1/MAT3.0 P0.24/AD0.2

V

DD(1V8)

P0.27/TRST/CAP2.0 P0.8/TXD1/MAT2.1

P0.28/TMS/CAP2.1 P0.7/SSEL0/MAT2.0

P0.29/TCK/CAP2.2 DBGSEL

1
2
3
4

VBAT P0.23/AD0.1

5
6

RST V

7

V

SS

8

9
10
11

XTAL1 RTCK

12

XTAL2 RTCX2

1314151617181920212223

P0.0/TXD0/MAT3.1 P0.18/CAP1.3/SDA1

LPC2101FBD48
LPC2102FBD48
LPC2103FBD48

DD(3V3)

V

P0.31/TDO P0.15/RI1/EINT2

P0.30/TDI/MAT3.3 P0.16/EINT0/MAT0.2

P0.1/RXD0/MAT3.2 P0.17/CAP1.2/SCL1

P0.2/SCL0/CAP0.0 V

SS

V

RTCX1 P0.13/DTR1/MAT1.1

P0.4/SCK0/CAP0.1 P0.26/AD0.7

P0.3/SDA0/MAT0.0 V

36
35
34
33
32

P0.22/AD0.0

31

SSA

30

P0.9/RXD1/MAT2.2
29
28
27
26
25

24

002aab821

P0.6/MOSI0/CAP0.2

P0.5/MISO0/MAT0.1

Fig 2. Pin configuration (LQFP48)

LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 04 — 2 June 2009 4 of 37

NXP Semiconductors

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

terminal 1

index area

P0.19/MAT1.2/MISO1
P0.20/MAT1.3/MOSI1
P0.21/SSEL1/MAT3.0

VBAT

V

DD(1V8)

RST

V

SS

P0.27/TRST/CAP2.0

P0.28/TMS/CAP2.1

P0.29/TCK/CAP2.2

XTAL1
XTAL2

P0.18/CAP1.3/SDA1

P0.17/CAP1.2/SCL1

P0.16/EINT0/MAT0.2

4847464544434241403938
1 36
2 35
3 34
4 33
5 32
6 31
7 30
8 29
9 28

10 27
11 26
12 25

1314151617181920212223

P0.0/TXD0/MAT3.1

LPC2103FHN48H

P0.30/TDI/MAT3.3

P0.1/RXD0/MAT3.2

Transparent top view

Fig 3. Pin configuration (HVQFN48)

P0.15/RI1/EINT2

DDA

P0.14/DCD1/SCK1/EINT1

VSSV

P0.13/DTR1/MAT1.1

LPC2102FHN48
LPC2103FHN48

SS

V

DD(3V3)

V

P0.31/TDO

RTCX1

P0.2/SCL0/CAP0.0

DD(3V3)

V

P0.26/AD0.7

P0.25/AD0.6

P0.12/DSR1/MAT1.0/AD0.5
37

24

P0.4/SCK0/CAP0.1

P0.3/SDA0/MAT0.0

P0.6/MOSI0/CAP0.2

P0.5/MISO0/MAT0.1

P0.11/CTS1/CAP1.1/AD0.4
P0.10/RTS1/CAP1.0/AD0.3
P0.24/AD0.2
P0.23/AD0.1
P0.22/AD0.0
V

SSA

P0.9/RXD1/MAT2.2
P0.8/TXD1/MAT2.1
P0.7/SSEL0/MAT2.0
DBGSEL
RTCK
RTCX2

002aad918

LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 04 — 2 June 2009 5 of 37

NXP Semiconductors

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

5.2 Pin description

Table 3. Pin description

Symbol Pin Type Description

P0.0 to P0.31 I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit.

A total of 31 pins of the Port 0 can be used as general purpose bidirectional
digital I/Os while P0.31 is an output only pin. The operation of port 0 pins
depends upon the pin function selected via the pin connect block.

P0.0/TXD0/
MAT3.1

P0.1/RXD0/
MAT3.2

P0.2/SCL0/
CAP0.0

P0.3/SDA0/
MAT0.0

P0.4/SCK0/
CAP0.1

P0.5/MISO0/
MAT0.1

P0.6/MOSI0/
CAP0.2

P0.7/SSEL0/
MAT2.0

P0.8/TXD1/
MAT2.1

P0.9/RXD1/
MAT2.2

P0.10/RTS1/
CAP1.0/AD0.3

13

14

18

21

22

23

24

28

29

30

35

[1]

I/O P0.0 — General purpose input/output digital pin.
O TXD0 — Transmitter output for UART0.
O MAT3.1 — PWM output 1 for Timer 3.

[1]

I/O P0.1 — General purpose input/output digital pin.
I RXD0 — Receiver input for UART0.
O MAT3.2 — PWM output 2 for Timer 3.

[2]

I/O P0.2 — General purpose input/output digital pin. Output is open-drain.

2

I/O SCL0 — I

C0 clock Input/output. Open-drain output (for I2C-bus compliance).

I CAP0.0 — Capture input for Timer 0, channel 0.

[2]

I/O P0.3 — General purpose input/output digital pin. Output is open-drain.

2

I/O SDA0 — I

C0 data input/output. Open-drain output (for I2C-bus compliance).

O MAT0.0 — PWM output for Timer 0, channel 0. Output is open-drain.

[1]

I/O P0.4 — General purpose input/output digital pin.
I/O SCK0 — Serial clock for SPI0. SPI clock output from master or input to slave.
I CAP0.1 — Capture input for Timer 0, channel 1.

[1]

I/O P0.5 — General purpose input/output digital pin.
I/O MISO0 — Master In Slave Out for SPI0. Data input to SPI master or data

output from SPI slave.

O MAT0.1 — PWM output for Timer 0, channel 1.

[1]

I/O P0.6 — General purpose input/output digital pin.
I/O MOSI0 — Master Out Slave In for SPI0. Data output from SPI master or data

input to SPI slave.

I CAP0.2 — Capture input for Timer 0, channel 2.

[1]

I/O P0.7 — General purpose input/output digital pin.
I SSEL0 — Slave Select for SPI0. Selects the SPI interface as a slave.
O MAT2.0 — PWM output for Timer 2, channel 0.

[1]

I/O P0.8 — General purpose input/output digital pin.
O TXD1 — Transmitter output for UART1.
O MAT2.1 — PWM output for Timer 2, channel 1.

[1]

I/O P0.9 — General purpose input/output digital pin.
I RXD1 — Receiver input for UART1.
O MAT2.2 — PWM output for Timer 2, channel 2.

[3]

I/O P0.10 — General purpose input/output digital pin.
O RTS1 — Request to Send output for UART1.
I CAP1.0 — Capture input for Timer 1, channel 0.
I AD0.3 — ADC 0, input 3.

LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 04 — 2 June 2009 6 of 37

NXP Semiconductors

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

Table 3. Pin description

…continued

Symbol Pin Type Description

P0.11/CTS1/
CAP1.1/AD0.4

36

[3]

I/O P0.11 — General purpose input/output digital pin.
I CTS1 — Clear to Send input for UART1.
I CAP1.1 — Capture input for Timer 1, channel 1.
I AD0.4 — ADC 0, input 4.

P0.12/DSR1/
MAT1.0/AD0.5

37

[3]

I/O P0.12 — General purpose input/output digital pin.
I DSR1 — Data Set Ready input for UART1.
O MAT1.0 — PWM output for Timer 1, channel 0.
I AD0.5 — ADC 0, input 5.

P0.13/DTR1/
MAT1.1

41

[1]

I/O P0.13 — General purpose input/output digital pin.
O DTR1 — Data Terminal Ready output for UART1.
O MAT1.1 — PWM output for Timer 1, channel 1.

P0.14/DCD1/
SCK1/EINT1

44

[4][5]

I/O P0.14 — General purpose input/output digital pin.
I DCD1 — Data Carrier Detect input for UART1.
I/O SCK1 — Serial Clock for SPI1. SPI clock output from master or input to slave.
I EINT1 — External interrupt 1 input.

P0.15/RI1/
EINT2

45

[4]

I/O P0.15 — General purpose input/output digital pin.
I RI1 — Ring Indicator input for UART1.
I EINT2 — External interrupt 2 input.

P0.16/EINT0/
MAT0.2

46

[4]

I/O P0.16 — General purpose input/output digital pin.
I EINT0 — External interrupt 0 input.
O MAT0.2 — PWM output for Timer 0, channel 2.

P0.17/CAP1.2/
SCL1

47

[6]

I/O P0.17 — General purpose input/output digital pin. The output is not

open-drain.
I CAP1.2 — Capture input for Timer 1, channel 2.
I/O SCL1 — I

function is selected in the pin connect block.

P0.18/CAP1.3/
SDA1

48

[6]

I/O P0.18 — General purpose input/output digital pin. The output is not

open-drain.
I CAP1.3 — Capture input for Timer 1, channel 3.
I/O SDA1 — I

function is selected in the pin connect block.

P0.19/MAT1.2/
MISO1

[1]

1

I/O P0.19 — General purpose input/output digital pin.
O MAT1.2 — PWM output for Timer 1, channel 2.
I/O MISO1 — Master In Slave Out for SSP. Data input to SSP master or data

output from SSP slave.

P0.20/MAT1.3/
MOSI1

[1]

2

I/O P0.20 — General purpose input/output digital pin.
O MAT1.3 — PWM output for Timer 1, channel 3.
I/O MOSI1 — Master Out Slave for SSP. Data output from SSP master or data

input to SSP slave.

P0.21/SSEL1/
MAT3.0

[1]

3

I/O P0.21 — General purpose input/output digital pin.
I SSEL1 — Slave Select for SPI1. Selects the SPI interface as a slave.
O MAT3.0 — PWM output for Timer 3, channel 0.

2

C1 clock Input/output. This pin is an open-drain output if I2C1

2

C1 data Input/output. This pin is an open-drain output if I2C1

LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 04 — 2 June 2009 7 of 37

NXP Semiconductors

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

Table 3. Pin description

…continued

Symbol Pin Type Description

P0.22/AD0.0 32

[3]

I/O P0.22 — General purpose input/output digital pin.
I AD0.0 — ADC 0, input 0.

P0.23/AD0.1 33

[3]

I/O P0.23 — General purpose input/output digital pin.
I AD0.1 — ADC 0, input 1.

P0.24/AD0.2 34

[3]

I/O P0.24 — General purpose input/output digital pin.
I AD0.2 — ADC 0, input 2.

P0.25/AD0.6 38

[3]

I/O P0.25 — General purpose input/output digital pin.
I AD0.6 — ADC 0, input 6.

P0.26/AD0.7 39

[3]

I/O P0.26 — General purpose input/output digital pin.
I AD0.7 — ADC 0, input 7.

P0.27/
CAP2.0

TRST/

[1]

8

I/O P0.27 — General purpose input/output digital pin.
I

TRST — Test Reset for JTAG interface. If DBGSEL is HIGH, this pin is

automatically configured for use with EmbeddedICE (Debug mode).
I CAP2.0 — Capture input for Timer 2, channel 0.

P0.28/TMS/
CAP2.1

[1]

9

I/O P0.28 — General purpose input/output digital pin.
I TMS — Test Mode Select for JTAG interface. If DBGSEL is HIGH, this pin is

automatically configured for use with EmbeddedICE (Debug mode).
I CAP2.1 — Capture input for Timer 2, channel 1.

P0.29/TCK/
CAP2.2

10

[1]

I/O P0.29 — General purpose input/output digital pin.
I TCK — Test ClockforJTAGinterface.This clock must be slower than

1

⁄6of the

CPU clock (CCLK) for the JTAG interface to operate. If DBGSEL is HIGH, this

pin is automatically configured for use with EmbeddedICE (Debug mode).
I CAP2.2 — Capture input for Timer 2, channel 2.

P0.30/TDI/
MAT3.3

15

[1]

I/O P0.30 — General purpose input/output digital pin.
I TDI — Test Data In for JTAG interface. If DBGSEL is HIGH, this pin is

automatically configured for use with EmbeddedICE (Debug mode).
O MAT3.3 — PWM output 3 for Timer 3.

P0.31/TDO 16

[1]

O P0.31 — General purpose output only digital pin.
O TDO — Test Data Out for JTAG interface. If DBGSEL is HIGH, this pin is

automatically configured for use with EmbeddedICE (Debug mode).

RTCX1 20
RTCX2 25
RTCK 26

[7][8]
[7][8]
[7]

I Input to the RTC oscillator circuit. Input voltage must not exceed 1.8 V.
O Output from the RTC oscillator circuit.
I/O Returned test clock output: Extra signal added to the JTAG port. Assists

debugger synchronization when processor frequency varies. Bidirectional pin

with internal pull-up.

XTAL1 11 I Input to the oscillator circuit and internal clock generator circuits. Input voltage

must not exceed 1.8 V.

XTAL2 12 O Output from the oscillator amplifier.
DBGSEL 27 I Debug select: When LOW, the part operates normally. When externally

pulled HIGH at reset, P0.27 to P0.31 are configured as JTAG port, and the

part is in Debug mode

[9]

. Input with internal pull-down.

RST 6 I External reset input: A LOW on this pin resets the device, causing I/O ports

and peripherals to take on their default states and processor execution to

begin at address 0. TTL with hysteresis, 5 V tolerant.

LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 04 — 2 June 2009 8 of 37

NXP Semiconductors

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

Table 3. Pin description

…continued

Symbol Pin Type Description

V

SS

V

SSA

V

DDA

7, 19, 43 I Ground: 0 V reference.
31 I Analog ground: 0 V reference. This should be nominally the same voltage as

V

but should be isolated to minimize noise and error.

SS

42 I Analog 3.3 V power supply: This should be nominally the same voltage as

V

but should be isolated to minimize noise and error. The level on this

DD(3V3)

pin also provides a voltage reference level for the ADC.

V

DD(1V8)

5I1.8 V core power supply: This is the power supply voltage for internal

circuitry and the on-chip PLL.

V

DD(3V3)

17, 40 I 3.3 V pad power supply: This is the power supply voltage for the I/O ports.

VBAT 4 I RTC power supply: 3.3 V on this pin supplies the power to the RTC.

[1] 5 V tolerant (if V
[2] Open-drain 5 V tolerant (if V

pull-up to provide an output functionality. Open-drain configuration applies to ALL functions on that pin.

[3] 5 V tolerant (if V

analog input function. If configured for an input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns. When
configured as an ADC input, digital section of the pad is disabled.

[4] 5 V tolerant (if V

If configured for an input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns.
[5] A LOW level during reset on pin P0.14 is considered as an external hardware request to start the ISP command handler.
[6] Open-drain 5 V tolerant (if V

pull-up to provide an output functionality. Open-drain configuration applies only to I2C function on that pin.
[7] Pad provides special analog functionality.
[8] For lowest power consumption, pin should be left floating when the RTC is not used.
[9] See

LPC2101/02/03 User manual UM10161

DD(3V3)

DD(3V3)

DD(3V3)

and V

and V

and V

≥ 3.0 V) pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.

DDA

and V

DD(3V3)

≥ 3.0 V) pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and

DDA

≥ 3.0 V) pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.

DDA

and V

DD(3V3)

≥ 3.0 V) digital I/O I2C-bus 400 kHz specification compatible pad. It requires external

DDA

≥ 3.0 V) digital I/O I2C-bus 400 kHz specification compatible pad. It requires external

DDA

for details.

LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 04 — 2 June 2009 9 of 37

NXP Semiconductors

6. Functional description

6.1 Architectural overview

The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed Complex
Instruction Set Computers (CISC). This simplicity results in a high instruction throughput
and impressive real-time interrupt response from a small and cost-effective processor
core.

Pipeline techniques are employed so that allparts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as
Thumb, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:

• The standard 32-bit ARM set.

• A 16-bit Thumb set.

The Thumb set’s 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16-bit processor using 16-bit registers. This is possible because Thumb code
operates on the same 32-bit register set as ARM code.

Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the
performance of an equivalent ARM processor connected to a 16-bit memory system.

The particular flash implementation in the LPC2101/02/03 allows for full speed execution
also in ARM mode. It is recommended to program performance critical and short code
sections in ARM mode. The impact on the overallcode size will be minimal but the speed
can be increased by 30 % over Thumb mode.

6.2 On-chip flash program memory

The LPC2101/02/03 incorporate a 8 kB, 16 kB or 32 kB flash memory system
respectively. This memory may be used for both code and data storage. Programming of
the flash memory maybe accomplished in several ways. It may be programmed in system
via the serial port. The application programmay also erase and/or program the flash while
the application is running, allowing a great degree of flexibility for data storage field
firmware upgrades, etc. The entire flash memory is available for user code as the
bootloader resides in a separate memory.

The LPC2101/02/03 flash memory provides a minimum of 100,000 erase/write cycles and
20 years of data-retention memory.

LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.

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6.3 On-chip static RAM

On-chip static RAM may be used for code and/or data storage. The SRAM may be
accessed as 8-bits, 16-bits, and 32-bits. The LPC2101/02/03 provide 2 kB,4 kB or 8 kB of
static RAM.

6.4 Memory map

The LPC2101/02/03 memory map incorporates several distinct regions, as shown in

Figure 4.

In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either
flash memory (the default) or on-chip static RAM. This is described in Section 6.17

“System control”.

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

4.0 GB

3.75 GB

3.5 GB

3.0 GB

2.0 GB

1.0 GB

0.0 GB

AHB PERIPHERALS

APB PERIPHERALS

RESERVED ADDRESS SPACE

BOOT BLOCK

RESERVED ADDRESS SPACE

8 kB ON-CHIP STATIC RAM (LPC2103)

4 kB ON-CHIP STATIC RAM (LPC2102)
2 kB ON-CHIP STATIC RAM (LPC2101)

RESERVED ADDRESS SPACE

32 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2103)

16 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2102)

8 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2101)

0xFFFF FFFF
0xF000 0000

0xE000 0000

0xC000 0000

0x8000 0000
0x7FFF FFFF

0x7FFF E000
0x7FFF DFFF

0x4000 2000
0x4000 1FFF

0x4000 1000
0x4000 0FFF

0x4000 0800
0x4000 07FF

0x4000 0000
0x0000 8000

0x0000 7FFF
0x0000 4000

0x0000 3FFF
0x0000 2000

0x0000 1FFF
0x0000 0000

002aab822

Fig 4. LPC2101/02/03 memory map

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NXP Semiconductors

6.5 Interrupt controller

The VIC accepts all of the interrupt request inputs and categorizes them as FIQ, vectored
IRQ, and non-vectored IRQ as defined by programmable settings. The programmable
assignment scheme means that priorities ofinterrupts from thevarious peripherals can be
dynamically assigned and adjusted.

FIQ has the highest priority. If more than one request is assigned to FIQ, the VIC
combines the requests to produce the FIQ signal to the ARM processor. The fastest
possible FIQ latency is achieved when only one requestis classified as FIQ, because then
the FIQ service routine does not need to branch into the interrupt service routine but can
run from the interrupt vector location. If more than one request is assigned to the FIQ
class, the FIQ service routine will read a word from the VIC that identifies which FIQ
source(s) is (are) requesting an interrupt.

Vectored IRQs have the middle priority.Sixteen of the interrupt requests can be assigned
to this category. Any of the interrupt requests can be assigned to any of the 16 vectored
IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.

Non-vectored IRQs have the lowest priority.

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

The VIC combines the requests from all the vectored and non-vectored IRQs to produce
the IRQ signal to the ARM processor. The IRQ service routine can start by reading a
register from the VIC and jumping there. If any of the vectored IRQs are pending, the VIC
provides the address of the highest-priority requesting IRQs service routine, otherwise it
provides the address of a default routine that is shared by all the non-vectored IRQs. The
default routine can read another VIC register to see what IRQs are active.

6.5.1 Interrupt sources

Each peripheral device has one interrupt line connected to the Vectored Interrupt
Controller,but may have several internal interrupt flags. Individual interrupt flags may also
represent more than one interrupt source.

6.6 Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on chip peripherals. Peripherals should be connected to the appropriate pins
prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any
enabled peripheral function that is not mapped to a related pin should be considered
undefined.

The pin control module with its pin select registers defines the functionality of the
microcontroller in a given hardware environment.

After reset all pins of Port 0 are configured as input with the following exceptions: If the
DBGSEL pin is HIGH (Debug mode enabled), the JTAG pins will assume their JTAG
functionality for use with EmbeddedICE and cannot be configured via the pin connect
block.

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6.7 Fast general purpose parallel I/O

Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of the
output register may be read back, as well as the current state of the port pins.

LPC2101/02/03 introduce accelerated GPIO functions over prior LPC2000 devices:

• GPIO registers are relocated to the ARM local bus for the fastest possible I/O timing.

• Mask registers allow treating sets of port bits as a group, leaving other bits

• All GPIO registers are byte addressable.

• Entire port value can be written in one instruction.

6.7.1 Features

• Bit-level set and clear registers allow a single instruction set or clear of any number of

• Direction control of individual bits.

• Separate control of output set and clear.

• All I/O default to inputs after reset.

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

unchanged.

bits in one port.

6.8 10-bit ADC

The LPC2101/02/03 contain one ADC. It is a single 10-bit successive approximation ADC
with eight channels.

6.8.1 Features

• Measurement range of 0 V to 3.3 V.

• Each converter capable of performing more than 400,000 10-bit samples per second.

• Burst conversion mode for single or multiple inputs.

• Optional conversion on transition on input pin or Timer Match signal.

• Every analog input has a dedicated result register to reduce interrupt overhead.

6.9 UARTs

The LPC2101/02/03 each contain two UARTs. In addition to standard transmit and
receive data lines, UART1 also provides a full modem control handshake interface.

Compared to previous LPC2000 microcontrollers, UARTs in LPC2101/02/03 include a
fractional baud rate generator for both UARTs. Standard baud rates such as 115200 can
be achieved with any crystal frequency above 2 MHz.

6.9.1 Features

• 16 byte Receive and Transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1, 4, 8, and 14 bytes

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NXP Semiconductors

• Built-in fractional baud rate generator covering wide range of baud rates without a

• Transmission FIFO control enables implementation of software (XON/XOFF) flow

• UART1 is equipped with standard modem interface signals. This module also

6.10 I2C-bus serial I/O controllers

The LPC2101/02/03 each contain two I2C-bus controllers.
The I2C-bus is bidirectional, for inter-IC control using only two wires: a Serial Clock Line

(SCL), and a Serial Data Line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., LCD driver) or a transmitter with the
capability to both receive and send information such as serial memory. Transmitters
and/or receivers can operate in either master or slave mode, depending on whether the
chip has to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus,
it can be controlled by more than one bus master connected to it.

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

need for external crystals of particular values.

control on both UARTs.

provides full support for hardware flow control (auto-CTS/RTS).

The I2C-bus implemented in LPC2101/02/03 supports bit rates up to 400 kbit/s (Fast
I2C-bus).

6.10.1 Features

• Compliant with standard I

• Easy to configure as Master, Slave, or Master/Slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Serialclock synchronization can be usedas a handshake mechanism to suspendand

resume serial transfer.

• The I

2

C-bus can also be used for test and diagnostic purposes.

6.11 SPI serial I/O controller

The LPC2101/02/03 each contain one SPI controller. The SPI is a full duplex serial
interface, designed to handle multiple masters and slaves connected to a given bus. Only
a single master and a single slave can communicate on the interface during a given data
transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the
slave, and the slave always sends 8 bits to 16 bits of data to the master.

2

C-bus interface.

6.11.1 Features

• Compliant with SPI specification.

• Synchronous, Serial, Full Duplex, Communication.

LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.

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NXP Semiconductors

• Combined SPI master and slave.

• Maximum data bit rate of one eighth of the input clock rate.

6.12 SSP serial I/O controller

The LPC2101/02/03 each contain one SSP. The SSP controller is capable of operationon
a SPI, 4-wire SSI, or Microwire bus. It caninteract with multiplemasters and slaves on the
bus.However, only a single master and asingle slave can communicate on the busduring
a given data transfer. The SSP supports full duplex transfers, with data frames of 4 bits to
16 bits flowing from the master to the slave and from the slave to the master. Often only
one of these data streams carries meaningful data.

6.12.1 Features

• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

• Synchronous serial communication

• Master or slave operation

• 8-frame FIFOs for both transmit and receive

• Four bits to 16 bits per frame

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

Semiconductor’s Microwire buses

6.13 General purpose 32-bit timers/external event counters

The Timer/Counter is designed to count cycles of the Peripheral Clock (PCLK) or an
externally supplied clock and optionally generate interrupts or perform other actions at
specified timer values, based on four match registers. It also includes four capture inputs
to trap the timer value when an input signal transitions, optionally generating an interrupt.
Multiple pins can be selected to perform a single capture or match function, providing an
application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.

The LPC2101/02/03 can count external events on one of the capture inputs if the
minimum external pulse is equal or longer thana period ofthe PCLK. In thisconfiguration,
unused capture lines can be selected as regular timer capture inputs or used as external
interrupts.

6.13.1 Features

• A 32-bit timer/counter with a programmable 32-bit prescaler.

• External event counter or timer operation.

• Four 32-bit capture channels per timer/counter that can take a snapshot of the timer

value when an input signal transitions. A capture event may also optionally generate
an interrupt.

• Four 32-bit match registers that allow:

– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.

• Four external outputs per timer/counter corresponding to match registers, with the

following capabilities:
– Set LOW on match.

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6.14 General purpose 16-bit timers/external event counters

The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an
externally supplied clock and optionally generate interrupts or perform other actions at
specified timer values, based on four match registers.It also includesthree captureinputs
to trap the timer value when an input signal transitions, optionally generating an interrupt.
Multiple pins can be selected to perform a single capture or match function, providing an
application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.

The LPC2101/02/03 can count external events on one of the capture inputs if the
minimum external pulse is equal or longer thana period ofthe PCLK. In thisconfiguration,
unused capture lines can be selected as regular timer capture inputs or used as external
interrupts.

6.14.1 Features

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

– Set HIGH on match.
– Toggle on match.
– Do nothing on match.

• Two 16-bit timer/counters with a programmable 16-bit prescaler.

• External event counter or timer operation.

• Three 16-bit capture channels that can take a snapshot of the timer value when an

input signal transitions. A capture event may also optionally generate an interrupt.

• Four 16-bit match registers that allow:

– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.

• Four external outputs per timer/counter corresponding to match registers, with the

following capabilities:

– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.

6.15 Watchdog timer

The purpose of the watchdog is toreset the microcontrollerwithin a reasonableamount of
time if it enters an erroneous state. When enabled, the watchdog will generate a system
reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined
amount of time.

6.15.1 Features

• Internally resets chip if not periodically reloaded.

• Debug mode.

• Enabled by software but requires a hardware reset or a watchdogreset/interrupt tobe

disabled.

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NXP Semiconductors

• Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.

• Flag to indicate watchdog reset.

• Programmable 32-bit timer with internal pre-scaler.

• Selectable time period from (T

6.16 Real-time clock

The Real-Time Clock (RTC) is designed to provide a set of counters to measure time
when normal or idle operating mode is selected. The RTC has been designed to use little
power, making it suitable for battery powered systems where the CPU is not running
continuously (Idle mode).

6.16.1 Features

• Measures the passage of time to maintain a calendar and clock.

• Ultra-low power design to support battery powered systems.

T

PCLK

× 4.

× 256 × 4) to (T

PCLK

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

× 232× 4) in multiples of

PCLK

• ProvidesSeconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day

of Year.

• Can use either the RTC dedicated 32 kHz oscillator input or clock derived from the

external crystal/oscillator input at XTAL1. The programmable reference clock divider
allows fine adjustment of the RTC.

• Dedicated power supply pin can be connected to a battery or the main 3.3 V.

6.17 System control

6.17.1 Crystal oscillator

The on-chip integrated oscillator operates with external crystal in range of 1 MHz to
25 MHz. The oscillator output frequency is called f
frequency is referred to as CCLK for purposes of rate equations, etc. f
the same value unless the PLL is running and connected. Refer to Section 6.17.2 “PLL”
and Section 10.1 “XTAL1 input” for additional information.

6.17.2 PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up into the range of 10 MHz to 70 MHz with a Current Controlled
Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the
multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper
frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so
there is an additional divider in the loop to keep the CCO within its frequency range while
the PLL is providing the desired output frequency. The output divider may be set to divide
by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2,
it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and
bypassed following a chip reset and may be enabled by software. The program must
configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a
clock source. The PLL settling time is 100 µs.

and the ARM processor clock

osc

and CCLK are

osc

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NXP Semiconductors

6.17.3 Reset and wake-up timer

Reset has two sources on the LPC2101/02/03: the RSTpin and watchdog reset. The RST
pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip reset by
any source starts the wake-up timer (see wake-up timer description below), causing the
internal chip reset to remain asserted until the external reset is de-asserted, the oscillator
is running, a fixed number of clocks have passed, and the on-chip flash controller has
completed its initialization.

When the internal reset is removed, the processor begins executing at address 0, which is
the reset vector. At that point, all of the processor and peripheral registers have been
initialized to predetermined reset values.

The wake-up timer ensures that the oscillator and other analog functions required for chip
operation are fully functional before the processor is allowed to execute instructions. This
is important at power on, all types of reset, and whenever any of the aforementioned
functions are turned off forany reason. Since the oscillator and other functions are turned
off during Power-down and Deep power-down mode, any wake-up of the processor from
the Power-down modes makes use of the wake-up timer.

The wake-up timer monitors the crystal oscillator as the means of checking whether it is
safe to begin code execution. When power is applied to the chip, or some event caused
the chip to exit Power-down mode, some time is required for the oscillator to produce a
signal of sufficient amplitude to drive the clock logic. The amount of time depends on
many factors, including the rate of VDD ramp (in the case of power on), the type of crystal
and its electrical characteristics (if a quartz crystal is used), as well as any other external
circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing
ambient conditions.

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

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NXP Semiconductors

6.17.4 Code security (Code Read Protection - CRP)

This feature of the LPC2101/02/03 allows user to enable different levels of security in the
system so that accessto theon-chip flashand useof theJTAG and ISP can be restricted.
When needed, CRP is invoked by programming a specific pattern into a dedicated flash
location. IAP commands are not affected by the CRP.

Implemented in bootloader code version 2.21 are three levels of the Code Read
Protection:

1. CRP1 disables access to chip via the JTAG and allows partial flash update (excluding

2. CRP2 disables access to chip via the JTAG and only allows full flash erase and

3. Running an application with level CRP3 selected fully disables any access to chip via

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

flash sector 0) using a limited set of the ISP commands. This mode is useful when
CRP is required and flash field updates are needed but all sectors cannot be erased.

update using a reduced set of the ISP commands.

the JTAG pins and the ISP. This mode effectively disables ISP override using P0.14
pin, too. It is up to the user’s application to provide (if needed) flash update
mechanism using IAP calls or call reinvoke ISP command to enable flash update via
UART0.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.

Remark: Parts LPC2101/02/03 Revision ‘-’ have CRP2 enabled only (bootloader code
version 2.2).

6.17.5 External interrupt inputs

The LPC2101/02/03 include up to three edgeor level sensitive external interrupt inputs as
selectable pin functions. When the pins are combined, external events can be processed
as three independent interrupt signals. The external interrupt inputs can optionally be
used to wake-up the processor from Power-down mode and Deep power-down mode.

Additionally all 10 capture input pins can also be used as external interrupts without the
option to wake the device up from Power-down mode.

6.17.6 Memory mapping control

The memory mapping control alters the mapping of the interrupt vectors that appear
beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip
flash memory, or to the on-chip static RAM. This allows code running in different memory
spaces to have control of the interrupts.

6.17.7 Power control

The LPC2101/02/03 supports three reduced power modes: Idle mode, Power-down
mode, and Deep power-down mode.

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NXP Semiconductors

In Idle mode, executionof instructions is suspended until either a resetor interrupt occurs.
Peripheral functions continue operation during Idle mode and may generate interrupts to
cause the processor to resume execution. Idle mode eliminates power used by the
processor itself, memory systems and related controllers, and internal buses.

In Power-down mode, the oscillator is shut down and the chip receives no internal clocks.
The processor state and registers, peripheral registers, and internal SRAM values are
preserved throughout Power-down mode and the logic levels of chip output pins remain
static. The Power-down mode can be terminated and normal operation resumed by either
a reset or certain specific interrupts that are able to function without clocks. Since all
dynamic operation of the chip is suspended, Power-down mode reduces chip power
consumption to nearly zero.

Selecting an external 32 kHz clock instead of the PCLK as a clock-source for the on-chip
RTC will enable the microcontroller to have the RTC active during Power-down mode.
Power-down current is increased with RTCactive. However, it is significantly lower than in
Idle mode.

In Deep-power down mode all poweris removed from the internal chip logic except for the
RTC module, the I/O ports, the SRAM, and the 32 kHz external oscillator. For additional
power savings, SRAM and the 32 kHz oscillator can be powered down individually. The
Deep power-down mode produces the lowest possible power consumption without
actually removing power from the entire chip. In Deep power-down mode, the contents of
registers and memory are not preserved except for SRAM, if selected, and three general
purpose registers. Therefore, to resume operations, a full chip reset process is required.

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

A power selector moduleswitches the RTC power supply from VBAT toV
the core voltage is present on pin V

A power control for peripherals feature allows individual peripherals to be turned off if they
are not needed in the application, resulting in additional power savings during Active and
Idle mode.

6.17.8 APB

The APB divider determines therelationship between the processor clock(CCLK) and the
clock used by peripheral devices (PCLK). The APB divider serves two purposes. The first
is to provide peripherals with the desired PCLK via APB so that they can operate at the
speed chosen for the ARM processor. In order to achieve this, the APB may be slowed
down to1⁄2 to1⁄4 of the processor clock rate. Because the APB must work properly at
power-up (and itstiming cannot bealtered if itdoes not worksince the APBdivider control
registers reside on the APB), the default condition at reset is for the APB to run at1⁄4of the
processor clock rate. The second purpose of the APB divider is to allow power savings
when an application does not require any peripherals to run at the full processor rate.
Because the APB divider is connected to the PLL output, the PLL remains active (if it was
running) during Idle mode.

6.18 Emulation and debugging

The LPC2101/02/03 support emulation and debugging via a JTAG serial port.

to conserve battery power.

DD(1V8)

DD(1V8)

whenever

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NXP Semiconductors

6.18.1 EmbeddedICE

Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of
the target system requires a host computer running the debugger software and an
EmbeddedICE protocol converter. The EmbeddedICE protocol converter converts the
remote debug protocol commands to the JTAG data needed to access the ARM core.

The ARM core has a debug communication channel function built-in. The debug
communication channel allows a program running on the target to communicate with the
host debugger or another separate host without stopping the program flow or even
entering the debug state. The debug communication channel is accessed as a
coprocessor 14 by the program running on the ARM7TDMI-S core. The debug
communication channel allows the JTAG port to be used for sending and receiving data
without affecting the normal program flow. The debug communication channel data and
control registers are mapped in to addresses in the EmbeddedICE logic. The JTAG clock
(TCK) must be slower than1⁄6 of the CPU clock (CCLK) for the JTAG interface to operate.

6.18.2 RealMonitor

RealMonitor is a configurable software module, developed by ARM Inc., which enables
real time debug. It is a lightweight debug monitor that runs in the background while users
debug their foreground application. It communicates with the host usingthe DCC, which is
present in the EmbeddedICE logic. The LPC2101/02/03 contain a specific configuration of
RealMonitor software programmed into the on-chip boot ROM memory.

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

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NXP Semiconductors

7. Limiting values

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

[1]

Symbol Parameter Conditions Min Max Unit

V

DD(1V8)

V

DD(3V3)

V

DDA

V

i(VBAT)

V

IA

V

I

supply voltage (1.8 V)
supply voltage (3.3 V)
analog 3.3 V pad supply voltage −0.5 +4.6 V
input voltage on pin VBAT for the RTC −0.5 +4.6 V
analog input voltage
input voltage 5 V tolerant I/O

[2]

−0.5 +2.5 V

[3]

−0.5 +4.6 V

[4]

−0.5 +5.1 V

[5][6]

−0.5 +6.0 V

pins

I

DD

I

SS

T

stg

P

tot(pack)

other I/O pins
supply current
ground current
storage temperature
total power dissipation (per package) based on package

[5]

−0.5 VDD + 0.5

[8]

- 100

[10]

- 100

[11]

−65 +150 °C

- 1.5 W

[7]

V

[9]
[9]

mA
mA

heat transfer, not

device power

consumption

V

ESD

electrostatic discharge voltage Human Body

−4000 +4000 V

Model (HBM)

Machine Model

−200 +200 V

(MM)

Charged Device

−800 +800 V

Model (CDM)

[12]

[13]

[14]

[1] The following applies to the limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless

otherwise noted.
[2] Core and internal rail.
[3] External rail.
[4] On ADC related pins.
[5] Including voltage on outputs in 3-state mode.
[6] Only valid when the V
[7] Not to exceed 4.6 V.
[8] Per supply pin.
[9] The peak current is limited to 25 times the corresponding maximum current.
[10] Per ground pin.
[11] Dependent on package type.
[12] Performed per AEC-Q100-002.
[13] Performed per AEC-Q100-003.
[14] Performed per AEC-Q100-011.

LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 04 — 2 June 2009 22 of 37

supply voltage is present.

DD(3V3)

NXP Semiconductors

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

8. Static characteristics

Table 5. Static characteristics

T

=−40°C to +85°C for commercial applications, unless otherwise specified.

amb

Symbol Parameter Conditions Min Typ

V

DD(1V8)

supply voltage
(1.8 V)

V

DD(3V3)

supply voltage
(3.3 V)

V

DDA

analog 3.3 V pad
supply voltage

V

i(VBAT)

input voltage on pin
VBAT

Standard port pins,

I

IL

LOW-level input
current

I

IH

HIGH-level input
current

I

OZ

OFF-state output
current

I

latch

V

V
V

I

O
IH

I/O latch-up current −(0.5V

input voltage pin configured to provide a digital

output voltage output active 0 - V
HIGH-level input

voltage

V

IL

LOW-level input
voltage

V

hys

V

OH

hysteresis voltage 0.4 - - V
HIGH-level output

voltage

V

OL

LOW-level output
voltage

I

OH

HIGH-level output
current

I

OL

LOW-level output
current

I

OHS

HIGH-level
short-circuit output
current

I

OLS

LOW-level
short-circuit output
current

I

pd

pull-down current VI=5V

RST, RTCK

VI= 0 V; no pull-up - - 3 µA

VI=V

VO=0V, VO=V

; no pull-down - - 3 µA

DD(3V3)

; no

DD(3V3)

pull-up/down

) < VI < (1.5V

DD(3V3)

< 125 °C

T

j

function; V

DD(3V3)

and V

DDA

DD(3V3)

≥ 3.0 V

pin configured to provide a digital
function; V

DD(3V3)

and V

DDA

< 3.0 V

IOH= −4mA

IOL= −4mA

VOH=V

DD(3V3)

− 0.4 V

VOL= 0.4 V

VOH=0V

VOL=V

DDA

[12]

[2]

1.65 1.8 1.95 V

[3]

[4]

2.6

2.6

2.0

[5]

[6]

3.3 3.6 V

3.3 3.6 V

3.3 3.6 V

--3µA

);

- - 100 mA

[7][8]

0 - 5.5 V

[9]

[7][8]

0V

[9]

2.0 - - V

- - 0.8 V

[10]

V

[10]

- - 0.4 V

[10]

−4--mA

[10]

4--mA

[11]

--−45 mA

[11]

- - 50 mA

− 0.4 - - V

DD(3V3)

10 50 150 µA

[1]

Max Unit

DD(3V3)

DD(3V3)

V

V

LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 04 — 2 June 2009 23 of 37

NXP Semiconductors

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

Table 5. Static characteristics

T

=−40°C to +85°C for commercial applications, unless otherwise specified.

amb

…continued

Symbol Parameter Conditions Min Typ

I

pu

I

DD(CORE)

pull-up current VI=0V

V

DD(3V3)<VI

core supply current Active mode;

<5V

[12]

[13]

−15 −50 −85 µA
000µA

code

while(1){}

executed from flash; all peripherals
enabled via PCONP register but not
configured to run; CCLK = 70 MHz

I

BAT

battery supply
current

2

C-bus pins

I

V

IH

HIGH-level input
voltage

V

IL

LOW-level input
voltage

V

hys

V

OL

hysteresis voltage - 0.5V
LOW-level output

voltage

I

LI

input leakage
current

Oscillator pins

V

i(XTAL1)

input voltage on pin
XTAL1

V

Power-down mode;

V
V

Deep power-down mode;
RTC off; SRAM off; T

V

Active mode; CCLK = 70 MHz;
PCLK = 17.5 MHz;
PCLK enabled to RTCK;
RTC clock = 32 kHz (from RTCX
pins); T

V

Power-down mode;
RTC clock = 32 kHz
(from RTCX pins); T

V
V

Deep power-down mode;
RTC off; SRAM off; T

V

I

OLS

VI=V

=5V

V

I

DD(1V8)

DD(1V8)
DD(1V8)

i(VBAT)

amb

DD(1V8)

DD(1V8)
DD(1V8)

DD(1V8)

=3mA

DD(3V3)

= 1.8 V; T

= 1.8 V; T
= 1.8 V; T

= 3.3 V; V

=25°C

= 1.8 V; V

= 1.8 V; V
= 1.8 V; V

= 1.8 V; V

=25°C - 41 70 mA

amb

=25°C - 2.5 25 µA

amb

=85°C - 35 105 µA

amb

=25°C

amb

= 1.8 V - 0.7 - µA

DD(1V8)

[14]

= 3.0 V - 10 15 µA

i(VBAT)

=25°C

amb

= 2.5 V - 7 12 µA

i(VBAT)

= 3.0 V - 8 12 µA

i(VBAT)

=25°C

amb

= 3.0 V - 8 - µA

i(VBAT)

0.7V

DD(3V3)

--V

- - 0.3V

[10]

- - 0.4 V

-24µA

[15]

-1022µA

0 - 1.8 V

[1]

DD(3V3)

Max Unit

DD(3V3)

V

-V

LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 04 — 2 June 2009 24 of 37

NXP Semiconductors

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

Table 5. Static characteristics

T

=−40°C to +85°C for commercial applications, unless otherwise specified.

amb

Symbol Parameter Conditions Min Typ

V

o(XTAL2)

output voltage on

…continued

[1]

0 - 1.8 V

pin XTAL2

V

i(RTCX1)

input voltage on pin

0 - 1.8 V

RTCX1

V

o(RTCX2)

output voltage on

0 - 1.8 V

pin RTCX2

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.
[2] Core and internal rail.
[3] External rail.
[4] If V
[5] If V
[6] The RTC typically fails when V
[7] Including voltage on outputs in 3-state mode.
[8] V

DD(3V3)

[9] 3-state outputs go into 3-state mode when V
[10] Accounts for 100mV voltage drop in all supply lines.
[11] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[12] Minimum condition for VI= 4.5 V, maximum condition for VI= 5.5 V. V
[13] Applies to P0.25:16.
[14] Battery supply current on pin VBAT.
[15] Input leakage current to VSS.

< 3.0 V, the I/O pins are not 5 V tolerant, and the ADC input voltage is limited to V

DD(3V3)

< 3.0 V, the I/O pins are not 5 V tolerant.

DDA

drops below 1.6 V.

i(VBAT)

supply voltages must be present.

is grounded.

DD(3V3)

≥ 3.0 V and V

DDA

DD(3V3)

DDA

≥ 3.0 V.

= 3.0 V.

Max Unit

Table 6. ADC static characteristics

V

= 2.5 V to 3.6 V; T

DDA

=−40°C to +85°C unless otherwise specified. ADC frequency 4.5 MHz.

amb

Symbol Parameter Conditions Min Typ Max Unit

V

IA

C

ia

E

D

E

L(adj)

E

O

E

G

E

T

[1] Conditions: V

resolution at full speed.
[2] The ADC is monotonic, there are no missing codes.
[3] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 5.
[4] The integral non-linearity (E

appropriate adjustment of gain and offset errors. See Figure 5.
[5] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the

ideal curve. See Figure 5.
[6] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset

error, and the straight line which fits the ideal transfer curve. See Figure 5.
[7] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC

and the ideal transfer curve. See Figure 5.

LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 04 — 2 June 2009 25 of 37

analog input voltage 0 - V

DDA

analog input capacitance - - 1 pF
differential linearity error
integral non-linearity
offset error
gain error
absolute error

SSA

=0V, V

= 3.3 V and V

DDA

) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

L(adj)

= 3.3 V for 10-bit resolution at full speed; V

DD(3V3)

[1][2][3]

--±1 LSB

[1][4]

--±2 LSB

[1][5]

--±3 LSB

[1][6]

--±0.5 %

[1][7]

--±4 LSB

= 2.6 V, V

DDA

DD(3V3)

= 2.6 V for 8-bit

V

NXP Semiconductors

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

code

out

1023

1022

1021

1020

1019

1018

offset

error

(2)

7

(1)

6

5

(5)

4

(4)

3

(3)

2

gain
error

E

E

O

G

1

0

offset error

E

O

1 LSB
(ideal)

7123456

VIA (LSB

ideal

10241018 1019 1020 1021 1022 1023

)

− V

V

DDA

1 LSB =

1024

SSA

002aac046

(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential linearity error (ED).
(4) Integral non-linearity (E

L(adj)

).

(5) Center of a step of the actual transfer curve.

Fig 5. ADC conversion characteristics

LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 04 — 2 June 2009 26 of 37

NXP Semiconductors

8.1 Power consumption in Deep power-down mode

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

1.5

I

DD(CORE)

(µA)

1.25

1

0.75

0.5

−40 853510 60−15

Test conditions: Deep power-down mode entered; RTC off; SRAM off;
V

i(VBAT)

= V

DD(3V3)

= V

DDA

Fig 6. Core supply current I

voltages

15

I

BAT

(µA)

12.5

= 3.3 V.

DD(CORE)

002aae680

V

=1.8 V

DD(1V8)

1.7 V

1.65 V

Temperature (°C)

measured at different temperatures and supply

002aae681

RTC on; SRAM on
RTC on; SRAM off

10

7.5

5

−40 853510 60−15

Test conditions: Deep power-down mode entered; V
V

DD(3V3)=VDDA

Fig 7. Battery supply current I

LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.

= 3.3 V.

measured at different temperatures and conditions

BAT

i(BAT)

= 3.3 V; V

RTC off; SRAM on
RTC off; SRAM off

Temperature (°C)

= 1.8 V;

DD(1V8)

Product data sheet Rev. 04 — 2 June 2009 27 of 37

NXP Semiconductors

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

0.20

I

DD(IO)

(µA)

0.15

0.10

0.05

0

−40 853510 60−15

Test conditions: Deep power-down mode entered; RTC off; SRAM off; V
V

DD(1V8)

= 1.8 V; V

i(BAT)=VDDA

Fig 8. I/O supply current I

= 3.3 V.

measured at different temperatures

DD(IO)

002aae682

Temperature (°C)

= 3.3 V;

DD(3V3)

LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 04 — 2 June 2009 28 of 37

NXP Semiconductors

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

9. Dynamic characteristics

Table 7. Dynamic characteristics

T

=0°Cto70°C for commercial applications,−40°C to +85°C for industrial applications, V

amb

specified ranges

Symbol Parameter Conditions Min Typ

External clock

f

osc

T

cy(clk)

t

CHCX

t

CLCX

t

CLCH

t

CHCL

Port pins (except P0.2 and P0.3)

t

r(o)

t

f(o)

2

C-bus pins (P0.2 and P0.3)

I

t

f(o)

[1]

.

oscillator frequency 10 - 25 MHz
clock cycle time 40 - 100 ns
clock HIGH time T
clock LOW time T

× 0.4 - - ns

cy(clk)

× 0.4 - - ns

cy(clk)

clock rise time - - 5 ns
clock fall time - - 5 ns

output rise time - 10 - ns
output fall time - 10 - ns

output fall time VIH to V

IL

20 + 0.1 × C

[3]

--ns

b

DD(1V8)

[2]

, V

DD(3V3)

over

Max Unit

[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.
[3] Bus capacitance Cb in pF, from 10 pF to 400 pF.

10. Application information

10.1 XTAL1 input

The input voltage to the on-chip oscillators is limited to 1.8 V.If the oscillator is driven by a
clock in slave mode, it is recommended that the input be coupled through a capacitor with
Ci = 100 pF. To limit the input voltage to the specified range, choose an additional
capacitor to ground Cgwhich attenuates the input voltage by a factor Ci/(Ci+Cg). In slave
mode, a minimum of 200 mV (RMS) is needed. For more details see the

User manual UM10161

.

LPC2xxx

XTAL1

C

i

100 pF

C

g

LPC2101/02/03

002aae718

Fig 9. Slave mode operation of the on-chip oscillator

LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 04 — 2 June 2009 29 of 37

NXP Semiconductors

10.2 XTAL and RTC Printed Circuit Board (PCB) layout guidelines

The crystal should be connected on the PCB as close as possible to the oscillator input
and output pins of the chip. Take care that the load capacitors Cx1 and Cx2, and Cx3 in
case of third overtone crystal usage, have a common ground plane. The external
components must also be connected to the ground plain. Loops must be made as small
as possible, in order to keep the noise coupled in via the PCB as small as possible. Also
parasitics should stay as small as possible. Values of Cx1 and Cx2 should be chosen
smaller accordingly to the increase in parasitics of the PCB layout.

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 04 — 2 June 2009 30 of 37

NXP Semiconductors

11. Package outline

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm

c

y

X

36

37

pin 1 index

48

25

24

Z

E

e

w M

b

p

13

A

H

E

E

A

2

A

SOT313-2

(A )

A

1

L

3

θ

L

p

1

e

DIMENSIONS (mm are the original dimensions)

A

UNIT

mm

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE

VERSION

SOT313-2 MS-026136E05

A1A2A3bpcE

max.

0.20

0.05

1.45

1.35

IEC JEDEC JEITA

1.6

b

p

0.25

w M

D

H

D

0.27

0.17

12

Z

D

B

0 2.5 5 mm

(1)

(1) (1)(1)

D

7.1

0.18

0.12

7.1

6.9

6.9

REFERENCES

v M

v M

scale

H

eHELL

9.15

0.5

8.85

detail X

A

B

Zywv θ

Z

D

0.95

0.55

E

0.95

7

0.55

0

ISSUE DATE

00-01-19
03-02-25

o
o

0.75

0.45

p

0.12 0.10.21

EUROPEAN

PROJECTION

D

9.15

8.85

Fig 10. Package outline SOT313-2 (LQFP48)

LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 04 — 2 June 2009 31 of 37

NXP Semiconductors

HVQFN48: plastic thermal enhanced very thin quad flat package; no leads;
48 terminals; body 7 x 7 x 0.85 mm

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

SOT619-7

terminal 1
index area

L

D

e

1

e

13 24

12

1/2 e

A

B

E

M

b

v

M

Cw

25

e

A

A

1

detail X

C

B

AC

y

C

1

c

y

E

h

1

terminal 1
index area

DIMENSIONS (mm are the original dimensions)

(1)

A

UNIT

mm

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included

OUTLINE

VERSION

SOT619-7 - - -

max

1

A

0.05

0.00

48 37

c

b

1

0.30

0.2

0.18

IEC JEDEC JEITA

- - -

D

7.1

6.9

(1)

D

h

D

h

3.45

3.15

MO-220

(1)

E

E

h

7.1

3.45

6.9

3.15

REFERENCES

0 2.5 5 mm

e

2

1/2 e

36

scale

ee

1

X

L v

e

2

0.5

5.50.5

0.3

0.15.5

PROJECTION

w

0.05y0.05

EUROPEAN

y

0.1

1

ISSUE DATE

05-10-24
05-10-25

Fig 11. Package outline SOT619-7 (HVQFN48)

LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 04 — 2 June 2009 32 of 37

NXP Semiconductors

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

HVQFN48: plastic thermal enhanced very thin quad flat package; no leads;
48 terminals; body 6 x 6 x 0.85 mm

A

B

E

M

AC

v

M

Cw

25

terminal 1
index area

L

D

e

1

e

13 24

12

1/2 e

b

SOT778-3

A

A

1

detail X

C

B

y

C

1

y

c

E

h

1/2 e

1

terminal 1
index area

DIMENSIONS (mm are the original dimensions)

(1)

A

UNIT

max

0.05

1

mm

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included

OUTLINE

VERSION

SOT778-3 - - -

0.00

48 37

0.2

(1)

D

c

6.1

5.9

A

b

1

0.25

0.15

IEC JEDEC JEITA

- - -

D

h

(1)

E

D

h

6.1

3.95

5.9

3.65

REFERENCES

- - -

36

0 2.5 5 mm

E

ee

h

3.95

3.65

e

e

2

X

scale

L v

e

1

2

0.5

4.40.4

0.3

0.14.4

PROJECTION

w

0.05y0.05

EUROPEAN

y

0.1

1

ISSUE DATE

04-06-16
04-06-23

Fig 12. Package outline SOT778-3 (HVQFN48)

LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 04 — 2 June 2009 33 of 37

NXP Semiconductors

12. Abbreviations

Table 8. Acronym list

Acronym Description

ADC Analog-to-Digital Converter
AMBA Advanced Microcontroller Bus Architecture
APB Advanced Peripheral Bus
DCC Debug Communications Channel
DSP Digital Signal Processor
FIFO First In, First Out
FIQ Fast Interrupt reQuest
GPIO General Purpose Input/Output
IAP In-Application Programming
IRQ Interrupt Request
ISP In-System Programming
PLL Phase-Locked Loop
PWM Pulse Width Modulator
SPI Serial Peripheral Interface
SRAM Static Random Access Memory
SSI Synchronous Serial Interface
SSP Synchronous Serial Port
TTL Transistor-Transistor Logic
UART Universal Asynchronous Receiver/Transmitter
VIC Vectored Interrupt Controller

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 04 — 2 June 2009 34 of 37

NXP Semiconductors

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

13. Revision history

Table 9. Revision history

Document ID Release date Data sheet status Change

notice

LPC2101_02_03_4 20090602 Product data sheet LPC2101_02_03_3
Modifications:

• Section 6.17.4 “Code security (Code Read Protection - CRP)”: added description of three

CRP levels (applicable to Revision A and higher).

• Section 6.17.7 “Power control”: added description of Deep power-down mode (applicable to

Revision A and higher).

• Section 10.1 “XTAL1 input” added.

• Section 10.2 “XTAL and RTC Printed Circuit Board (PCB) layout guidelines” added.

• Figure 6, Figure 7, Figure 8: added power consumption data for Deep power-down mode

(applicable to Revision A and higher).

• Table 3: added table note 7.

• Table 3: modified description of P0.14, RTCX1, RTCX2, XTAL1, XTAL2,JTAG, and DBGSEL

pins.

• Table 4: modified value for V

• Table 5: added and modified values for V

• Table 5: Voltage range for pins V

LPC2101_02_03_3 20081007 Product data sheet - LPC2101_02_03_2
Modifications:

• Updated data sheet status to Product data sheet.

DD(3V3)

DD(3V3)

.

.

hys

and V

extended to 2.6 V.

DDA

• Table 1 and Table 2: added LPC2102FHN48 and LPC2103FHN48.

• Table 1, Table 2, Table 3 and related figures: removed LPC2103FA44.

• Table 3: updated pad descriptions.

• Table 3: updated description of pin 47, SCL1.

• Table 3: updated description of pins V

DDA

and V

DD(1V8)

• Table 4: changed storage temperature range from −40 °C/125 °C to −65 °C/150 °C.

• Table 5: added or modified values for I

DD(act)

, I

DD(pd)

, I

BATpd

• Table 5: removed “CCLK = 10 MHz” and associated values for I

• Section 5: added Figure 3.

• Section 11: added Figure 11.

LPC2101_02_03_2 20071218 Preliminary data sheet - LPC2101_02_03_1
LPC2101_02_03_1 20060118 Preliminary data sheet - -

.

, I

Supersedes

.

BATact

.

DD(act)

LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 04 — 2 June 2009 35 of 37

NXP Semiconductors

14. Legal information

14.1 Data sheet status

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

Document status

Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s)described in this document may havechanged since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL

[1][2]

Product status

14.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability fortheconsequencesof
use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.

14.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However,NXP Semiconductors does not give any representations or
warranties, expressedor implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.

Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental

[3]

http://www.nxp.com.

Definition

damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.

Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at

http://www.nxp.com/profile/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyanceor implication of any license under any copyrights, patents
or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.

14.4 Trademarks

Notice: All referencedbrands,product names, service names and trademarks
are the property of their respective owners.

I2C-bus — logo is a trademark of NXP B.V.

15. Contact information

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [e-mail]

LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 04 — 2 June 2009 36 of 37

NXP Semiconductors

16. Contents

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.1 Enhanced features . . . . . . . . . . . . . . . . . . . . . . 1

2.2 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

3.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

6 Functional description . . . . . . . . . . . . . . . . . . 10

6.1 Architectural overview. . . . . . . . . . . . . . . . . . . 10

6.2 On-chip flash program memory . . . . . . . . . . . 10

6.3 On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 11

6.4 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 11

6.5 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 12

6.5.1 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 12

6.6 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 12

6.7 Fast general purpose parallel I/O . . . . . . . . . . 13

6.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6.8 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6.8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6.9 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6.10 I

2

C-bus serial I/O controllers. . . . . . . . . . . . . . 14

6.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.11 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 14

6.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.12 SSP serial I/O controller . . . . . . . . . . . . . . . . . 15

6.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.13 General purpose 32-bit timers/external

event counters . . . . . . . . . . . . . . . . . . . . . . . . 15

6.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.14 General purpose 16-bit timers/external

event counters . . . . . . . . . . . . . . . . . . . . . . . . 16

6.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.15 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 16

6.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.16 Real-time clock. . . . . . . . . . . . . . . . . . . . . . . . 17

6.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.17 System control . . . . . . . . . . . . . . . . . . . . . . . . 17

6.17.1 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . 17

6.17.2 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.17.3 Reset and wake-up timer . . . . . . . . . . . . . . . . 18

6.17.4 Code security (Code Read Protection - CRP) 19

6.17.5 External interrupt inputs . . . . . . . . . . . . . . . . . 19

6.17.6 Memory mapping control . . . . . . . . . . . . . . . . 19

6.17.7 Power control. . . . . . . . . . . . . . . . . . . . . . . . . 19

6.17.8 APB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.18 Emulation and debugging. . . . . . . . . . . . . . . . 20

6.18.1 EmbeddedICE . . . . . . . . . . . . . . . . . . . . . . . . 21

6.18.2 RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 22

8 Static characteristics . . . . . . . . . . . . . . . . . . . 23

8.1 Power consumption in Deep power-down

mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

9 Dynamic characteristics. . . . . . . . . . . . . . . . . 29

10 Application information . . . . . . . . . . . . . . . . . 29

10.1 XTAL1 input . . . . . . . . . . . . . . . . . . . . . . . . . . 29

10.2 XTAL and RTC Printed Circuit Board (PCB)

layout guidelines. . . . . . . . . . . . . . . . . . . . . . . 30

11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 31

12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 34

13 Revision history . . . . . . . . . . . . . . . . . . . . . . . 35

14 Legal information . . . . . . . . . . . . . . . . . . . . . . 36

14.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 36

14.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

14.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 36

14.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 36

15 Contact information . . . . . . . . . . . . . . . . . . . . 36

16 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.

© NXP B.V. 2009. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [e-mail]

Document identifier: LPC2101_02_03_4

Date of release: 2 June 2009