LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers; 8 kB/16 kB/32 kB
flash with ISP/IAP, fast ports and 10-bit ADC
Rev. 04 — 2 June 2009 Product data sheet
1. General description
The LPC2101/02/03 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with
real-time emulation that combines the microcontroller with 8 kB, 16 kB or 32 kB of
embedded high-speed flash memory. A 128-bit wide memory interface and a unique
accelerator architecture enable 32-bit code execution at the maximum clock rate. For
critical performance in interrupt service routines and DSP algorithms, this increases
performance up to 30 % over Thumb mode. For critical code size applications, the
alternative 16-bit Thumb mode reduces code by more than 30 % with minimal
performance penalty.
Due to their tiny size and low power consumption, the LPC2101/02/03 are ideal for
applications where miniaturization is a key requirement. A blendof serial communications
interfaces ranging from multiple UARTs, SPI to SSP and two I2C-buses, combined with
on-chip SRAM of 2 kB/4 kB/8 kB, make these devices very well suited for communication
gateways and protocol converters. The superior performance also makes these devices
suitable for use as math coprocessors. Various 32-bit and 16-bit timers, an improved
10-bit ADC, PWM features through output match on all timers,and32 fastGPIO lines with
up to nine edge or level sensitive external interrupt pins make these microcontrollers
particularly suitable for industrial control and medical systems.
2. Features
2.1 Enhanced features
2.2 Key features
Enhanced features are available in parts LPC2101/02/03 labelled Revision A and higher:
n Deep power-down mode with option to retain SRAM memory and/or RTC.
n Three levels of flash Code Read Protection (CRP) implemented.
n 16-bit/32-bit ARM7TDMI-S microcontroller in tiny LQFP48 and HVQFN48 packages.
n 2 kB/4 kB/8 kB of on-chip static RAM and 8 kB/16 kB/32 kB of on-chip flash program
memory. 128-bit wide interface/accelerator enables high-speed 70 MHz operation.
n ISP/IAP via on-chip bootloader software. Single flash sector or full chip erase in
100 ms and programming of 256 bytes in 1 ms.
n EmbeddedICE-RT offers real-time debugging with the on-chip RealMonitor software.
n The 10-bit ADC provides eight analog inputs, with conversion times as low as 2.44 µs
per channel and dedicated result registers to minimize interrupt overhead.
n Two 32-bit timers/external event counters with combined seven capture and seven
compare channels.
NXP Semiconductors
n Two 16-bit timers/external event counters with combined three capture and seven
n Low power Real-Time Clock (RTC) with independent power and dedicated 32 kHz
n Multiple serial interfaces including two UARTs (16C550), two Fast I2C-buses
n Vectored interrupt controller with configurable priorities and vector addresses.
n Up to thirty-two, 5 V tolerant fast general purpose I/O pins.
n Up to 13 edge or level sensitive external interrupt pins available.
n 70 MHz maximum CPU clock available from programmable on-chip PLL with a
n On-chip integrated oscillator operates with an external crystal in the range from 1 MHz
n Power saving modes include Idle mode, Power-down mode with RTC active, and
n Individual enable/disable of peripheral functions as well as peripheral clock scaling for
n Processor wake-up from Power-down and Deep power-down (Revision A and higher)
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
compare channels.
clock input.
(400 kbit/s), SPI and SSP with buffering and variable data length capabilities.
possible input frequency of 10 MHz to 25 MHz and a settling time of 100 µs.
to 25 MHz.
Power-down mode.
additional power optimization.
mode via external interrupt or RTC.
3. Ordering information
Table 1. Ordering information
Type number Package
Name Description Version
LPC2101FBD48 LQFP48 plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2
LPC2102FBD48 LQFP48 plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2
LPC2103FBD48 LQFP48 plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2
LPC2102FHN48 HVQFN48 plastic thermal enhanced very thin quad flat package; no leads;
48 terminals; body 7 × 7 × 0.85 mm
LPC2103FHN48 HVQFN48 plastic thermal enhanced very thin quad flat package; no leads;
48 terminals; body 7 × 7 × 0.85 mm
LPC2103FHN48H HVQFN48 plastic thermal enhanced very thin quad flat package; no leads;
48 terminals; body 6 × 6 × 0.85 mm
3.1 Ordering options
Table 2. Ordering options
Type number Flash memory RAM ADC Temperature
LPC2101FBD48 8 kB 2 kB 8 inputs −40 to +85
LPC2102FBD48 16 kB 4 kB 8 inputs −40 to +85
LPC2103FBD48 32 kB 8 kB 8 inputs −40 to +85
LPC2102FHN48 16 kB 4 kB 8 inputs −40 to +85
LPC2103FHN48 32 kB 8 kB 8 inputs −40 to +85
LPC2103FHN48H 32 kB 8 kB 8 inputs −40 to +85
SOT619-7
SOT619-7
SOT778-3
range (°C)
LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 2 June 2009 2 of 37
NXP Semiconductors
4. Block diagram
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
P0[31:0]
EINT2 to
EINT0
3 × CAP0
4 × CAP1
3 × CAP2
3 × MAT0
4 × MAT1
3 × MAT2
4 × MAT3
AD0[7:0]
TMS
TRST
LPC2101/2102/2103
HIGH SPEED
GENERAL
PURPOSE I/O
ARM7 local bus
INTERNAL
SRAM
CONTROLLER
2 kB/4 kB/
8 kB SRAM
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
CAPTURE/COMPARE
EXTERNAL COUNTER
8 kB
BOOT ROM
MEMORY
ACCELERATOR
8 kB/16 kB/
32 kB FLASH
EXTERNAL
INTERRUPTS
TIMER 0/TIMER 1/
TIMER 2/TIMER 3
ADC
TEST/DEBUG
INTERFACE
ARM7TDMI-S
AHB BRIDGE
AHB TO APB
TDI
TCK
BRIDGE
TDO
system
clock
AMBA AHB
(Advanced High-performance Bus)
APB (ARM
peripheral bus)
XTAL2 V
XTAL1
PLL
2
C-BUS SERIAL
I
INTERFACES 0 AND 1
SPI AND SSP
SERIAL INTERFACES
UART0/UART1
RST V
SYSTEM
FUNCTIONS
VECTORED
INTERRUPT
CONTROLLER
DD(3V3)
V
DD(1V8)
SS
SCL0, SCL1
SDA0, SDA1
SCK0, SCK1
MOSI0, MOSI1
MISO0, MISO1
SSEL0, SSEL1
TXD0, TXD1
RXD0, RXD1
DSR1, CTS1,
RTS1, DTR1
DCD1, RI1
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
P0[31:0]
GENERAL
PURPOSE I/O
WATCHDOG
TIMER
REAL-TIME CLOCK
SYSTEM CONTROL
002aab814
RTCX1
RTCX2
VBAT
(1) Pins shared with GPIO.
Fig 1. Block diagram
LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 2 June 2009 3 of 37
NXP Semiconductors
5. Pinning information
5.1 Pinning
Single-chip 16-bit/32-bit microcontrollers
SS
DDA
P0.14/DCD1/SCK1/EINT1
4847464544434241403938
DD(3V3)
V
LPC2101/02/03
P0.25/AD0.6
P0.12/DSR1/MAT1.0/AD0.5
37
P0.19/MAT1.2/MISO1 P0.11/CTS1/CAP1.1/AD0.4
P0.20/MAT1.3/MOSI1 P0.10/RTS1/CAP1.0/AD0.3
P0.21/SSEL1/MAT3.0 P0.24/AD0.2
V
DD(1V8)
P0.27/TRST/CAP2.0 P0.8/TXD1/MAT2.1
P0.28/TMS/CAP2.1 P0.7/SSEL0/MAT2.0
P0.29/TCK/CAP2.2 DBGSEL
1
2
3
4
VBAT P0.23/AD0.1
5
6
RST V
7
V
SS
8
9
10
11
XTAL1 RTCK
12
XTAL2 RTCX2
1314151617181920212223
P0.0/TXD0/MAT3.1 P0.18/CAP1.3/SDA1
LPC2101FBD48
LPC2102FBD48
LPC2103FBD48
DD(3V3)
V
P0.31/TDO P0.15/RI1/EINT2
P0.30/TDI/MAT3.3 P0.16/EINT0/MAT0.2
P0.1/RXD0/MAT3.2 P0.17/CAP1.2/SCL1
P0.2/SCL0/CAP0.0 V
SS
V
RTCX1 P0.13/DTR1/MAT1.1
P0.4/SCK0/CAP0.1 P0.26/AD0.7
P0.3/SDA0/MAT0.0 V
36
35
34
33
32
P0.22/AD0.0
31
SSA
30
P0.9/RXD1/MAT2.2
29
28
27
26
25
24
002aab821
P0.6/MOSI0/CAP0.2
P0.5/MISO0/MAT0.1
Fig 2. Pin configuration (LQFP48)
LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 2 June 2009 4 of 37
NXP Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
terminal 1
index area
P0.19/MAT1.2/MISO1
P0.20/MAT1.3/MOSI1
P0.21/SSEL1/MAT3.0
VBAT
V
DD(1V8)
RST
V
SS
P0.27/TRST/CAP2.0
P0.28/TMS/CAP2.1
P0.29/TCK/CAP2.2
XTAL1
XTAL2
P0.18/CAP1.3/SDA1
P0.17/CAP1.2/SCL1
P0.16/EINT0/MAT0.2
4847464544434241403938
1 36
2 35
3 34
4 33
5 32
6 31
7 30
8 29
9 28
10 27
11 26
12 25
1314151617181920212223
P0.0/TXD0/MAT3.1
LPC2103FHN48H
P0.30/TDI/MAT3.3
P0.1/RXD0/MAT3.2
Transparent top view
Fig 3. Pin configuration (HVQFN48)
P0.15/RI1/EINT2
DDA
P0.14/DCD1/SCK1/EINT1
VSSV
P0.13/DTR1/MAT1.1
LPC2102FHN48
LPC2103FHN48
SS
V
DD(3V3)
V
P0.31/TDO
RTCX1
P0.2/SCL0/CAP0.0
DD(3V3)
V
P0.26/AD0.7
P0.25/AD0.6
P0.12/DSR1/MAT1.0/AD0.5
37
24
P0.4/SCK0/CAP0.1
P0.3/SDA0/MAT0.0
P0.6/MOSI0/CAP0.2
P0.5/MISO0/MAT0.1
P0.11/CTS1/CAP1.1/AD0.4
P0.10/RTS1/CAP1.0/AD0.3
P0.24/AD0.2
P0.23/AD0.1
P0.22/AD0.0
V
SSA
P0.9/RXD1/MAT2.2
P0.8/TXD1/MAT2.1
P0.7/SSEL0/MAT2.0
DBGSEL
RTCK
RTCX2
002aad918
LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 2 June 2009 5 of 37
NXP Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
5.2 Pin description
Table 3. Pin description
Symbol Pin Type Description
P0.0 to P0.31 I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit.
A total of 31 pins of the Port 0 can be used as general purpose bidirectional
digital I/Os while P0.31 is an output only pin. The operation of port 0 pins
depends upon the pin function selected via the pin connect block.
P0.0/TXD0/
MAT3.1
P0.1/RXD0/
MAT3.2
P0.2/SCL0/
CAP0.0
P0.3/SDA0/
MAT0.0
P0.4/SCK0/
CAP0.1
P0.5/MISO0/
MAT0.1
P0.6/MOSI0/
CAP0.2
P0.7/SSEL0/
MAT2.0
P0.8/TXD1/
MAT2.1
P0.9/RXD1/
MAT2.2
P0.10/RTS1/
CAP1.0/AD0.3
13
14
18
21
22
23
24
28
29
30
35
[1]
I/O P0.0 — General purpose input/output digital pin.
O TXD0 — Transmitter output for UART0.
O MAT3.1 — PWM output 1 for Timer 3.
[1]
I/O P0.1 — General purpose input/output digital pin.
I RXD0 — Receiver input for UART0.
O MAT3.2 — PWM output 2 for Timer 3.
[2]
I/O P0.2 — General purpose input/output digital pin. Output is open-drain.
2
I/O SCL0 — I
C0 clock Input/output. Open-drain output (for I2C-bus compliance).
I CAP0.0 — Capture input for Timer 0, channel 0.
[2]
I/O P0.3 — General purpose input/output digital pin. Output is open-drain.
2
I/O SDA0 — I
C0 data input/output. Open-drain output (for I2C-bus compliance).
O MAT0.0 — PWM output for Timer 0, channel 0. Output is open-drain.
[1]
I/O P0.4 — General purpose input/output digital pin.
I/O SCK0 — Serial clock for SPI0. SPI clock output from master or input to slave.
I CAP0.1 — Capture input for Timer 0, channel 1.
[1]
I/O P0.5 — General purpose input/output digital pin.
I/O MISO0 — Master In Slave Out for SPI0. Data input to SPI master or data
output from SPI slave.
O MAT0.1 — PWM output for Timer 0, channel 1.
[1]
I/O P0.6 — General purpose input/output digital pin.
I/O MOSI0 — Master Out Slave In for SPI0. Data output from SPI master or data
input to SPI slave.
I CAP0.2 — Capture input for Timer 0, channel 2.
[1]
I/O P0.7 — General purpose input/output digital pin.
I SSEL0 — Slave Select for SPI0. Selects the SPI interface as a slave.
O MAT2.0 — PWM output for Timer 2, channel 0.
[1]
I/O P0.8 — General purpose input/output digital pin.
O TXD1 — Transmitter output for UART1.
O MAT2.1 — PWM output for Timer 2, channel 1.
[1]
I/O P0.9 — General purpose input/output digital pin.
I RXD1 — Receiver input for UART1.
O MAT2.2 — PWM output for Timer 2, channel 2.
[3]
I/O P0.10 — General purpose input/output digital pin.
O RTS1 — Request to Send output for UART1.
I CAP1.0 — Capture input for Timer 1, channel 0.
I AD0.3 — ADC 0, input 3.
LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 2 June 2009 6 of 37
NXP Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
Table 3. Pin description
…continued
Symbol Pin Type Description
P0.11/CTS1/
CAP1.1/AD0.4
36
[3]
I/O P0.11 — General purpose input/output digital pin.
I CTS1 — Clear to Send input for UART1.
I CAP1.1 — Capture input for Timer 1, channel 1.
I AD0.4 — ADC 0, input 4.
P0.12/DSR1/
MAT1.0/AD0.5
37
[3]
I/O P0.12 — General purpose input/output digital pin.
I DSR1 — Data Set Ready input for UART1.
O MAT1.0 — PWM output for Timer 1, channel 0.
I AD0.5 — ADC 0, input 5.
P0.13/DTR1/
MAT1.1
41
[1]
I/O P0.13 — General purpose input/output digital pin.
O DTR1 — Data Terminal Ready output for UART1.
O MAT1.1 — PWM output for Timer 1, channel 1.
P0.14/DCD1/
SCK1/EINT1
44
[4][5]
I/O P0.14 — General purpose input/output digital pin.
I DCD1 — Data Carrier Detect input for UART1.
I/O SCK1 — Serial Clock for SPI1. SPI clock output from master or input to slave.
I EINT1 — External interrupt 1 input.
P0.15/RI1/
EINT2
45
[4]
I/O P0.15 — General purpose input/output digital pin.
I RI1 — Ring Indicator input for UART1.
I EINT2 — External interrupt 2 input.
P0.16/EINT0/
MAT0.2
46
[4]
I/O P0.16 — General purpose input/output digital pin.
I EINT0 — External interrupt 0 input.
O MAT0.2 — PWM output for Timer 0, channel 2.
P0.17/CAP1.2/
SCL1
47
[6]
I/O P0.17 — General purpose input/output digital pin. The output is not
open-drain.
I CAP1.2 — Capture input for Timer 1, channel 2.
I/O SCL1 — I
function is selected in the pin connect block.
P0.18/CAP1.3/
SDA1
48
[6]
I/O P0.18 — General purpose input/output digital pin. The output is not
open-drain.
I CAP1.3 — Capture input for Timer 1, channel 3.
I/O SDA1 — I
function is selected in the pin connect block.
P0.19/MAT1.2/
MISO1
[1]
1
I/O P0.19 — General purpose input/output digital pin.
O MAT1.2 — PWM output for Timer 1, channel 2.
I/O MISO1 — Master In Slave Out for SSP. Data input to SSP master or data
output from SSP slave.
P0.20/MAT1.3/
MOSI1
[1]
2
I/O P0.20 — General purpose input/output digital pin.
O MAT1.3 — PWM output for Timer 1, channel 3.
I/O MOSI1 — Master Out Slave for SSP. Data output from SSP master or data
input to SSP slave.
P0.21/SSEL1/
MAT3.0
[1]
3
I/O P0.21 — General purpose input/output digital pin.
I SSEL1 — Slave Select for SPI1. Selects the SPI interface as a slave.
O MAT3.0 — PWM output for Timer 3, channel 0.
2
C1 clock Input/output. This pin is an open-drain output if I2C1
2
C1 data Input/output. This pin is an open-drain output if I2C1
LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 2 June 2009 7 of 37
NXP Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
Table 3. Pin description
…continued
Symbol Pin Type Description
P0.22/AD0.0 32
[3]
I/O P0.22 — General purpose input/output digital pin.
I AD0.0 — ADC 0, input 0.
P0.23/AD0.1 33
[3]
I/O P0.23 — General purpose input/output digital pin.
I AD0.1 — ADC 0, input 1.
P0.24/AD0.2 34
[3]
I/O P0.24 — General purpose input/output digital pin.
I AD0.2 — ADC 0, input 2.
P0.25/AD0.6 38
[3]
I/O P0.25 — General purpose input/output digital pin.
I AD0.6 — ADC 0, input 6.
P0.26/AD0.7 39
[3]
I/O P0.26 — General purpose input/output digital pin.
I AD0.7 — ADC 0, input 7.
P0.27/
CAP2.0
TRST/
[1]
8
I/O P0.27 — General purpose input/output digital pin.
I
TRST — Test Reset for JTAG interface. If DBGSEL is HIGH, this pin is
automatically configured for use with EmbeddedICE (Debug mode).
I CAP2.0 — Capture input for Timer 2, channel 0.
P0.28/TMS/
CAP2.1
[1]
9
I/O P0.28 — General purpose input/output digital pin.
I TMS — Test Mode Select for JTAG interface. If DBGSEL is HIGH, this pin is
automatically configured for use with EmbeddedICE (Debug mode).
I CAP2.1 — Capture input for Timer 2, channel 1.
P0.29/TCK/
CAP2.2
10
[1]
I/O P0.29 — General purpose input/output digital pin.
I TCK — Test ClockforJTAGinterface.This clock must be slower than
1
⁄6of the
CPU clock (CCLK) for the JTAG interface to operate. If DBGSEL is HIGH, this
pin is automatically configured for use with EmbeddedICE (Debug mode).
I CAP2.2 — Capture input for Timer 2, channel 2.
P0.30/TDI/
MAT3.3
15
[1]
I/O P0.30 — General purpose input/output digital pin.
I TDI — Test Data In for JTAG interface. If DBGSEL is HIGH, this pin is
automatically configured for use with EmbeddedICE (Debug mode).
O MAT3.3 — PWM output 3 for Timer 3.
P0.31/TDO 16
[1]
O P0.31 — General purpose output only digital pin.
O TDO — Test Data Out for JTAG interface. If DBGSEL is HIGH, this pin is
automatically configured for use with EmbeddedICE (Debug mode).
RTCX1 20
RTCX2 25
RTCK 26
[7][8]
[7][8]
[7]
I Input to the RTC oscillator circuit. Input voltage must not exceed 1.8 V.
O Output from the RTC oscillator circuit.
I/O Returned test clock output: Extra signal added to the JTAG port. Assists
debugger synchronization when processor frequency varies. Bidirectional pin
with internal pull-up.
XTAL1 11 I Input to the oscillator circuit and internal clock generator circuits. Input voltage
must not exceed 1.8 V.
XTAL2 12 O Output from the oscillator amplifier.
DBGSEL 27 I Debug select: When LOW, the part operates normally. When externally
pulled HIGH at reset, P0.27 to P0.31 are configured as JTAG port, and the
part is in Debug mode
[9]
. Input with internal pull-down.
RST 6 I External reset input: A LOW on this pin resets the device, causing I/O ports
and peripherals to take on their default states and processor execution to
begin at address 0. TTL with hysteresis, 5 V tolerant.
LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 2 June 2009 8 of 37
NXP Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
Table 3. Pin description
…continued
Symbol Pin Type Description
V
SS
V
SSA
V
DDA
7, 19, 43 I Ground: 0 V reference.
31 I Analog ground: 0 V reference. This should be nominally the same voltage as
V
but should be isolated to minimize noise and error.
SS
42 I Analog 3.3 V power supply: This should be nominally the same voltage as
V
but should be isolated to minimize noise and error. The level on this
DD(3V3)
pin also provides a voltage reference level for the ADC.
V
DD(1V8)
5I1.8 V core power supply: This is the power supply voltage for internal
circuitry and the on-chip PLL.
V
DD(3V3)
17, 40 I 3.3 V pad power supply: This is the power supply voltage for the I/O ports.
VBAT 4 I RTC power supply: 3.3 V on this pin supplies the power to the RTC.
[1] 5 V tolerant (if V
[2] Open-drain 5 V tolerant (if V
pull-up to provide an output functionality. Open-drain configuration applies to ALL functions on that pin.
[3] 5 V tolerant (if V
analog input function. If configured for an input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns. When
configured as an ADC input, digital section of the pad is disabled.
[4] 5 V tolerant (if V
If configured for an input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns.
[5] A LOW level during reset on pin P0.14 is considered as an external hardware request to start the ISP command handler.
[6] Open-drain 5 V tolerant (if V
pull-up to provide an output functionality. Open-drain configuration applies only to I2C function on that pin.
[7] Pad provides special analog functionality.
[8] For lowest power consumption, pin should be left floating when the RTC is not used.
[9] See
LPC2101/02/03 User manual UM10161
DD(3V3)
DD(3V3)
DD(3V3)
and V
and V
and V
≥ 3.0 V) pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.
DDA
and V
DD(3V3)
≥ 3.0 V) pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and
DDA
≥ 3.0 V) pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.
DDA
and V
DD(3V3)
≥ 3.0 V) digital I/O I2C-bus 400 kHz specification compatible pad. It requires external
DDA
≥ 3.0 V) digital I/O I2C-bus 400 kHz specification compatible pad. It requires external
DDA
for details.
LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 2 June 2009 9 of 37
NXP Semiconductors
6. Functional description
6.1 Architectural overview
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed Complex
Instruction Set Computers (CISC). This simplicity results in a high instruction throughput
and impressive real-time interrupt response from a small and cost-effective processor
core.
Pipeline techniques are employed so that allparts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as
Thumb, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:
• The standard 32-bit ARM set.
• A 16-bit Thumb set.
The Thumb set’s 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16-bit processor using 16-bit registers. This is possible because Thumb code
operates on the same 32-bit register set as ARM code.
Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the
performance of an equivalent ARM processor connected to a 16-bit memory system.
The particular flash implementation in the LPC2101/02/03 allows for full speed execution
also in ARM mode. It is recommended to program performance critical and short code
sections in ARM mode. The impact on the overallcode size will be minimal but the speed
can be increased by 30 % over Thumb mode.
6.2 On-chip flash program memory
The LPC2101/02/03 incorporate a 8 kB, 16 kB or 32 kB flash memory system
respectively. This memory may be used for both code and data storage. Programming of
the flash memory maybe accomplished in several ways. It may be programmed in system
via the serial port. The application programmay also erase and/or program the flash while
the application is running, allowing a great degree of flexibility for data storage field
firmware upgrades, etc. The entire flash memory is available for user code as the
bootloader resides in a separate memory.
The LPC2101/02/03 flash memory provides a minimum of 100,000 erase/write cycles and
20 years of data-retention memory.
LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 2 June 2009 10 of 37
NXP Semiconductors
6.3 On-chip static RAM
On-chip static RAM may be used for code and/or data storage. The SRAM may be
accessed as 8-bits, 16-bits, and 32-bits. The LPC2101/02/03 provide 2 kB,4 kB or 8 kB of
static RAM.
6.4 Memory map
The LPC2101/02/03 memory map incorporates several distinct regions, as shown in
Figure 4.
In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either
flash memory (the default) or on-chip static RAM. This is described in Section 6.17
“System control”.
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
4.0 GB
3.75 GB
3.5 GB
3.0 GB
2.0 GB
1.0 GB
0.0 GB
AHB PERIPHERALS
APB PERIPHERALS
RESERVED ADDRESS SPACE
BOOT BLOCK
RESERVED ADDRESS SPACE
8 kB ON-CHIP STATIC RAM (LPC2103)
4 kB ON-CHIP STATIC RAM (LPC2102)
2 kB ON-CHIP STATIC RAM (LPC2101)
RESERVED ADDRESS SPACE
32 kB ON-CHIP NON-VOLATILE MEMORY
(LPC2103)
16 kB ON-CHIP NON-VOLATILE MEMORY
(LPC2102)
8 kB ON-CHIP NON-VOLATILE MEMORY
(LPC2101)
0xFFFF FFFF
0xF000 0000
0xE000 0000
0xC000 0000
0x8000 0000
0x7FFF FFFF
0x7FFF E000
0x7FFF DFFF
0x4000 2000
0x4000 1FFF
0x4000 1000
0x4000 0FFF
0x4000 0800
0x4000 07FF
0x4000 0000
0x0000 8000
0x0000 7FFF
0x0000 4000
0x0000 3FFF
0x0000 2000
0x0000 1FFF
0x0000 0000
002aab822
Fig 4. LPC2101/02/03 memory map
LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 2 June 2009 11 of 37
NXP Semiconductors
6.5 Interrupt controller
The VIC accepts all of the interrupt request inputs and categorizes them as FIQ, vectored
IRQ, and non-vectored IRQ as defined by programmable settings. The programmable
assignment scheme means that priorities ofinterrupts from thevarious peripherals can be
dynamically assigned and adjusted.
FIQ has the highest priority. If more than one request is assigned to FIQ, the VIC
combines the requests to produce the FIQ signal to the ARM processor. The fastest
possible FIQ latency is achieved when only one requestis classified as FIQ, because then
the FIQ service routine does not need to branch into the interrupt service routine but can
run from the interrupt vector location. If more than one request is assigned to the FIQ
class, the FIQ service routine will read a word from the VIC that identifies which FIQ
source(s) is (are) requesting an interrupt.
Vectored IRQs have the middle priority.Sixteen of the interrupt requests can be assigned
to this category. Any of the interrupt requests can be assigned to any of the 16 vectored
IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.
Non-vectored IRQs have the lowest priority.
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
The VIC combines the requests from all the vectored and non-vectored IRQs to produce
the IRQ signal to the ARM processor. The IRQ service routine can start by reading a
register from the VIC and jumping there. If any of the vectored IRQs are pending, the VIC
provides the address of the highest-priority requesting IRQs service routine, otherwise it
provides the address of a default routine that is shared by all the non-vectored IRQs. The
default routine can read another VIC register to see what IRQs are active.
6.5.1 Interrupt sources
Each peripheral device has one interrupt line connected to the Vectored Interrupt
Controller,but may have several internal interrupt flags. Individual interrupt flags may also
represent more than one interrupt source.
6.6 Pin connect block
The pin connect block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on chip peripherals. Peripherals should be connected to the appropriate pins
prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any
enabled peripheral function that is not mapped to a related pin should be considered
undefined.
The pin control module with its pin select registers defines the functionality of the
microcontroller in a given hardware environment.
After reset all pins of Port 0 are configured as input with the following exceptions: If the
DBGSEL pin is HIGH (Debug mode enabled), the JTAG pins will assume their JTAG
functionality for use with EmbeddedICE and cannot be configured via the pin connect
block.
LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 2 June 2009 12 of 37
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