NXP LPC178x, LPC177x User Manual

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller; up to 512 kB flash and 96 kB SRAM; USB Device/Host/OTG; Ethernet; LCD; EMC

Rev. 5 — 9 September 2014 Product data sheet

1. General description

The LPC178x/7x is an ARM Cortex-M3 based microcontroller for embedded applications requiring a high level of integration and low power dissipation.

The ARM Cortex-M3 is a next generation core that of fers better performance than the ARM7 at the same clock rate and other system enhancements such as modernized debug features and a higher level of support block integration. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and has a Harvard architecture with separate local instruction and data buses, as well as a third bus with slightly lower performance for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branches.

The LPC178x/7x adds a specialized flash memory accelerator to accomplish optimal performance when executing code from flash. The LPC178x/7x operates at up to 120 MHz CPU frequency.

The peripheral complement of the LPC178x/7x includes up to 512 kB of flash program memory, up to 96 kB of SRAM data memory, up to 4032 byte of EEPROM data memory, External Memory Controller (EMC), LCD (LPC178x only), Ethernet, USB Device/Host/OTG, a General Purpose DMA controller, five UARTs, three SSP controllers,

three I two general purpose PWMs with six outputs each and one motor control PWM, an ultra-low power RTC with separa te battery supply and event recorder, a windowed watchdog timer, a CRC calculation engine, up to 165 general purpose I/O pins, and more.

The analog peripherals include one eight-channel 12-bit ADC and a 10-bit DAC. The pinout of LPC178x/7x is intended to allow pin function compatibility with the LPC24xx

and LPC23xx. For additional documentation, see Section 18 “

C-bus interfaces, a Quadrature Encoder Interface, four general purpose timers,

2. Features and benefits

 Functional replacement for the LPC23xx and LPC24xx family devices.  System:

 ARM Cortex-M3 processor, running at frequencies of up to 120 MHz. A Memory

Protection Unit (MPU) supporting eight regions is included.

 ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).

References”.

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

 Multilayer AHB matrix interconnect provides a separate bus for each AHB master.

AHB masters include the CPU, USB, Ethernet, and the General Purpose DMA controller. This interconnect provides communication with no arbitration delays unless two masters attempt to access the same slave at the same time.

 Split APB bus allows for higher throughput with fewer stalls between the CPU and

DMA. A single level of write buffering allows the CPU to continue without waiting for completion of APB writes if the APB was not already busy.

 Cortex-M3 system tick timer, including an external clock input option.  Standard JTAG test/debug interface as well as Serial Wire Debug and Serial

WireTrace Port options.

 Embedded Trace Macrocell (ETM) module supports real-time trace.  Boundary scan for simplified board testing.  Non-maskable Interrupt (NMI) input.

 Memory:

 Up to 512 kB on-chip flash program memory with In-System Programming (ISP)

and In-Application Programming (IAP) capabilities. The combination of an enhanced flash memory accelerator and location of the flash memory on the CPU local code/data bus provides high code performance from flash.

 Up to 96 kB on-chip SRAM includes:

64 kB of main SRAM on the CPU with local code/data bus for high-performance CPU access.

Two 16 kB peripheral SRAM blocks with se parate access paths for higher throughput. These SRAM blocks may be used for DMA memory as well as for general purpose instruction and data storage.

 Up to 4032 byte on-chip EEPROM.

 LCD controller, supporting both Super-Twisted Nematic (STN) and Thin-Film

Transistors (TFT) displays.

 Dedicated DMA controller.  Selectable display resolution (up to 1024  768 pixels).  Supports up to 24-bit true-color mode.

 External Memory Controller (EMC) provides support for asynchronous static memory

devices such as RAM, ROM and flash, as well as dynamic memories such as single data rate SDRAM with an SDRAM clock of up to 80 MHz.

 Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer

matrix that can be used with the SSP, I2S, UART, CRC engine, Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, GPIO, and for memory-to-memory transfers.

 Serial interfaces:

 Ethernet MAC with MII/RMII interface and associated DMA controller. These

functions reside on an independent AHB.

 USB 2.0 full-speed dual-port device/host/OTG controller with on-chip PHY and

associated DMA controller.

 Five UARTs with fractional baud rate generation, internal FIFO, DMA support, and

RS-485/EIA-485 support. One UART (UAR T1) has full modem control I/O, and one UART (USART4) supports IrDA, synchronous mode, and a smart card mode conforming to ISO7816-3.

 Three SSP controllers with FIFO and multi-protocol capabilities. The SSP

controllers can be used with the GPDMA.

Product data sheet Rev. 5 — 9 September 2014 2 of 122

LPC178x/7x

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

 Three enhanced I2C-bus interfaces, one with a true open-drain output supporting

the full I with standard port pins. Enhancement s include multiple address recognition and monitor mode.

 I

with the GPDMA.

 CAN controller with two channels.

 Digital peripherals:

 SD/MMC memory card interface.  Up to 165 General Purpose I/O (GPIO) pins depending on the packaging with

configurable pull-up/down resistors, open-drain mode, and repeater mode. All GPIOs are located on an AHB bus for fast access and support Cortex-M3 bit-banding. GPIOs can be accessed by the General Purpose DMA Controller. Any pin of ports 0 and 2 can be used to generate an interrupt.

 T wo external interrupt in puts configurable as e dge/level sensitive. All pi ns on port 0

and port 2 can be used as edge sensitive interrupt sources.

 Four general purpose timers/counters with a total of eight capture inputs and ten

compare outputs. Each timer block has an external count input. Specific timer events can be selected to generate DMA requests.

 Quadrature encoder interface that can monitor one external quadrature encoder.  Two standard PWM/timer blocks with external count input option.  One motor control PWM with support for three-phase motor control.  Real-Time Clock (RTC) with a separate power domain. The RTC is clocked by a

dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered backup registers, allowing system status to be stored when the rest of the chip is powered off. Battery power can be supplied from a sta ndard 3 V lithiu m button cell. The RTC will continue working when the battery voltage drops to as low as 2.1 V. An RTC interrupt can wake up the CPU from any reduced power mode.

 Event Recorder that can capture the clock value when an event occurs on any of

three inputs. The event identification and the time it occurred are stored in registers. The Event Recorder is located in the RTC power domain and can therefore operate as long as there is RTC power.

 Windowed Watchdog Timer (WWDT). Windowed operation, dedicated internal

oscillator, watchdog warning interrupt, and safety features.

 CRC Engine block can calculate a CRC on supplied data using one of three

standard polynomials. The CRC engine can be used in conjunction with the DMA controller to generate a CRC without CPU involvement in the data transfer.

 Analog peripherals:

 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins,

conversion rates up to 400 kHz, and multiple result registers. The 12-bit ADC can be used with the GPDMA controller.

 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and

GPDMA support.

 Power control:

 Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep

power-down.

C-bus specification and Fast-mode Plus with data rates of 1 Mbit/s, two

S-bus (Inter-IC Sound) interface for digital audio input or output. It can be used

Product data sheet Rev. 5 — 9 September 2014 3 of 122

NXP Semiconductors

 Clock generation:

 Versatile pin function selection feature allows many possibilities for using on-chip

 Unique device serial number for identification purposes.  Single 3.3 V power supply (2.4 V to 3.6 V). Temperature range of 40 C to 85 C.  Available as LQFP208, TFBGA208, TFBGA180, and LQFP144 package.

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

 The Wake-up Interrupt Controller (WIC) allows the CPU to automatically wake up

from any priority interrupt that can occur while the clocks are stopped in Deep-sleep, Power-down, and Deep power-down mo d es .

 Processor wake-up from Power-down mode via any interrupt able to operate

during Power-down mode (includes external interrupts, RTC interrupt, PORT0/2 pin interrupt, and NMI).

 Brownout detect with separate threshold for interrupt and forced reset.  On-chip Power-On Reset (POR).

 Clock output function that can reflect the main oscillator clock, IRC clock, RTC

clock, CPU clock, USB clock, or the watchdog timer clock.

 On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz.  12 MHz Internal RC oscillator (IRC) trimmed to 1% accuracy that can optionally be

used as a system clock.

 An on-chip PLL allows CPU operation up to the maximum CPU rate without the

need for a high-frequency crystal. May be run from the main oscillator or the internal RC oscillator.

 A second, dedicated PLL may be used for USB interface in order to allow added

flexibility for the Main PLL settings.

peripheral functions.

3. Applications

 Communications:

 Industrial/Medical:

 Consumer/Appliance:

 Automotive:

 Point-of-sale terminals, web servers, multi-protocol bridges

 Automation controllers, application control, robotics co ntrol, HVAC, PLC, inverters,

circuit breakers, medical scanning, security monitoring, motor drive, video intercom

 Audio, MP3 decoders, alarm systems, displays, printers, scanners, small

appliances, fitness equipment

 After-market, car alarms, GPS/fleet monitors

Product data sheet Rev. 5 — 9 September 2014 4 of 122

NXP Semiconductors

4. Ordering information

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 1. Ordering information

Type number Package

LPC1788

LPC1788FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1 LPC1788FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body

LPC1788FET180 TFBGA180 thin fine-p itch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3 LPC1788FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm SOT486-1

LPC1787

LPC1787FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1

LPC1786

LPC1786FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1

LPC1785

LPC1785FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1

LPC1778

LPC1778FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1 LPC1778FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body

LPC1778FET180 TFBGA180 thin fine-p itch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3 LPC1778FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm SOT486-1

LPC1777

LPC1777FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1

LPC1776

LPC1776FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1 LPC1776FET180 TFBGA180 thin fine-p itch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3

LPC1774

LPC1774FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1 LPC1774FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm SOT486-1

Name Description Version

SOT950-1

15 ´ 15 ´ 0.7 mm

SOT950-1

15 ´ 15 ´ 0.7 mm

Product data sheet Rev. 5 — 9 September 2014 5 of 122

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 2. LPC178x/7x ordering options

All parts include two CAN channels, three SSP interfaces, three I2C interfaces, one I2S interface, DAC, and an 8-channel 12-bit ADC.

Type number Flash

(kB)

Main SRAM (kB)

Peripheral SRAM (kB)

Total SRAM (kB)

EEPROM (byte)

Ethernet USB UART EMC

bus width

LCD QEI SD/

MMC

(bit)

[1]

LPC178x

LPC1788FBD208 512 64 16  2 96 4032 Y H/O/D 5 32 Y Y Y LPC1788FET208 512 64 16  2 96 4032 Y H/O/D 5 32 Y Y Y LPC1788FET180 512 64 16  2 96 4032 Y H/O/D 5 16 Y Y Y LPC1788FBD144 512 64 16  2 96 4032 Y H/O/D 5 8 Y Y Y LPC1787FBD208 512 64 16  2 96 4032 N H/O/D 5 32 Y Y Y LPC1786FBD208 256 64 16 80 4032 Y H/O/D 5 32 Y Y Y LPC1785FBD208 256 64 16 80 4032 N H/O/D 5 32 Y N Y

LPC177x

LPC1778FBD208 512 64 16  2 96 4032 Y H/O/D 5 32 N Y Y LPC1778FET208 512 64 16  2 96 4032 Y H/O/D 5 32 N Y Y LPC1778FET180 512 64 16  2 96 4032 Y H/O/D 5 16 N Y Y LPC1778FBD144 512 64 16  2 96 4032 Y H/O/D 5 8 N Y Y LPC1777FBD208 512 64 16  2 96 4032 N H/O/D 5 32 N Y Y LPC1776FBD208 256 64 16 80 4032 Y H/O/D 5 32 N Y Y LPC1776FET180 256 64 16 80 4032 Y H/O/D 5 16 N Y Y LPC1774FBD208 128 32 8 40 2048 N D 5 32 N N N

[2]

LPC1774FBD144 128 32 8 40 2048 N D 4

8 N N N

[1] Maximum data bus width of the External Memory Controller (EMC) depends on package size. Smaller widths may be used. [2] USART4 not available.

Product data sheet Rev. 5 — 9 September 2014 6 of 122

NXP Semiconductors

SRAM

96/80/40 kB

ARM

CORTEX-M3

TEST/DEBUG

INTERFACE

EMULATION

TRACE MODULE

FLASH

ACCELERATOR

FLASH

512/256/128/64 kB

GPDMA

CONTROLLER

I-code bus

D-code bus

system bus

AHB TO

APB

BRIDGE 0

HIGH-SPEED

GPIO

AHB TO

APB

BRIDGE 1

4032 B/

2048 B

EEPROM

CLOCK

GENERATION,

POWER CONTROL,

SYSTEM

FUNCTIONS

clocks and

controls

JTAG

interface

debug

port

SSP0/2

USART4

(1)

UART2/3

SYSTEM CONTROL

SSP1

UART0/1

I2C0/1

CAN 0/1

TIMER 0/1

WINDOWED WDT

12-bit ADC

PWM0/1

PIN CONNECT

GPIO INTERRUPT CONTROL

RTC

BACKUP REGISTERS

EVENT RECORDER

32 kHz

OSCILLATOR

APB slave group 1

APB slave group 0

RTC POWER DOMAIN

LPC178x/7x

master

ETHERNET

(1)

master

USB

DEVICE/

HOST

(1)

/OTG

(1)

master

002aaf528

slave

CRC

slave

ROM

EMC

slaveslave

LCD

(1)

slave

MULTILAYER AHB MATRIX

I2C2

TIMER2/3

DAC

I2S

QUADRATURE ENCODER

(1)

MOTOR CONTROL PWM

MPU

SD/MMC

(1)

= connected to GPDMA

5. Block diagram

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

(1) Not available on all parts. See Table 2.

Fig 1. Block diagram

Product data sheet Rev. 5 — 9 September 2014 7 of 122

NXP Semiconductors

LPC178x/7xFBD208

156

104

208

157

105

002aaf518

002aaf529

LPC178x/7x

Transparent top view

ball A1 index area

246810121314

15 17

1357911

6. Pinning information

6.1 Pinning

Fig 2. Pin configuration (LQFP208)

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Fig 3. Pin configuration (TFBGA208)

Product data sheet Rev. 5 — 9 September 2014 8 of 122

NXP Semiconductors

002aaf519

LPC178x/7x

2 4 6 8 10 12 13 141357911

ball A1 index area

Transparent top view

LPC178x/7x

108

144

109

002aaf520

Fig 4. Pin configuration (TFBGA180)

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Fig 5. Pin configuration (LQFP144)

6.2 Pin description

I/O pins on the LPC178x/7x are 5 V tolerant and have input hysteresis unless otherwise indicated in the table below. Crystal pins, power pins, and reference voltage pins are not 5 V tolerant. In addition, when pins are selected to be ADC inputs, they are no longer 5 V tolerant and the input voltage must be limited to the volt a ge at the ADC positive re ference pin (VREFP).

Product data sheet Rev. 5 — 9 September 2014 9 of 122

All port pins Pn[m] are multiplexed, and the multiplexed functions appear in Table 3 order defined by the FUNC bits of the corresponding IOCON register up to the highest used function number. Each port pin can support up to eight multiplexed functions. IOCON register FUNC values which are reserved are noted as ‘R’ in the pin configuration table.

in the

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 3. Pin description

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).

Symbol

P0[0] to P0[31]

[1]

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

Pin LQFP144

Reset state

Description

[2]

Type

I/O Port 0: Port 0 is a 32-bit I/O port with individual direction

controls for each bit. The operation of port 0 pins depends upon the pin function selected via the pin connect block.

P0[0] 94 U15 M10 66

[3]

I; PUI/O P0[0] — General purpose digital input/output pin.

I CAN_RD1 — CAN1 receiver input. O U3_TXD — Transmitter output for UART3.

I/O I2C1_SDA — I

C1 data input/output (this pin does not use a

specialized I2C pad).

O U0_TXD — Transmitter output for UART0.

[3]

P0[1] 96 T14 N11 67

I; PUI/O P0[1] — General purpose digital input/output pin.

O CAN_TD1 — CAN1 transmitter output. I U3_RXD — Receiver input for UART3.

I/O I2C1_SCL — I

C1 clock input/output (this pin does not use a

specialized I2C pad).

I U0_RXD — Receiver input for UART0.

[3]

P0[2] 202 C4 D5 141

I; PUI/O P0[2] — General purpose digital input/output pin.

O U0_TXD — Transmitter output for UART0. O U3_TXD — Transmitter output for UART3.

[3]

P0[3] 204 D6 A3 142

I; PUI/O P0[3] — General purpose digital input/output pin.

I U0_RXD — Receiver input for UART0. I U3_RXD — Receiver input for UART3.

[3]

P0[4] 168 B12 A11 116

I; PUI/O P0[4] — General purpose digital input/output pin.

I/O I2S_RX_SCK — I

S Receive clock. It is driven by the master

and received by the slave. Corresponds to the signal SCK in the

S-bus specification.

I CAN_RD2 — CAN2 receiver input. I T2_CAP0 — Capture input for Timer 2, channel 0.

- R — Function reserved.

- R — Function reserved. O LCD_VD[0] — LCD data.

Product data sheet Rev. 5 — 9 September 2014 10 of 122

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 3. Pin description

…continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

P0[5] 166 C12 B11 115

[1]

Pin LQFP144

Reset state

[3]

I; PUI/O P0[5] — General purpose digital input/output pin.

Description

[2]

Type

I/O I2S_RX_WS — I

S Receive word select. It is driven by the

master and received by the slave. Corresponds to the signal WS

in the I

S-bus specification.

O CAN_TD2 — CAN2 transmitter output. I T2_CAP1 — Capture input for Timer 2, channel 1.

- R — Function reserved.

- R — Function reserved. O LCD_VD[1] — LCD data.

[3]

P0[6] 164 D13 D11 113

I; PUI/O P0[6] — General purpose digital input/output pin.

I/O I2S_RX_SDA — I

S Receive data. It is driven by the transmitter

and read by the receiver. Corresponds to the signal SD in the

S-bus specification.

I/O SSP1_SSEL — Slave Select for SSP1. O T2_MAT0 — Match output for Timer 2, channel 0. O U1_RTS — Request to Send output for UART1. Can also be

configured to be an RS-485/EIA-485 output enable signal for UART1.

- R — Function reserved.

- R — Function reserved. O LCD_VD[8] — LCD data.

[4]

P0[7] 162 C13 B12 112

I; IA I/O P0[7] — General purpose digital input/output pin.

I/O I2S_TX_SCK — I

S transmit clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification.

I/O SSP1_SCK — Serial Clock for SSP1. O T2_MAT1 — Match output for Timer 2, channel 1. I RTC_EV0 — Event input 0 to Event Monitor/Recorder.

- R — Function reserved.

- R — Function reserved. O LCD_VD[9] — LCD data.

Product data sheet Rev. 5 — 9 September 2014 11 of 122

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 3. Pin description

…continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

P0[8] 160 A15 C12 111

[1]

Pin LQFP144

Reset state

[4]

I; IA I/O P0[8] — General purpose digital input/output pin.

Description

[2]

Type

I/O I2S_TX_WS — I

S Transmit word select. It is driven by the

master and received by the slave. Corresponds to the signal WS

in the I

S-bus specification.

I/O SSP1_MISO — Master In Slave Out for SSP1. O T2_MAT2 — Match output for Timer 2, channel 2. I RTC_EV1 — Event input 1 to Event Monitor/Recorder.

- R — Function reserved.

- R — Function reserved. O LCD_VD[16] — LCD data.

[4]

P0[9] 158 C14 A13 109

I; IA I/O P0[9] — General purpose digital input/output pin.

I/O I2S_TX_SDA — I

S transmit data. It is driven by the transm itter and read by the receiver. Corresponds to the signal SD in the

S-bus specification.

I/O SSP1_MOSI — Master Out Slave In for SSP1. O T2_MAT3 — Match output for Timer 2, channel 3. I RTC_EV2 — Event input 2 to Event Monitor/Recorder.

- R — Function reserved.

- R — Function reserved. O LCD_VD[17] — LCD data.

[3]

P0[10] 98 T15 L10 69

I; PUI/O P0[10] — General purpose digital input/output pin.

O U2_TXD — Transmitter output for UART2.

I/O I2C2_SDA — I

C2 data input/output (this pin does not use a

specialized I2C pad).

O T3_MAT0 — Match output for Timer 3, channel 0.

[3]

P0[11] 100 R14 P12 70

I; PUI/O P0[11] — General purpose digital input/output pin.

I U2_RXD — Receiver input for UART2.

I/O I2C2_SCL — I

C2 clock input/output (this pin does not use a

specialized I2C pad).

O T3_MAT1 — Match output for Timer 3, channel 1.

[5]

P0[12] 41 R1 J4 29

I; PUI/O P0[12] — General purpose digital input/output pin.

O USB_PPWR2

— Port Power enable signal for USB port 2. I/O SSP1_MISO — Master In Slave Out for SSP1. I ADC0_IN[6] — A/D converter 0, input 6. When configured as an

ADC input, the digital function of the pin must be disabled.

Product data sheet Rev. 5 — 9 September 2014 12 of 122

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 3. Pin description …continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

P0[13] 45 R2 J5 32

P0[14] 69 T7 M5 48

P0[15] 128 J16 H13 89

P0[16] 130 J14 H14 90

P0[17] 126 K17 J12 87

P0[18] 124 K15 J13 86

P0[19] 122 L17 J10 85

[1]

Pin LQFP144

Reset state

[5]

I; PUI/O P0[13] — General purpose digital input/output pin.

[3]

I; PUI/O P0[14] — General purpose digital input/output pin.

[3]

I; PUI/O P0[15] — General purpose digital input/output pin.

[3]

I; PUI/O P0[16] — General purpose digital input/output pin.

[3]

I; PUI/O P0[17] — General purpose digital input/output pin.

[3]

I; PUI/O P0[18] — General purpose digital input/output pin.

[3]

I; PUI/O P0[19] — General purpose digital input/output pin.

Description

[2]

Type

O USB_UP_LED2 — USB port 2 GoodLink LED indicator. It is

LOW when the device is configured (non-control endpoints enabled), or when the host is enabled and has detected a device on the bus. It is HIGH when the device is not configured, or when host is enabled and has not detected a device on the bus, or during global suspend. It transitions between LOW and HIGH (flashes) when the host is enabled and detects activity on

the bus. I/O SSP1_MOSI — Master Out Slave In for SSP1. I ADC0_IN[7] — A/D converter 0, input 7. When configured as an

ADC input, the digital function of the pin must be disabled.

O USB_HSTEN2

— Host Enabled status for USB port 2. I/O SSP1_SSEL — Slave Select for SSP1. O USB_CONNECT2 — SoftConnect control for USB port 2.

Signal used to switch an external 1.5 k resistor under software control. Used with the SoftConnect USB feature.

O U1_TXD — Transmitter output for UART1. I/O SSP0_SCK — Serial clock for SSP0.

I U1_RXD — Receiver input for UART1. I/O SSP0_SSEL — Slave Select for SSP0.

I U1_CTS — Clear to Send input for UART1. I/O SSP0_MISO — Master In Slave Out for SSP0.

I U1_DCD — Data Carrier Detect input for UART1. I/O SSP0_MOSI — Master Out Slave In for SSP0.

I U1_DSR — Data Set Ready input for UART1. O SD_CLK — Clock output line for SD card interface.

I/O I2C1_SDA — I

C1 data input/output (this pin does not use a

specialized I2C pad).

Product data sheet Rev. 5 — 9 September 2014 13 of 122

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 3. Pin description

…continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

P0[20] 120 M17 K14 83

[1]

Pin LQFP144

Reset state

[3]

I; PUI/O P0[20] — General purpose digital input/output pin.

Description

[2]

Type

O U1_DTR — Data Terminal Ready output for UART1. Can also

be configured to be an RS-485/EIA-485 output enable signal for UART1.

I/O SD_CMD — Command line for SD card interface.

I/O I2C1_SCL — I

C1 clock input/output (this pin does not use a

specialized I2C pad).

[3]

P0[21] 118 M16 K11 82

I; PUI/O P0[21] — General purpose digital input/output pin.

I U1_RI — Ring Indicator input for UART1. O SD_PWR — Power Supply Enable for external SD card power

supply. O U4_OE — RS-485/EIA-485 output enable signal for UART4. I CAN_RD1 — CAN1 receiver input. I/O U4_SCLK — USART 4 clock input or output in synchronous

mode.

[6]

P0[22] 116 N17 L14 80

I; PUI/O P0[22] — General purpose digital input/output pin.

O U1_RTS — Request to Send output for UART1. Can also be

configured to be an RS-485/EIA-485 output enable signal for

UART1. I/O SD_DAT[0] — Data line 0 for SD card interface. O U4_TXD — Transmitter output for USART4 (input/output in

smart card mode). O CAN_TD1 — CAN1 transmitter output.

[5]

P0[23] 18 H1 F5 13

I; PUI/O P0[23] — General purpose digital input/output pin.

I ADC0_IN[0] — A/D converter 0, input 0. When configured as an

ADC input, the digital function of the pin must be disabled. I/O I2S_RX_SCK — Receive Clock. It is driven by the master and

received by the slave. Corresponds to the signal SCK in the

S-bus specification.

I T3_CAP0 — Capture input for Timer 3, channel 0.

[5]

P0[24] 16 G2 E1 11

I; PUI/O P0[24] — General purpose digital input/output pin.

I ADC0_IN[1] — A/D converter 0, input 1. When configured as an

ADC input, the digital function of the pin must be disabled. I/O I2S_RX_WS — Receive Word Select. It is driven by the master

and received by the slave. Corresponds to the signal WS in the

S-bus specification.

I T3_CAP1 — Capture input for Timer 3, channel 1.

Product data sheet Rev. 5 — 9 September 2014 14 of 122

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 3. Pin description

…continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

P0[25] 14 F1 E4 10

[1]

Pin LQFP144

Reset state

[5]

I; PUI/O P0[25] — General purpose digital input/output pin.

Description

[2]

Type

I ADC0_IN[2] — A/D converter 0, input 2. When configured as an

ADC input, the digital function of the pin must be disabled. I/O I2S_RX_SDA — Receive data. It is driven by the transmitter

and read by the receiver. Corresponds to the signal SD in the

S-bus specification.

O U3_TXD — Transmitter output for UART3.

[7]

P0[26] 12 E1 D1 8

I; PUI/O P0[26] — General purpose digital input/output pin.

I ADC0_IN[3] — A/D converter 0, input 3. When configured as an

ADC input, the digital function of the pin must be disabled. O DAC_OUT — D/A converter output. When configured as the

DAC output, the digital function of the pin must be disabled. I U3_RXD — Receiver input for UART3.

[8]

P0[27] 50 T1 L3 35

I I/O P0[27] — General purpose digital input/output pin.

I/O I2C0_SDA — I

C0 data input/output (this pin uses a specialized

I2C pad). I/O USB_SDA1 — I2C serial data for communication with an

external USB transceiver.

[8]

P0[28] 48 R3 M1 34

I I/O P0[28] — General purpose digital input/output pin.

I/O I2C0_SCL — I

C0 clock input/output (this pin uses a

specialized I2C pad). I/O USB_SCL1 — I2C serial clock for communication with an

external USB transceiver.

[9]

P0[29] 61 U4 K5 42

I I/O P0[29] — General purpose digital input/output pin.

I/O USB_D+1 — USB port 1 bidirectional D+ line.

— External interrupt 0 input.

P0[30] 62 R6 N4 43

I EINT0

[9]

I I/O P0[30] — General purpose digital input/output pin.

I/O USB_D1 — USB port 1 bidirectional D line.

— External interrupt 1 input.

P0[31] 51 T2 N1 36

I EINT1

[9]

I I/O P0[31] — General purpose digital input/output pin.

I/O USB_D+2 — USB port 2 bidirectional D+ line.

P1[0] to P1[31]

I/O Port 1: Port 1 is a 32 bit I/O port with individual direction

controls for each bit. The operation of port 1 pins depends upon

the pin function selected via the pin connect block

[3]

P1[0] 196 A3 B5 136

I; PUI/O P1[0] — General purpose digital input/output pin.

O ENET_TXD0 — Ethernet transmit data 0 (RMII/MII interface).

- R — Function reserved. I T3_CAP1 — Capture input for Timer 3, channel 1. I/O SSP2_SCK — Serial clock for SSP2.

Product data sheet Rev. 5 — 9 September 2014 15 of 122

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 3. Pin description

…continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

P1[1] 194 B5 A5 135

[1]

Pin LQFP144

Reset state

[3]

I; PUI/O P1[1] — General purpose digital input/output pin.

Description

[2]

Type

O ENET_TXD1 — Ethernet transmit data 1 (RMII/MII interface).

- R — Function reserved. O T3_MAT3 — Match output for Timer 3, channel 3. I/O SSP2_MOSI — Master Out Slave In for SSP2.

[3]

P1[2] 185 D9 B7 -

I; PUI/O P1[2] — General purpose digital input/output pin.

O ENET_TXD2 — Ethernet transmit data 2 (MII interface). O SD_CLK — Clock output line for SD card interface. O PWM0[1] — Pulse Width Modulator 0, output 1.

[3]

P1[3] 177 A10 A9 -

I; PUI/O P1[3] — General purpose digital input/output pin.

O ENET_TXD3 — Ethernet transmit data 3 (MII interface). I/O SD_CMD — Command line for SD card interface. O PWM0[2] — Pulse Width Modulator 0, output 2.

[3]

P1[4] 192 A5 C6 133

I; PUI/O P1[4] — General purpose digital input/output pin.

O ENET_TX_EN — Ethernet transmit data enable (RMII/MII

interface).

- R — Function reserved. O T3_MAT2 — Match output for Timer 3, channel 2. I/O SSP2_MISO — Master In Slave Out for SSP2.

[3]

P1[5] 156 A17 B13 -

I; PUI/O P1[5] — General purpose digital input/output pin.

O ENET_TX_ER — Ethernet Transmit Error (MII interface). O SD_PWR — Power Supply Enable for external SD card power

supply. O PWM0[3] — Pulse Width Modulator 0, output 3.

[3]

P1[6] 171 B11 B10 -

I; PUI/O P1[6] — General purpose digital input/output pin.

I ENET_TX_CLK — Ethernet Transmit Clock (MII interface). I/O SD_DAT[0] — Data line 0 for SD card interface. O PWM0[4] — Pulse Width Modulator 0, output 4.

[3]

P1[7] 153 D14 C13 -

I; PUI/O P1[7] — General purpose digital input/output pin.

I ENET_COL — Ethernet Collision detect (MII interface). I/O SD_DAT[1] — Data line 1 for SD card interface. O PWM0[5] — Pulse Width Modulator 0, output 5.

Product data sheet Rev. 5 — 9 September 2014 16 of 122

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 3. Pin description

…continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

P1[8] 190 C7 B6 132

[1]

Pin LQFP144

Reset state

[3]

I; PUI/O P1[8] — General purpose digital input/output pin.

Description

[2]

Type

I ENET_CRS (ENET_CRS_DV) — Ethernet Carrier Sense (MII

interface) or Ethernet Carrier Sense/Data Valid (RMII interface).

- R — Function reserved. O T3_MAT1 — Match output for Timer 3, channel 1. I/O SSP2_SSEL — Slave Select for SSP2.

[3]

P1[9] 188 A6 D7 131

I; PUI/O P1[9] — General purpose digital input/output pin.

I ENET_RXD0 — Ethernet receive data 0 (RMII/MII interface).

- R — Function reserved. O T3_MAT0 — Match output for Timer 3, channel 0.

[3]

P1[10] 186 C8 A7 129

I; PUI/O P1[10] — General purpose digital input/output pin.

I ENET_RXD1 — Ethernet receive data 1 (RMII/MII interface).

- R — Function reserved. I T3_CAP0 — Capture input for Timer 3, channel 0.

[3]

P1[11] 163 A14 A12 -

I; PUI/O P1[11] — General purpose digital input/output pin.

I ENET_RXD2 — Ethernet Receive Data 2 (MII interface). I/O SD_DAT[2] — Data line 2 for SD card interface. O PWM0[6] — Pulse Width Modulator 0, output 6.

[3]

P1[12] 157 A16 A14 -

I; PUI/O P1[12] — General purpose digital input/output pin.

I ENET_RXD3 — Ethernet Receive Data (MII interface). I/O SD_DAT[3] — Data line 3 for SD card interface. I PWM0_CAP0 — Capture input for PWM0, channel 0.

[3]

P1[13] 147 D16 D14 -

I; PUI/O P1[13] — General purpose digital input/output pin.

I ENET_RX_DV — Ethernet Receive Data Valid (MII interface).

[3]

P1[14] 184 A7 D8 128

I; PUI/O P1[14] — General purpose digital input/output pin.

I ENET_RX_ER — Ethernet receive error (RMII/MII interface).

- R — Function reserved. I T2_CAP0 — Capture input for Timer 2, channel 0.

[3]

P1[15] 182 A8 A8 126

I; PUI/O P1[15] — General purpose digital input/output pin.

I ENET_RX_CLK (ENET_REF_CLK) — Ethernet Receive Clock

(MII interface) or Ethernet Reference Clock (RMII interface).

- R — Function reserved.

I/O I2C2_SDA — I

C2 data input/output (this pin does not use a

specialized I2C pad).

Product data sheet Rev. 5 — 9 September 2014 17 of 122

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 3. Pin description

…continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

P1[16] 180 D10 B8 125

[1]

Pin LQFP144

Reset state

[3]

I; PUI/O P1[16] — General purpose digital input/output pin.

Description

[2]

Type

O ENET_MDC — Ethernet MIIM clock. O I2S_TX_MCLK — I2S transmit master clock.

[3]

P1[17] 178 A9 C9 123

I; PUI/O P1[17] — General purpose digital input/output pin.

I/O ENET_MDIO — Ethernet MIIM data input and output. O I2S_RX_MCLK — I2S receive master clock.

[3]

P1[18] 66 P7 L5 46

I; PUI/O P1[18] — General purpose digital input/output pin.

O USB_UP_LED1 — It is LOW when the device is configured

(non-control endpoints enabled), or when the host is enabled

and has detected a device on the bus. It is HIGH when the

device is not configured, or when host is enabled and has not

detected a device on the bus, or during global suspend. It

transitions between LOW and HIGH (flashes) when the host is

enabled and detects activity on the bus. O PWM1[1] — Pulse Width Modulator 1, channel 1 output. I T1_CAP0 — Capture input for Timer 1, channel 0.

- R — Function reserved. I/O SSP1_MISO — Master In Slave Out for SSP1.

[3]

P1[19] 68 U6 P5 47

I; PUI/O P1[19] — General purpose digital input/output pin.

O USB_TX_E1

— Transmit Enable signal for USB port 1 (OTG

transceiver). O USB_PPWR1

— Port Power enable signal for USB port 1. I T1_CAP1 — Capture input for Timer 1, channel 1. O MC_0A — Motor control PWM channel 0, output A. I/O SSP1_SCK — Serial clock for SSP1. O U2_OE — RS-485/EIA-485 output enable signal for UART2.

[3]

P1[20] 70 U7 K6 49

I; PUI/O P1[20] — General purpose digital input/output pin.

O USB_TX_DP1 — D+ transmit data for USB port 1 (OTG

transceiver). O PWM1[2] — Pulse Width Modulator 1, channel 2 output. I QEI_PHA — Quadrature Encoder Interface PHA input. I MC_FB0 — Motor control PWM channel 0 feedback input. I/O SSP0_SCK — Serial clock for SSP0. O LCD_VD[6] — LCD data. O LCD_VD[10] — LCD data.

Product data sheet Rev. 5 — 9 September 2014 18 of 122

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 3. Pin description

…continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

P1[21] 72 R8 N6 50

[1]

Pin LQFP144

Reset state

[3]

I; PUI/O P1[21] — General purpose digital input/output pin.

Description

[2]

Type

O USB_TX_DM1 — D transmit data for USB port 1 (OTG

transceiver). O PWM1[3] — Pulse Width Modulator 1, channel 3 output. I/O SSP0_SSEL — Slave Select for SSP0. I MC_ABORT

— Motor control PWM, active low fast abort.

- R — Function reserved. O LCD_VD[7] — LCD data. O LCD_VD[11] — LCD data.

[3]

P1[22] 74 U8 M6 51

I; PUI/O P1[22] — General purpose digital input/output pin.

I USB_RCV1 — Differential receive data for USB port 1 (OTG

transceiver). I USB_PWRD1 — Power Status for USB port 1 (host power

switch). O T1_MAT0 — Match output for Timer 1, channel 0. O MC_0B — Motor control PWM channel 0, output B. I/O SSP1_MOSI — Master Out Slave In for SSP1. O LCD_VD[8] — LCD data. O LCD_VD[12] — LCD data.

[3]

P1[23] 76 P9 N7 53

I; PUI/O P1[23] — General purpose digital input/output pin.

I USB_RX_DP1 — D+ receive data for USB port 1 (OTG

transceiver). O PWM1[4] — Pulse Width Modulator 1, channel 4 output. I QEI_PHB — Quadrature Encoder Interface PHB input. I MC_FB1 — Motor control PWM channel 1 feedback input. I/O SSP0_MISO — Master In Slave Out for SSP0. O LCD_VD[9] — LCD data. O LCD_VD[13] — LCD data.

[3]

P1[24] 78 T9 P7 54

I; PUI/O P1[24] — General purpose digital input/output pin.

I USB_RX_DM1 — D receive data for USB port 1 (OTG

transceiver). O PWM1[5] — Pulse Width Modulator 1, channel 5 output. I QEI_IDX — Quadrature Encoder Interface INDEX input. I MC_FB2 — Motor control PWM channel 2 feedback input. I/O SSP0_MOSI — Master Out Slave in for SSP0. O LCD_VD[10] — LCD data. O LCD_VD[14] — LCD data.

Product data sheet Rev. 5 — 9 September 2014 19 of 122

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 3. Pin description

…continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

P1[25] 80 T10 L7 56

[1]

Pin LQFP144

Reset state

[3]

I; PUI/O P1[25] — General purpose digital input/output pin.

Description

[2]

Type

O USB_LS1

— Low Speed status for USB port 1 (OTG

transceiver). O USB_HSTEN1

— Host Enabled status for USB port 1. O T1_MAT1 — Match output for Timer 1, channel 1. O MC_1A — Motor control PWM channel 1, output A. O CLKOUT — Selectable clock output. O LCD_VD[11] — LCD data. O LCD_VD[15] — LCD data.

[3]

P1[26] 82 R10 P8 57

I; PUI/O P1[26] — General purpose digital input/output pin.

O USB_SSPND1

— USB port 1 Bus Suspend status (OTG

transceiver). O PWM1[6] — Pulse Width Modulator 1, channel 6 output. I T0_CAP0 — Capture input for Timer 0, channel 0. O MC_1B — Motor control PWM channel 1, output B. I/O SSP1_SSEL — Slave Select for SSP1. O LCD_VD[12] — LCD data. O LCD_VD[20] — LCD data.

[3]

P1[27] 88 T12 M9 61

I; PUI/O P1[27] — General purpose digital input/output pin.

I USB_INT1

— USB port 1 OTG transceiver interrupt (OTG

transceiver). I USB_OVRCR1

— USB port 1 Over-Current status. I T0_CAP1 — Capture input for Timer 0, channel 1. O CLKOUT — Selectable clock output.

- R — Function reserved. O LCD_VD[13] — LCD data. O LCD_VD[21] — LCD data.

[3]

P1[28] 90 T13 P10 63

I; PUI/O P1[28] — General purpose digital input/output pin.

I/O USB_SCL1 — USB port 1 I

C serial clock (OTG transceiver). I PWM1_CAP0 — Capture input for PWM1, channel 0. O T0_MAT0 — Match output for Timer 0, channel 0. O MC_2A — Motor control PWM channel 2, output A. I/O SSP0_SSEL — Slave Select for SSP0. O LCD_VD[14] — LCD data. O LCD_VD[22] — LCD data.

Product data sheet Rev. 5 — 9 September 2014 20 of 122

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 3. Pin description

…continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

P1[29] 92 U14 N10 64

[1]

Pin LQFP144

Reset state

[3]

I; PUI/O P1[29] — General purpose digital input/output pin.

Description

[2]

Type

I/O USB_SDA1 — USB port 1 I

C serial data (OTG transceiver). I PWM1_CAP1 — Capture input for PWM1, channel 1. O T0_MAT1 — Match output for Timer 0, channel 1. O MC_2B — Motor control PWM channel 2, output B. O U4_TXD — Transmitter output for USART4 (input/output in

smart card mode). O LCD_VD[15] — LCD data. O LCD_VD[23] — LCD data.

[5]

P1[30] 42 P2 K3 30

I; PUI/O P1[30] — General purpose digital input/output pin.

I USB_PWRD2 — Power Status for USB port 2. I USB_VBUS — Monitors the presence of USB bus power.

This signal must be HIGH for USB reset to occur. I ADC0_IN[4] — A/D converter 0, input 4. When configured as an

ADC input, the digital function of the pin must be disabled.

I/O I2C0_SDA — I

C0 data input/output (this pin does not use a

specialized I2C pad). O U3_OE — RS-485/EIA-485 output enable signal for UART3.

[5]

P1[31] 40 P1 K2 28

I; PUI/O P1[31] — General purpose digital input/output pin.

I USB_OVRCR2

— Over-Current status for USB port 2. I/O SSP1_SCK — Serial Clock for SSP1. I ADC0_IN[5] — A/D converter 0, input 5. When configured as an

ADC input, the digital function of the pin must be disabled.

I/O I2C0_SCL — I

C0 clock input/output (this pin does not use a

specialized I2C pad).

P2[0] to P2[31]

I/O Port 2: Port 2 is a 32 bit I/O port with individual direction

controls for each bit. The operation of port 1 pins depends upon the pin function selected via the pin connect block.

[3]

P2[0] 154 B17 D12 107

I; PUI/O P2[0] — General purpose digital input/output pin.

O PWM1[1] — Pulse Width Modulator 1, channel 1 output. O U1_TXD — Transmitter output for UART1.

- R — Function reserved.

- R — Function reserved. O LCD_PWR — LCD panel power enable.

Product data sheet Rev. 5 — 9 September 2014 21 of 122

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 3. Pin description

…continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

P2[1] 152 E14 C14 106

[1]

Pin LQFP144

Reset state

[3]

I; PUI/O P2[1] — General purpose digital input/output pin.

Description

[2]

Type

O PWM1[2] — Pulse Width Modulator 1, channel 2 output. I U1_RXD — Receiver input for UART1.

- R — Function reserved.

- R — Function reserved. O LCD_LE — Line end signal.

[3]

P2[2] 150 D15 E11 105

I; PUI/O P2[2] — General purpose digital input/output pin.

O PWM1[3] — Pulse Width Modulator 1, channel 3 output. I U1_CTS — Clear to Send input for UART1. O T2_MAT3 — Match output for Timer 2, channel 3.

- R — Function reserved. O TRACEDATA[3] — Trace data, bit 3.

- R — Function reserved. O LCD_DCLK — LCD panel clock.

[3]

P2[3] 144 E16 E13 100

I; PUI/O P2[3] — General purpose digital input/output pin.

O PWM1[4] — Pulse Width Modulator 1, channel 4 output. I U1_DCD — Data Carrier Detect input for UART1. O T2_MAT2 — Match output for Timer 2, channel 2.

- R — Function reserved. O TRACEDATA[2] — Trace data, bit 2.

- R — Function reserved. O LCD_FP — Frame pulse (STN). Vertical synchronization pulse

(TFT).

[3]

P2[4] 142 D17 E14 99

I; PUI/O P2[4] — General purpose digital input/output pin.

O PWM1[5] — Pulse Width Modulator 1, channel 5 output. I U1_DSR — Data Set Ready input for UART1. O T2_MAT1 — Match output for Timer 2, channel 1.

- R — Function reserved. O TRACEDATA[1] — Trace data, bit 1.

- R — Function reserved. O LCD_ENAB_M — STN AC bias drive or TFT data enable

output.

Product data sheet Rev. 5 — 9 September 2014 22 of 122

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 3. Pin description

…continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

P2[5] 140 F16 F12 97

[1]

Pin LQFP144

Reset state

[3]

I; PUI/O P2[5] — General purpose digital input/output pin.

Description

[2]

Type

O PWM1[6] — Pulse Width Modulator 1, channel 6 output. O U1_DTR — Data Terminal Ready output for UART1. Can also

be configured to be an RS-485/EIA-485 output enable signal for UART1.

O T2_MAT0 — Match output for Timer 2, channel 0.

- R — Function reserved. O TRACEDATA[0] — Trace data, bit 0.

- R — Function reserved. O LCD_LP — Line synchronization pulse (STN). Horizontal

synchronization pulse (TFT).

[3]

P2[6] 138 E17 F13 96

I; PUI/O P2[6] — General purpose digital input/output pin.

I PWM1_CAP0 — Capture input for PWM1, channel 0. I U1_RI — Ring Indicator input for UART1. I T2_CAP0 — Capture input for Timer 2, channel 0. O U2_OE — RS-485/EIA-485 output enable signal for UART2. O TRACECLK — Trace clock. O LCD_VD[0] — LCD data. O LCD_VD[4] — LCD data.

[3]

P2[7] 136 G16 G11 95

I; PUI/O P2[7] — General purpose digital input/output pin.

I CAN_RD2 — CAN2 receiver input. O U1_RTS — Request to Send output for UART1. Can also be

configured to be an RS-485/EIA-485 output enable signal for UART1.

- R — Function reserved.

- R — Function reserved. O LCD_VD[1] — LCD data. O LCD_VD[5] — LCD data.

[3]

P2[8] 134 H15 G14 93

I; PUI/O P2[8] — General purpose digital input/output pin.

O CAN_TD2 — CAN2 transmitter output. O U2_TXD — Transmitter output for UART2. I U1_CTS — Clear to Send input for UART1. O ENET_MDC — Ethernet MIIM clock.

- R — Function reserved. O LCD_VD[2] — LCD data. O LCD_VD[6] — LCD data.

Product data sheet Rev. 5 — 9 September 2014 23 of 122

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 3. Pin description

…continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

P2[9] 132 H16 H11 92

[1]

Pin LQFP144

Reset state

[3]

I; PUI/O P2[9] — General purpose digital input/output pin.

Description

[2]

Type

O USB_CONNECT1 — USB1 SoftConnect control. Signal used to

switch an external 1.5 k resistor under the software control.

Used with the SoftConnect USB feature. I U2_RXD — Receiver input for UART2. I U4_RXD — Receiver input for USART4. I/O ENET_MDIO — Ethernet MIIM data input and output.

- R — Function reserved. I LCD_VD[3] — LCD data. I LCD_VD[7] — LCD data.

[10]

P2[10] 110 N15 M13 76

I; PUI/O P2[10] — General purpose digital input/output pin. This pin

includes a 10 ns input .

A LOW on this pin while RESET is LOW forces the on-chip boot

loader to take over control of the part after a reset and go into

ISP mode. I EINT0

— External interrupt 0 input.

I NMI — Non-maskable interrupt input.

[10]

P2[11] 108 T17 M12 75

I; PUI/O P2[11] — General purpose digital input/output pin. This pin

includes a 10 ns input glitch filter. I EINT1

— External interrupt 1 input. I/O SD_DAT[1] — Data line 1 for SD card interface. I/O I2S_TX_SCK — Transmit Clock. It is driven by the master and

received by the slave. Corresponds to the signal SCK in the

S-bus specification.

- R — Function reserved.

- R — Function reserved. O LCD_CLKIN — LCD clock.

[10]

P2[12] 106 N14 N14 73

I; PUI/O P2[12] — General purpose digital input/output pin. This pin

includes a 10 ns input glitch filter.

I EINT2

— External interrupt 2 input. I/O SD_DAT[2] — Data line 2 for SD card interface. I/O I2S_TX_WS — Transmit Word Select. It is driven by the master

and received by the slave. Corresponds to the signal WS in the

S-bus specification.

O LCD_VD[4] — LCD data. O LCD_VD[3] — LCD data. O LCD_VD[8] — LCD data. O LCD_VD[18] — LCD data.

Product data sheet Rev. 5 — 9 September 2014 24 of 122

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 3. Pin description

…continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

P2[13] 102 T16 M11 71

[1]

Pin LQFP144

Reset state

[10]

I; PUI/O P2[13] — General purpose digital input/output pin. This pin

Description

[2]

Type

includes a 10 ns input glitch filter.

I EINT3

— External interrupt 3 input. I/O SD_DAT[3] — Data line 3 for SD card interface. I/O I2S_TX_SDA — Transmit data. It is driven by the transmitter

and read by the receiver. Corresponds to the signal SD in the

S-bus specification.

- R — Function reserved. O LCD_VD[5] — LCD data. O LCD_VD[9] — LCD data. O LCD_VD[19] — LCD data.

[3]

P2[14] 91 R12 - -

I; PUI/O P2[14] — General purpose digital input/output pin.

O EMC_CS2 I/O I2C1_SDA — I

— LOW active Chip Select 2 signal.

C1 data input/output (this pin does not use a

specialized I2C pad).

I T2_CAP0 — Capture input for Timer 2, channel 0.

[3]

P2[15] 99 P13 - -

I; PUI/O P2[15] — General purpose digital input/output pin.

O EMC_CS3 I/O I2C1_SCL — I

— LOW active Chip Select 3 signal.

C1 clock input/output (this pin does not use a

specialized I2C pad).

I T2_CAP1 — Capture input for Timer 2, channel 1.

[3]

P2[16] 87 R11 P9 -

P2[17] 95 R13 P11 -

P2[18] 59 U3 P3 -

I; PUI/O P2[16] — General purpose digital input/output pin.

O EMC_CAS

[3]

I; PUI/O P2[17] — General purpose digital input/output pin.

O EMC_RAS

[6]

I; PUI/O P2[18] — General purpose digital input/output pin.

— LOW active SDRAM Column Address Strobe.

— LOW active SDRAM Row Address Strobe.

O EMC_CLK[0] — SDRAM clock 0.

[6]

P2[19] 67 R7 N5 -

I; PUI/O P2[19] — General purpose digital input/output pin.

O EMC_CLK[1] — SDRAM clock 1.

[3]

P2[20] 73 T8 P6 -

P2[21] 81 U11 N8 -

P2[22] 85 U12 - -

I; PUI/O P2[20] — General purpose digital input/output pin.

O EMC_DYCS0

[3]

I; PUI/O P2[21] — General purpose digital input/output pin.

O EMC_DYCS1

[3]

I; PUI/O P2[22] — General purpose digital input/output pin.

O EMC_DYCS2

— SDRAM chip select 0.

— SDRAM chip select 1.

— SDRAM chip select 2.

I/O SSP0_SCK — Serial clock for SSP0. I T3_CAP0 — Capture input for Timer 3, channel 0.

Product data sheet Rev. 5 — 9 September 2014 25 of 122

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 3. Pin description

…continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

P2[23] 64 U5 - -

[1]

Pin LQFP144

Reset state

[3]

I; PUI/O P2[23] — General purpose digital input/output pin.

Description

[2]

Type

O EMC_DYCS3

— SDRAM chip select 3.

I/O SSP0_SSEL — Slave Select for SSP0. I T3_CAP1 — Capture input for Timer 3, channel 1.

[3]

P2[24] 53 P5 P1 -

I; PUI/O P2[24] — General purpose digital input/output pin.

O EMC_CKE0 — SDRAM clock enable 0.

[3]

P2[25] 54 R4 P2 -

I; PUI/O P2[25] — General purpose digital input/output pin.

O EMC_CKE1 — SDRAM clock enable 1.

[3]

P2[26] 57 T4 - -

I; PUI/O P2[26] — General purpose digital input/output pin.

O EMC_CKE2 — SDRAM clock enable 2. I/O SSP0_MISO — Master In Slave Out for SSP0. O T3_MAT0 — Match output for Timer 3, channel 0.

[3]

P2[27] 47 P3 - -

I; PUI/O P2[27] — General purpose digital input/output pin.

O EMC_CKE3 — SDRAM clock enable 3. I/O SSP0_MOSI — Master Out Slave In for SSP0. O T3_MAT1 — Match output for Timer 3, channel 1.

[3]

P2[28] 49 P4 M2 -

I; PUI/O P2[28] — General purpose digital input/output pin.

O EMC_DQM0 — Data mask 0 used with SDRAM and static

devices.

[3]

P2[29] 43 N3 L1 -

I; PUI/O P2[29] — General purpose digital input/output pin.

O EMC_DQM1 — Data mask 1 used with SDRAM and static

devices.

[3]

P2[30] 31 L4 - -

I; PUI/O P2[30] — General purpose digital input/output pin.

O EMC_DQM2 — Data mask 2 used with SDRAM and static

devices.

I/O I2C2_SDA — I

C2 data input/output (this pin does not use a

specialized I2C pad).

O T3_MAT2 — Match output for Timer 3, channel 2.

[3]

P2[31] 39 N2 - -

I; PUI/O P2[31] — General purpose digital input/output pin.

O EMC_DQM3 — Data mask 3 used with SDRAM and static

devices.

I/O I2C2_SCL — I

C2 clock input/output (this pin does not use a

specialized I2C pad).

O T3_MAT3 — Match output for Timer 3, channel 3.

P3[0] to P3[31]

I/O Port 3: Port 3 is a 32-bit I/O port with individual direction

controls for each bit. The operation of port 3 pins depends upon the pin function selected via the pin connect block.

Product data sheet Rev. 5 — 9 September 2014 26 of 122

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 3. Pin description

…continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

P3[0] 197 B4 D6 137

[1]

Pin LQFP144

Reset state

[3]

I; PUI/O P3[0] — General purpose digital input/output pin.

Description

[2]

Type

I/O EMC_D[0] — External memory data line 0.

[3]

P3[1] 201 B3 E6 140

I; PUI/O P3[1] — General purpose digital input/output pin.

I/O EMC_D[1] — External memory data line 1.

[3]

P3[2] 207 B1 A2 144

I; PUI/O P3[2] — General purpose digital input/output pin.

I/O EMC_D[2] — External memory data line 2.

[3]

P3[3] 3 E4 G5 2

I; PUI/O P3[3] — General purpose digital input/output pin.

I/O EMC_D[3] — External memory data line 3.

[3]

P3[4] 13 F2 D3 9

I; PUI/O P3[4] — General purpose digital input/output pin.

I/O EMC_D[4] — External memory data line 4.

[3]

P3[5] 17 G1 E3 12

I; PUI/O P3[5] — General purpose digital input/output pin.

I/O EMC_D[5] — External memory data line 5.

[3]

P3[6] 23 J1 F4 16

I; PUI/O P3[6] — General purpose digital input/output pin.

I/O EMC_D[6] — External memory data line 6.

P3[7] 27 L1 G3 19

[3]

I; PUI/O P3[7] — General purpose digital input/output pin.

I/O EMC_D[7] — External memory data line 7.

[3]

P3[8] 191 D8 A6 -

I; PUI/O P3[8] — General purpose digital input/output pin.

I/O EMC_D[8] — External memory data line 8.

[3]

P3[9] 199 C5 A4 -

I; PUI/O P3[9] — General purpose digital input/output pin.

I/O EMC_D[9] — External memory data line 9.

[3]

P3[10] 205 B2 B3 -

I; PUI/O P3[10] — General purpose digital input/output pin.

I/O EMC_D[10] — External memory data line 10.

[3]

P3[11] 208 D5 B2 -

I; PUI/O P3[11] — General purpose digital input/output pin.

I/O EMC_D[11] — External memory data line 11.

[3]

P3[12] 1 D4 A1 -

I; PUI/O P3[12] — General purpose digital input/output pin.

I/O EMC_D[12] — External memory data line 12.

[3]

P3[13] 7 C1 C1 -

I; PUI/O P3[13] — General purpose digital input/output pin.

I/O EMC_D[13] — External memory data line 13.

[3]

P3[14] 21 H2 F1 -

I; PUI/O P3[14] — General purpose digital input/output pin.

I/O EMC_D[14] — External memory data line 14.

[3]

P3[15] 28 M1 G4 -

I; PUI/O P3[15] — General purpose digital input/output pin.

I/O EMC_D[15] — External memory data line 15.

[3]

P3[16] 137 F17 - -

I; PUI/O P3[16] — General purpose digital input/output pin.

I/O EMC_D[16] — External memory data line 16. O PWM0[1] — Pulse Width Modulator 0, output 1. O U1_TXD — Transmitter output for UART1.

Product data sheet Rev. 5 — 9 September 2014 27 of 122

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 3. Pin description

…continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

P3[17] 143 F15 - -

[1]

Pin LQFP144

Reset state

[3]

I; PUI/O P3[17] — General purpose digital input/output pin.

Description

[2]

Type

I/O EMC_D[17] — External memory data line 17. O PWM0[2] — Pulse Width Modulator 0, output 2. I U1_RXD — Receiver input for UART1.

[3]

P3[18] 151 C15 - -

I; PUI/O P3[18] — General purpose digital input/output pin.

I/O EMC_D[18] — External memory data line 18. O PWM0[3] — Pulse Width Modulator 0, output 3. I U1_CTS — Clear to Send input for UART1.

[3]

P3[19] 161 B14 - -

I; PUI/O P3[19] — General purpose digital input/output pin.

I/O EMC_D[19] — External memory data line 19. O PWM0[4] — Pulse Width Modulator 0, output 4. I U1_DCD — Data Carrier Detect input for UART1.

[3]

P3[20] 167 A13 - -

I; PUI/O P3[20] — General purpose digital input/output pin.

I/O EMC_D[20] — External memory data line 20. O PWM0[5] — Pulse Width Modulator 0, output 5. I U1_DSR — Data Set Ready input for UART1.

[3]

P3[21] 175 C10 - -

I; PUI/O P3[21] — General purpose digital input/output pin.

I/O EMC_D[21] — External memory data line 21. O PWM0[6] — Pulse Width Modulator 0, output 6. O U1_DTR — Data Terminal Ready output for UART1. Can also

be configured to be an RS-485/EIA-485 output enable signal for UART1.

[3]

P3[22] 195 C6 - -

I; PUI/O P3[22] — General purpose digital input/output pin.

I/O EMC_D[22] — External memory data line 22. I PWM0_CAP0 — Capture input for PWM0, channel 0. I U1_RI — Ring Indicator input for UART1.

[3]

P3[23] 65 T6 M4 45

I; PUI/O P3[23] — General purpose digital input/output pin.

I/O EMC_D[23] — External memory data line 23. I PWM1_CAP0 — Capture input for PWM1, channel 0. I T0_CAP0 — Capture input for Timer 0, channel 0.

[3]

P3[24] 58 R5 N3 40

I; PUI/O P3[24] — General purpose digital input/output pin.

I/O EMC_D[24] — External memory data line 24. O PWM1[1] — Pulse Width Modulator 1, output 1. I T0_CAP1 — Capture input for Timer 0, channel 1.

Product data sheet Rev. 5 — 9 September 2014 28 of 122

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 3. Pin description

…continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

P3[25] 56 U2 M3 39

[1]

Pin LQFP144

Reset state

[3]

I; PUI/O P3[25] — General purpose digital input/output pin.

Description

[2]

Type

I/O EMC_D[25] — External memory data line 25. O PWM1[2] — Pulse Width Modulator 1, output 2. O T0_MAT0 — Match output for Timer 0, channel 0.

[3]

P3[26] 55 T3 K7 38

I; PUI/O P3[26] — General purpose digital input/output pin.

I/O EMC_D[26] — External memory data line 26. O PWM1[3] — Pulse Width Modulator 1, output 3. O T0_MAT1 — Match output for Timer 0, channel 1. I STCLK — System tick timer clock input. The maximum STCLK

frequency is 1/4 of the ARM processor clock frequency CCLK.

[3]

P3[27] 203 A1 - -

I; PUI/O P3[27] — General purpose digital input/output pin.

I/O EMC_D[27] — External memory data line 27. O PWM1[4] — Pulse Width Modulator 1, output 4. I T1_CAP0 — Capture input for Timer 1, channel 0.

[3]

P3[28] 5 D2 - -

I; PUI/O P3[28] — General purpose digital input/output pin.

I/O EMC_D[28] — External memory data line 28. O PWM1[5] — Pulse Width Modulator 1, output 5. I T1_CAP1 — Capture input for Timer 1, channel 1.

[3]

P3[29] 11 F3 - -

I; PUI/O P3[29] — General purpose digital input/output pin.

I/O EMC_D[29] — External memory data line 29. O PWM1[6] — Pulse Width Modulator 1, output 6. O T1_MAT0 — Match output for Timer 1, channel 0.

[3]

P3[30] 19 H3 - -

I; PUI/O P3[30] — General purpose digital input/output pin.

I/O EMC_D[30] — External memory data line 30. O U1_RTS — Request to Send output for UART1. Can also be

configured to be an RS-485/EIA-485 output enable signal for UART1.

O T1_MAT1 — Match output for Timer 1, channel 1.

[3]

P3[31] 25 J3 - -

I; PUI/O P3[31] — General purpose digital input/output pin.

I/O EMC_D[31] — External memory data line 31.

- R — Function reserved. O T1_MAT2 — Match output for Timer 1, channel 2.

P4[0] to P4[31]

I/O Port 4: Port 4 is a 32-bit I/O port with individual direction

controls for each bit. The operation of port 4 pins depends upon the pin function selected via the pin connect block.

[3]

P4[0] 75 U9 L6 52

I; PUI/O P4[0] — General purpose digital input/output pin.

I/O EMC_A[0] — External memory address line 0.

Product data sheet Rev. 5 — 9 September 2014 29 of 122

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 3. Pin description

…continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

P4[1] 79 U10 M7 55

[1]

Pin LQFP144

Reset state

[3]

I; PUI/O P4[1] — General purpose digital input/output pin.

Description

[2]

Type

I/O EMC_A[1] — External memory address line 1.

[3]

P4[2] 83 T11 M8 58

I; PUI/O P4[2] — General purpose digital input/output pin.

I/O EMC_A[2] — External memory address line 2.

[3]

P4[3] 97 U16 K9 68

I; PUI/O P4[3] — General purpose digital input/output pin.

I/O EMC_A[3] — External memory address line 3.

[3]

P4[4] 103 R15 P13 72

I; PUI/O P4[4] — General purpose digital input/output pin.

I/O EMC_A[4] — External memory address line 4.

[3]

P4[5] 107 R16 H10 74

I; PUI/O P4[5] — General purpose digital input/output pin.

I/O EMC_A[5] — External memory address line 5.

[3]

P4[6] 113 M14 K10 78

I; PUI/O P4[6] — General purpose digital input/output pin.

I/O EMC_A[6] — External memory address line 6.

[3]

P4[7] 121 L16 K12 84

I; PUI/O P4[7] — General purpose digital input/output pin.

I/O EMC_A[7] — External memory address line 7.

P4[8] 127 J17 J11 88

[3]

I; PUI/O P4[8] — General purpose digital input/output pin.

I/O EMC_A[8] — External memory address line 8.

[3]

P4[9] 131 H17 H12 91

I; PUI/O P4[9] — General purpose digital input/output pin.

I/O EMC_A[9] — External memory address line 9.

[3]

P4[10] 135 G17 G12 94

I; PUI/O P4[10] — General purpose digital input/output pin.

I/O EMC_A[10] — External memory address line 10.

[3]

P4[11] 145 F14 F11 101

I; PUI/O P4[11] — General purpose digital input/output pin.

I/O EMC_A[11] — External memory address line 11.

[3]

P4[12] 149 C16 F10 104

I; PUI/O P4[12] — General purpose digital input/output pin.

I/O EMC_A[12] — External memory address line 12.

[3]

P4[13] 155 B16 B14 108

I; PUI/O P4[13] — General purpose digital input/output pin.

I/O EMC_A[13] — External memory address line 13.

[3]

P4[14] 159 B15 E8 110

I; PUI/O P4[14] — General purpose digital input/output pin.

I/O EMC_A[14] — External memory address line 14.

[3]

P4[15] 173 A11 C10 120

I; PUI/O P4[15] — General purpose digital input/output pin.

I/O EMC_A[15] — External memory address line 15.

[3]

P4[16] 101 U17 N12 -

I; PUI/O P4[16] — General purpose digital input/output pin.

I/O EMC_A[16] — External memory address line 16.

[3]

P4[17] 104 P14 N13 -

I; PUI/O P4[17] — General purpose digital input/output pin.

I/O EMC_A[17] — External memory address line 17.

[3]

P4[18] 105 P15 P14 -

I; PUI/O P4[18] — General purpose digital input/output pin.

I/O EMC_A[18] — External memory address line 18.

Product data sheet Rev. 5 — 9 September 2014 30 of 122

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 3. Pin description

…continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

P4[19] 111 P16 M14 -

[1]

Pin LQFP144

Reset state

[3]

I; PUI/O P4[19] — General purpose digital input/output pin.

Description

[2]

Type

I/O EMC_A[19] — External memory address line 19.

[3]

P4[20] 109 R17 - -

I; PUI/O P4[20] — General purpose digital input/output pin.

I/O EMC_A[20] — External memory address line 20.

I/O I2C2_SDA — I

C2 data input/output (this pin does not use a

specialized I2C pad).

I/O SSP1_SCK — Serial Clock for SSP1.

[3]

P4[21] 115 M15 - -

I; PUI/O P4[21] — General purpose digital input/output pin.

I/O EMC_A[21] — External memory address line 21.

I/O I2C2_SCL — I

C2 clock input/output (this pin does not use a

specialized I2C pad).

I/O SSP1_SSEL — Slave Select for SSP1.

[3]

P4[22] 123 K14 - -

I; PUI/O P4[22] — General purpose digital input/output pin.

I/O EMC_A[22] — External memory address line 22. O U2_TXD — Transmitter output for UART2. I/O SSP1_MISO — Master In Slave Out for SSP1.

[3]

P4[23] 129 J15 - -

I; PUI/O P4[23] — General purpose digital input/output pin.

I/O EMC_A[23] — External memory address line 23. I U2_RXD — Receiver input for UART2. I/O SSP1_MOSI — Master Out Slave In for SSP1.

[3]

P4[24] 183 B8 C8 127

P4[25] 179 B9 D9 124

P4[26] 119 L15 K13 -

P4[27] 139 G15 F14 -

P4[28] 170 C11 D10 118

I; PUI/O P4[24] — General purpose digital input/output pin.

O EMC_OE

[3]

I; PUI/O P4[25] — General purpose digital input/output pin.

O EMC_WE

[3]

I; PUI/O P4[26] — General purpose digital input/output pin.

O EMC_BLS0

[3]

I; PUI/O P4[27] — General purpose digital input/output pin.

O EMC_BLS1

[3]

I; PUI/O P4[28] — General purpose digital input/output pin.

O EMC_BLS2

— LOW active Output Enable signal.

— LOW active Write Enable signal.

— LOW active Byte Lane select signal 0.

— LOW active Byte Lane select signal 1.

— LOW active Byte Lane select signal 2.

O U3_TXD — Transmitter output for UART3. O T2_MAT0 — Match output for Timer 2, channel 0.

- R — Function reserved. O LCD_VD[6] — LCD data. O LCD_VD[10] — LCD data. O LCD_VD[2] — LCD data.

Product data sheet Rev. 5 — 9 September 2014 31 of 122

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 3. Pin description

…continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

P4[29] 176 B10 B9 122

[1]

Pin LQFP144

Reset state

[3]

I; PUI/O P4[29] — General purpose digital input/output pin.

Description

[2]

Type

O EMC_BLS3

— LOW active Byte Lane select signal 3.

I U3_RXD — Receiver input for UART3. O T2_MAT1 — Match output for Timer 2, channel 1.

I/O I2C2_SCL — I

C2 clock input/output (this pin does not use a

specialized I2C pad). O LCD_VD[7] — LCD data. O LCD_VD[11] — LCD data. O LCD_VD[3] — LCD data.

[3]

P4[30] 187 B7 C7 130

P4[31] 193 A4 E7 134

I; PUI/O P4[30] — General purpose digital input/output pin.

O EMC_CS0

[3]

I; PUI/O P4[31] — General purpose digital input/output pin.

O EMC_CS1

— LOW active Chip Select 0 signal.

— LOW active Chip Select 1 signal.

P5[0] to P5[4] I/O Port 5: Port 5 is a 5-bit I/O port with individual direction controls

for each bit. The operation of port 5 pins depends upon the pin

function selected via the pin connect block.

[3]

P5[0] 9 F4 E5 6

I; PUI/O P5[0] — General purpose digital input/output pin.

I/O EMC_A[24] — External memory address line 24. I/O SSP2_MOSI — Master Out Slave In for SSP2. O T2_MAT2 — Match output for Timer 2, channel 2.

[3]

P5[1] 30 J4 H1 21

I; PUI/O P5[1] — General purpose digital input/output pin.

I/O EMC_A[25] — External memory address line 25. I/O SSP2_MISO — Master In Slave Out for SSP2. O T2_MAT3 — Match output for Timer 2, channel 3.

[11]

P5[2] 117 L14 L12 81

I I/O P5[2] — General purpose digital input/output pin.

- R — Function reserved.

- R — Function reserved. O T3_MAT2 — Match output for Timer 3, channel 2.

- R — Function reserved.

I/O I2C0_SDA — I

C0 data input/output (this pin uses a specialized

I2C pad that supports I2C Fast Mode Plus).

Product data sheet Rev. 5 — 9 September 2014 32 of 122

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 3. Pin description

…continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

P5[3] 141 G14 G10 98

[1]

Pin LQFP144

Reset state

[11]

I I/O P5[3] — General purpose digital input/output pin.

Description

[2]

Type

- R — Function reserved.

- R — Function reserved. I U4_RXD — Receiver input for USART4.

C0 clock input/output (this pin uses a

C pad that supports I2C Fast Mode Plus).

P5[4] 206 C3 C4 143

I/O I2C0_SCL — I

specialized I

[3]

I; PUI/O P5[4] — General purpose digital input/output pin.

O U0_OE — RS-485/EIA-485 output enable signal for UART0.

- R — Function reserved. O T3_MAT3 — Match output for Timer 3, channel 3. O U4_TXD — Transmitter output for USART4 (input/output in

smart card mode).

[3]

JTAG_TDO

2D3B11

(SWO) JTAG_TDI 4 C2 C3 3

O O Test Data Out for JTAG interface. Also used as Serial wire trace

output.

[3]

I; PUI Test Data In for JTAG interface.

JTAG_TMS

6E3C24

[3]

(SWDIO) JTAG_TRST

JTAG_TCK

8D1D45

10 E2 D2 7

[3]

(SWDCLK)

RESET

RSTOUT

35 M2 J1 24

29 K3 H2 20

RTC_ALARM 37 N1 H5 26

RTCX1 34 K2 J2 23

RTCX2 36 L2 J3 25

USB_D252U1N237

[12]

[3]

[13]

[14] [15]

[9]

I; PUI Test Mode Select for JTAG interface. Also used as Serial wire

debug data input/output.

I; PUI Test Reset for JTAG interface.

i I Test Clock for JTAG interface. This clock must be slower than

1/6 of the CPU clock (CCLK) for the JTAG interface to operate.

Also used as serial wire clock.

I; PUI External reset input with 20 ns glitch filter. A LOW-going pulse

as short as 50 ns on this pin resets the device, causing I/O ports

and peripherals to take on their default states, and processor

execution to begin at address 0. This pin also serves as the

debug select input. LOW level selects the JTAG boundary scan.

HIGH level selects the ARM SWD debug mode.

OH O Reset status output. A LOW output on this pin indicates that the

device is in the reset state for any reason. This reflects the

RESET

input pin and all internal reset sources.

OL O RTC controlled output. This pin has a low drive strength and is

generated.

- I Input to the RTC 32 kHz ultra-low power oscillator circuit.

- O Output from the RTC 32 kHz ultra-low power oscillator circuit.

- I/O USB port 2 bidirectional D line.

Product data sheet Rev. 5 — 9 September 2014 33 of 122

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 3. Pin description …continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).

Symbol

[1]

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

Pin LQFP144

Reset state

VBAT 38 M3 K1 27 - I RTC power supply: 3.0 V on this pin supplies power to the RTC. V

DD(REG)(3V3)

DDA

DD(3V3)

18,

86,

P11,

N9,

60,

174

D11

121

20 G4 F2 14 - S Analog 3.3 V pad supply voltage: This can be connected to the

15,

G3,

E2,

41,

60,

P6,

L4,

62,

71,

P8,

K8,

77,

89,

U13,

L11,

102,

112,

P17,

J14,

114,

125,

K16,

E12,

138

146,

C17,

E10,

165,

B13,

181,

C9,

198

- S 3.3 V regulator supply voltage: This is the power supply for the

- S 3.3 V supply voltage: This is the power supply voltage for I/O

26,

H4,

G1,

VREFP 24 K1 G2 17 - S ADC positive reference voltage: This should be the same

SSREG

SSA

XTAL1 44 M4 L2 31

XTAL2 46 N4 K4 33

33,

L3,

H4, 63, 77, 93, 114, 133, 148, 169, 189, 200

32, 84, 172

T5, R9, P12, N16, H14, E15, A12, B6, A2

D12, K4, P10

P4,

L9,

L13,

G13,

D13,

C1 1,

H3,

L8,

A10

44, 65, 79, 103, 117, 139

22, 59, 119

- G Ground: 0 V reference for digital IO pins.

- G Ground: 0 V reference for internal logic.

22 J2 F3 15 - G Analog ground: 0 V power supply and reference for the ADC

[14]

- I Input to the oscillator circuit and internal clock generator circuits.

[16] [14]

- O Output from the oscillator amplifier.

[16]

Description

[2]

Type

on-chip voltage regulator that supplies internal logic.

same supply as V

but should be isolated to minimize

DD(3V3)

noise and error. This voltage is used to power the ADC and DAC. Note: This pin should be tied to 3.3 V if the ADC and

DAC are not used.

other than pins in the VBAT domain.

voltage as V

, but should be isolated to minimize noise and

DDA

error. The voltage level on this pin is used as a reference for ADC and DAC. Note: This pin should be tied to 3.3 V if the

ADC and DAC are not used.

and DAC. This should be the same voltage as VSS, but should be isolated to minimize noise and error.

Product data sheet Rev. 5 — 9 September 2014 34 of 122

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

[1] PU = internal pull-up enabled (for V

DD(REG)(3V3)

= 3.3 V, pulled up to 3.3 V); IA = inactive, no pull-up/down enabled; F = floating; floating

pins, if not used, should be tied to ground or power to minimize power consumption. [2] I = Input; O = Output; OL = Output driving LOW; G = Ground; S = Supply. [3] 5 V tolerant pad (5 V tolerant if V

DD(3V3)

present; if V

not present, do not exceed 3.6 V) providing digital I/O functions with TTL

DD(3V3)

levels and hysteresis. [4] 5 V tolerant standard pad (5 V tolerant if V

DD(3V3)

present; if V

not present, do not exceed 3.6 V) providing digital I/O functions with

DD(3V3)

TTL levels and hysteresis. This pad can be powered by VBAT. [5] 5 V tolerant pad (5 V tolerant if V

DD(3V3)

present; if V

not present or configured for an analog function, do not exceed 3.6 V)

DD(3V3)

providing digital I/O functions with TTL levels and hysteresis and analog input. When configured as a ADC input, digital section of the

pad is disabled. [6] 5 V tolerant fast pad (5 V tolerant if V

DD(3V3)

present; if V

not present, do not exceed 3.6 V) providing digital I/O functions with TTL

DD(3V3)

levels and hysteresis. [7] 5 V tolerant pad (5 V tolerant if V

DD(3V3)

present; if V

not present or configured for an analog function, do not exceed 3.6 V)

DD(3V3)

providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output, digital section of the

pad is disabled.

[8] Open-drain 5 V tolerant digital I/O pad, compatible with I

functionality. When power is switched off, this pin connected to the I

C-bus 400 kHz specification. It requires an external pull-up to provide output

C-bus is floating and does not disturb the I2C lines. Open-drain

configuration applies to all functions on this pin. [9] Not 5 V tolerant. Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0

(Full-speed and Low-speed mode only). [10] 5 V tolerant pad (5 V tolerant if V

DD(3V3)

present; if V

not present, do not exceed 3.6 V) with 5 ns glitch filter providing digital I/O

DD(3V3)

functions with TTL levels and hysteresis. [11] Open-drain 5 V tolerant digital I/O pad, compatible with I

functionality. When power is switched off, this pin connected to the I

C-bus 1 MHz specification. It requires an external pull-up to provide output

C-bus is floating and does not disturb the I2C lines. Open-drain

configuration applies to all functions on this pin. [12] 5 V tolerant pad (5 V tolerant if V

DD(3V3)

present; if V

not present, do not exceed 3.6 V) with 20 ns glitch filter providing digital I/O

DD(3V3)

function with TTL levels and hysteresis. [13] This pad can be powered from VBAT. [14] Pad provides special analog functionality. A 32 kHz crystal oscillator must be used with the RTC. An external clock (32 kHz) can’t be

used to drive the RTCX1 pin. [15] If the RTC is not used, these pins can be left floating. [16] When the main oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding

is preferred to reduce susceptibility to noise). XTAL2 should be left floating.

Table 4. Pin allocation table TFBGA208

Not all functions are available on all parts. See Table 2 and Table 7 (EMC pins).

Ball Symbol Ball Symbol Ball Symbol Ball Symbol

Row A

1 P3[27] 2 V

3 P1[0] 4 P4[31] 5 P1[4] 6 P1[9] 7 P1[14] 8 P1[15] 9 P1[17] 10 P1[3] 11 P4[15] 12 V

13 P3[20] 14 P1[11] 15 P0[8] 16 P1[12] 17 P1[5] - - -

Row B

1 P3[2] 2 P3[10] 3 P3[1] 4 P3[0] 5 P1[1] 6 V

7 P4[30] 8 P4[24] 9 P4[25] 10 P4[29] 11 P1[6] 12 P0[4] 13 V

DD(3V3)

14 P3[19] 15 P4[14] 16 P4[13]

17 P2[0] - - -

Row C

Product data sheet Rev. 5 — 9 September 2014 35 of 122

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 4. Pin allocation table TFBGA208

Not all functions are available on all parts. See Table 2

Ball Symbol Ball Symbol Ball Symbol Ball Symbol

1 P3[13] 2 JTAG_TDI 3 P5[4] 4 P0[2] 5 P3[9] 6 P3[22] 7 P1[8] 8 P1[10] 9V

DD(3V3)

10 P3[21] 11 P4[28] 12 P0[5] 13 P0[7] 14 P0[9] 15 P3[18] 16 P4[12] 17 V

)- - -

DD(3V3

Row D

1 JTAG_TRST 2 P3[28] 3 JTAG_TDO (SWO) 4 P3[12] 5P3[11] 6P0[3] 7V 9 P1[2] 10 P1[16] 11 V 13 P0[6] 14 P1[7] 15 P2[2] 16 P1[13] 17 P2[4] - - -

Row E

1 P0[26] 2 JTAG_TCK

(SWDCLK) 5- 6- 7- 89 - 10 - 11 - 12 13 - 14 P2[1] 15 V 17 P2[6] - - -

Row F

1 P0[25] 2 P3[4] 3 P3[29] 4 P5[0] 5- 6- 7- 89 - 10 - 11 - 12 13 - 14 P4[11] 15 P3[17] 16 P2[5] 17 P3[16] - - -

Row G

1 P3[5] 2 P0[24] 3 V 5- 6- 7- 89 - 10 - 11 - 12 13 - 14 P5[3] 15 P4[27] 16 P2[7] 17 P4[10] - - -

Row H

1 P0[23] 2 P3[14] 3 P3[30] 4 V 5- 6- 7- 89 - 10 - 11 - 12 13 - 14 V

17 P4[9] - - -

Row J

1 P3[6] 2 V

SSA

5- 6- 7- 89 - 10 - 11 - 12 -

and Table 7 (EMC pins).

DD(3V3) DD(REG)(3V3)

3 JTAG_TMS (SWDIO) 4 P3[3]

DD(3V3)

15 P2[8] 16 P2[9]

3 P3[31] 4 P5[1]

8 P3[8] 12 VSSREG

16 P2[3]

DDA

DD(REG)(3V3)

Product data sheet Rev. 5 — 9 September 2014 36 of 122

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 4. Pin allocation table TFBGA208

Not all functions are available on all parts. See Table 2

Ball Symbol Ball Symbol Ball Symbol Ball Symbol

13 14 P0[16] 15 P4[23] 16 P0[15] 17 P4[8] - - -

Row K

1 VREFP 2 RTCX1 3 RSTOUT 4 VSSREG 13 - 14 P4[22] 15 P0[18] 16 V 17 P0[17] - - -

Row L

1 P3[7] 2 RTCX2 3 V 5- 6- 7- 89 - 10 - 11 - 12 13 - 14 P5[2] 15 P4[26] 16 P4[7] 17 P0[19] - - -

Row M

1 P3[15] 2 RESET 5- 6- 7- 89 - 10 - 11 - 12 13 - 14 P4[6] 15 P4[21] 16 P0[21] 17 P0[20] - - -

Row N

1 RTC_ALARM 2 P2[31] 3 P2[29] 4 XTAL2 5- 6- 7- 89 - 10 - 11 - 12 13 - 14 P2[12 15 P2[10] 16 V 17 P0[22] - - -

Row P

1 P1[31] 2 P1[30] 3 P2[27] 4 P2[28] 5 P2[24] 6 V

DD(3V3)

9 P1[23] 10 VSSREG 11 V 13 P2[15] 14 P4[17] 15 P4[18] 16 P4[19] 17 V

DD(3V3)

---

Row R

1 P0[12] 2 P0[13] 3 P0[28] 4 P2[25] 5 P3[24] 6 P0[30] 7 P2[19] 8 P1[21] 9V

10 P1[26] 11 P2[16] 12 P2[14] 13 P2[17] 14 P0[11] 15 P4[4] 16 P4[5] 17 P4[20] - - -

Row T

1 P0[27] 2 P0[31] 3 P3[26] 4 P2[26] 5V

6 P3[23] 7 P0[14] 8 P2[20] 9 P1[24] 10 P1[25] 11 P4[2] 12 P1[27]

and Table 7 (EMC pins).

3 VBAT 4 XTAL1

7 P1[18] 8 V

DD(REG)(3V3)

DD(3V3)

4 P2[30]

DD(3V3)

12 V

Product data sheet Rev. 5 — 9 September 2014 37 of 122

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 4. Pin allocation table TFBGA208

Not all functions are available on all parts. See Table 2

Ball Symbol Ball Symbol Ball Symbol Ball Symbol

13 P1[28] 14 P0[1] 15 P0[10] 16 P2[13] 17 P2[11] - - -

Row U

1 USB_D-2 2 P3[25] 3 P2[18] 4 P0[29] 5 P2[23] 6 P1[19] 7 P1[20] 8 P1[22] 9 P4[0] 10 P4[1] 11 P2[21] 12 P2[22] 13 V

DD(3V3)

14 P1[29] 15 P0[0] 16 P4[3] 17 P4[16] - - -

and Table 7 (EMC pins).

Table 5. Pin allocation table TFBGA180

Not all functions are available on all parts. See Table 2 and Table 7 (EMC pins).

Ball Symbol Ball Symbol Ball Symbol Ball Symbol

Row A

5 P1[1] 6 P3[8] 7 P1[10] 8 P1[15] 9 P1[3] 10 V

SSREG

11 P0[4] 12 P1[11]

13 P0[9] 14 P1[12] - -

Row B

1 JTAG_TDO (SWO) 2 P3[11] 3 P3[10] 4 V

5 P1[0] 6 P1[8] 7 P1[2] 8 P1[16] 9 P4[29] 10 P1[6] 11 P0[5] 12 P0[7] 13 P1[5] 14 P4[13] - -

Row C

1 P3[13] 2 JTAG_TMS (SWDIO) 3 JTAG_TDI 4 P5[4] 5V

DD(3V3)

9 P1[17] 10 P4[15] 11 V

6 P1[4] 7 P4[30] 8 P4[24]

12 P0[8]

13 P1[7] 14 P2[1] - -

Row D

1 P0[26] 2 JTAG_TCK

3 P3[4] 4 JTAG_TRST

(SWDCLK) 5 P0[2] 6 P3[0] 7 P1[9] 8 P1[14] 9 P4[25] 10 P4[28] 11 P0[6] 12 P2[0] 13 V

14 P1[13] - -

Row E

1 P0[24] 2 V

DD(3V3)

3 P3[5] 4 P0[25] 5 P5[0] 6 P3[1] 7 P4[31] 8 P4[14] 9V

DD(REG)(3V3)

10 V

DD(3V3)

11 P2[2] 12 V

DD(3V3)

13 P2[3] 14 P2[4] - -

Row F

1 P3[14] 2 V

DDA

SSA

4 P3[6] 5 P0[23] 6 - 7 - 8 9 - 10 P4[12] 11 P4[11] 12 P2[5]

Product data sheet Rev. 5 — 9 September 2014 38 of 122

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 5. Pin allocation table TFBGA180

Not all functions are available on all parts. See Table 2

Ball Symbol Ball Symbol Ball Symbol Ball Symbol

13 P2[6] 14 P4[27] - -

Row G

1V 5 P3[3] 6 - 7 - 8 9 - 10 P5[3] 11 P2[7] 12 P4[10] 13 V

Row H

1 P5[1] 2 RSTOUT 5RTC_ALARM 6- 7- 89 - 10 P4[5] 11 P2[9] 12 P4[9] 13 P0[15] 14 P0[16] - -

DD(REG)(3V3)

2 VREFP 3 P3[7] 4 P3[15]

14 P2[8] - -

and Table 7 (EMC pins).

SSREG

Product data sheet Rev. 5 — 9 September 2014 39 of 122

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 5. Pin allocation table TFBGA180

Not all functions are available on all parts. See Table 2

Ball Symbol Ball Symbol Ball Symbol Ball Symbol

Row J

1 RESET 5 P0[13] 6 - 7 - 8 9 - 10 P0[19] 11 P4[8] 12 P0[17] 13 P0[18] 14 V

Row K

1 VBAT 2 P1[31] 3 P1[30] 4 XTAL2 5 P0[29] 6 P1[20] 7 P3[26] 8 V 9 P4[3] 10 P4[6] 11 P0[21] 12 P4[7] 13 P4[26] 14 P0[20] - -

Row L

1 P2[29] 2 XTAL1 3 P0[27] 4 V 5 P1[18] 6 P4[0] 7 P1[25] 8 V 9V 13 V

Row M

1 P0[28] 2 P2[28] 3 P3[25] 4 P3[23] 5 P0[14] 6 P1[22] 7 P4[1] 8 P4[2] 9 P1[27] 10 P0[0] 11 P2[13] 12 P2[11] 13 P2[10] 14 P4[19] - -

Row N

1 P0[31] 2 USB_D-2 3 P3[24] 4 P0[30] 5 P2[19] 6 P1[21] 7 P1[23] 8 P2[21] 9V 13 P4[17] 14 P2[12] - -

Row P

1 P2[24] 2 P2[25] 3 P2[18] 4 V 5 P1[19] 6 P2[20] 7 P1[24] 8 P1[26] 9 P2[16] 10 P1[28] 11 P2[17] 12 P0[11] 13 P4[4] 14 P4[18] - -

SS SS

DD(REG)(3V3)

2 RTCX1 3 RTCX2 4 P0[12]

DD(3V3)

10 P0[10] 11 V 14 P0[22] - -

10 P1[29] 11 P0[1] 12 P4[16]

and Table 7 (EMC pins).

DD(3V3)

DD(3V3) SSREG

12 P5[2]

7. Functional description

7.1 Architectural overview

The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and the D-code bus. The I-code and D-code core buses are faster than the system bus and are used similarly to Tightly Coupled Memory (TCM) interfaces: one bus dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of two core buses allows for simultaneous operations if concur rent operations tar get differ ent devices.

Product data sheet Rev. 5 — 9 September 2014 40 of 122

NXP Semiconductors

The LPC178x/7x use a multi-layer AHB matrix to connect the ARM Cortex-M3 buses and other bus masters to peripherals in a flexible mann e r tha t op timi ze s pe rform a nc e by allowing peripherals that are on different slaves ports of the matrix to be accessed simultaneously by different bus masters.

7.2 ARM Cortex-M3 processor

The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. The ARM Cortex-M3 offers ma ny new features, including a Thumb-2 instruction set, low interrupt latency, hardware division, hardware single-cycle multiply, interruptable/continuable multiple load and store instructions, automatic state save and restore for interrupts, tightly integrated interrupt controller with wake-up interrupt controller, and multiple core buses capable of simultaneous accesses.

Pipeline techniques are employed so that all pa rts of the p rocessing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory.

The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical Reference Manual that can be found on official ARM website.

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

7.3 On-chip flash program memory

The LPC178x/7x contain up to 512 kB of on-chip flash program memory. A new two-port flash accelerator maximizes performance for use with the two fast AHB-Lite buses.

7.4 EEPROM

The LPC178x/7x contains up to 4032 byte of on-chip byte-erasable an d byte-programmable EEPROM data memory.

7.5 On-chip SRAM

The LPC178x/7x contain a total of up to 96 kB on-chip static RAM data memory. This includes the main 64 kB SRAM, accessible by the CPU and DMA controller on a higher-speed bus, and up to two additional 16 kB each SRAM blocks situated on a separate slave port on the AHB multilayer matrix.

This architecture allows CPU and DMA accesses to be spread over three separate RAMs that can be accessed simultaneously.

7.6 Memory Protection Unit (MPU)

The LPC178x/7x have a Memory Protection Unit (MPU) which can be used to improve the reliability of an embedded system by protecting critical data within the user application.

The MPU allows separating processing tasks by disallowing access to each other's data, disabling access to memory regions, allowing memory regions to be defined as re ad-on ly and detecting unexpected memory accesses that could potentially break the system.

Product data sheet Rev. 5 — 9 September 2014 41 of 122

NXP Semiconductors

32-bit ARM Cortex-M3 microcontroller

The MPU separates the memory into distinct regions and implements protection by preventing disallowed accesses. The MPU support s up to eight regio ns each of which can be divided into eight subregions. Accesses to memory locations that are not defined in the MPU regions, or not permitted by the region setting, will cause the Memory Management Fault exception to take place.

7.7 Memory map

Table 6. LPC178x/177x memory usage and details

Address range General Use Address range details and de s crip tion

0x0000 0000 to 0x1FFF FFFF

0x2000 0000 to 0x3FFF FFFF

0x4000 0000 to 0x7FFF FFFF

0x8000 0000 to 0xDFFF FFFF

0xE000 0000 to 0xE00F FFFF

On-chip non-volatile memory

On-chip main SRAM 0x1000 0000 - 0x1000 FFFF For devices with 64 kB of main SRAM.

Boot ROM 0x1FFF 0000 - 0x1FFF 1FFF 8 kB Boot ROM with flash services. On-chip SRAM

(typically used for peripheral data)

AHB peripherals 0x2008 0000 - 0x200B FFFF See Figure 6 APB Peripherals 0x4000 0000 - 0x4007 FFFF APB0 Peripherals, up to 32 peripheral blocks of

Off-chip Memory via the External Memory Controller

Cortex-M3 Private Peripheral Bus

0x0000 0000 - 0x0007 FFFF For devices with 512 kB of flash memory. 0x0000 0000 - 0x0003 FFFF For devices with 256 kB of flash memory. 0x0000 0000 - 0x0001 FFFF For devices with 128 kB of flash memory. 0x0000 0000 - 0x0000 FFFF For devices with 64 kB of flash memory.

0x1000 0000 - 0x1000 7FFF For devices with 32 kB of main SRAM. 0x1000 0000 - 0x1000 3FFF For devices with 16 kB of main SRAM.

0x2000 0000 - 0x2000 1FFF Peripheral RAM - bank 0 (first 8 kB) 0x2000 2000 - 0x2000 3FFF Peripheral RAM - bank 0 (second 8 kB) 0x2000 4000 - 0x2000 7FFF Peripheral RAM - bank 1 (16 kB)

16 kB each.

0x4008 0000 - 0x400F FFFF APB1 Peripherals, up to 32 peripheral blocks of

16 kB each. Four static memory chip selects: 0x8000 0000 - 0x83FF FFFF Static memory chip select 0 (up to 64 MB) 0x9000 0000 - 0x93FF FFFF Static memory chip select 1 (up to 64 MB) 0x9800 0000 - 0x9BFF FFFF St atic memory chip select 2 (up to 64 MB) 0x9C00 0000 - 0x9FFF FFFF Static memory chip select 3 (up to 64 MB) Four dynamic memory chip selects: 0xA000 0000 - 0xAFFF FFFF Dynamic memory chip select 0 (up to 256MB) 0xB000 0000 - 0xBFFF FFFF Dynamic memory chip select 1 (up to 256MB) 0xC000 0000 - 0xCFFF FFFF Dynamic memory chip select 2 (up to 256MB) 0xD000 0000 - 0xDFFF FFFF Dynamic memory chip select 3 (up to 256MB) 0xE000 0000 - 0xE00F FFFF Cortex-M3 related functions, includes the NVIC

and System Tick Timer.

LPC178x/7x

for details

The LPC178x/7x incorporate several distinct memory regions, shown in the following figures. Figure 6

shows the overall map of the entire address space from the user

program viewpoint following reset. The interrupt vector area supports address remapping. The AHB peripheral area is 2 MB in size, and is divided to allow for up to 128 per ipherals.

The APB peripheral area is 1 MB in size and is divided to allow for up to 64 peripherals. Each peripheral of either type is allocated 16 kB of space. This allows simplifying the address decoding for each peripheral.

Product data sheet Rev. 5 — 9 September 2014 42 of 122

Product data sheet Rev. 5 — 9 September 2014 43 of 122

0x4000 4000

0x4000 8000

0x4000 C000

0x4001 0000

0x4001 8000

0x4002 0000

0x4002 8000

0x4002 C000

0x4003 4000

0x4003 0000

0x4003 8000

0x4003 C000

0x4004 0000

0x4004 4000

0x4004 8000

0x4004 C000

0x4005 C000

0x4006 0000

0x4008 0000

0x4002 4000

0x4001 C000

0x4001 4000

0x4000 0000

APB1 peripherals

0x4008 0000

0x4008 8000

0x4008 C000

0x4009 0000

0x4009 4000

0x4009 8000

0x4009 C000

0x400A 0000

0x400A 4000

0x400A 8000

0x400A C000

0x400B 0000

0x400B 4000

0x400B 8000

0x400B C000

0x400C 0000

0x400F C000

0x4010 0000

SSP0

DAC

timer 2

timer 3

UART2

UART3

USART4

(1)

I2C2

1 - 0 reserved

SSP2

reserved

motor control PWM

reserved

30 - 17 reserved

system control31

reserved

64 kB main static RAM

(1)

EMC 4 x static chip select

(1)

EMC 4 x dynamic chip select

(1)

reserved

private peripheral bus

0x0000 0000

0 GB

0.5 GB

4 GB

1 GB

0x1000 0000

0x1001 0000

0x1FFF 0000

0x2000 0000

0x2000 8000

0x2008 0000

0x2200 0000

0x200A 0000

0x2400 0000

0x2800 0000

0x4000 0000

0x4008 0000

0x4010 0000

0x4200 0000

0x4400 0000

0x8000 0000

0xA000 0000

0xE000 0000

0xE010 0000

0xFFFF FFFF

reserved

APB0 peripherals

0xE004 0000

AHB peripherals

APB1 peripherals

peripheral

SRAM bit-band alias addressing

peripheral bit-band alias addressing

16 kB peripheral SRAM1

(1)

0x2000 4000

16 kB peripheral SRAM0

(1)

LPC178x/7x

0x0008 0000

512 kB on-chip flash

(1)

QEI

(1)

SD/MMC

(1)

APB0 peripherals

WWDT

timer 0

timer 1

UART0

UART1

reserved

CAN AF RAM

CAN common

CAN1

CAN2

CAN AF registers

PWM0

RTC/event recorder + backup registers

GPIO interrupts

pin connect

SSP1

ADC

22 - 19 reserved

31 - 24 reserved

PWM1

8 kB boot ROM

0x0000 0000

0x0000 0400

active interrupt vectors

+ 256 words

I-code/D-code memory space

002aaf574

reserved

0x1FFF 2000

0x2900 0000

reserved

0x2008 0000

0x2008 4000

0x2008 8000

0x2008 C000

0x200A 0000

0x2009 C000

AHB peripherals

LCD

(1)

USB

(1)

Ethernet

(1)

GPDMA controller

0x2009 0000

CRC engine

0x2009 4000

0x2009 8000

GPIO

EMC registers

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

NXP Semiconductors

(1) Not available on all parts. See Table 2 and Table 6.

Fig 6. LPC178x/7x memory map

32-bit ARM Cortex-M3 microcontroller

LPC178x/7x

NXP Semiconductors

7.8 Nested Vectored Interrupt Controller (NVIC)

The NVIC is an integral part of the Cortex-M3. The tight coup ling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts.

7.8.1 Features

• Controls system exceptions and peripheral interrupts.

• On the LPC178x/7x, the NVIC supports 40 vectored interrupts.

• 32 programmable interrupt priority levels, with hardware priority level masking.

• Relocatable vector table.

• Non-Maskable Interrupt (NMI).

• Software interrup t ge ne ra tio n .

7.8.2 Interrupt sources

Each peripheral device has one interrupt line con nected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source.

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Any pin on port 0 and port 2 regardless of the selected function can be programmed to generate an interrupt on a rising edge, a falling edge, or both.

7.9 Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals.

Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined.

Most pins can also be configured as open-drain outputs or to have a pull-up, p ull-down, o r no resistor enabled.

7.10 External memory controller

Remark: Supported memory size and type and EMC bus width vary for different parts

(see Table 2

). The EMC pin configuration for each part is shown in Table 7.

Product data sheet Rev. 5 — 9 September 2014 44 of 122

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 7. External memory controller pin configuration

Part Data bus pins Address bus

LPC1788FBD208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0]

LPC1788FET208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0]

LPC1788FET180 EMC_D[15:0] EMC_A[19:0] EMC_BLS[1:0]

LPC1788FBD144 EMC_D[7:0] EMC_A[15:0] EMC_BLS[3:2]

LPC1787FBD208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0]

LPC1786FBD208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0]

LPC1785FBD208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0]

LPC1778FBD208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0]

LPC1778FET208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0]

LPC1778FET180 EMC_D[15:0] EMC_A[19:0] EMC_BLS[1:0]

LPC1778FBD144 EMC_D[7:0] EMC_A[15:0] EMC_CS[1:0]

LPC1777FBD208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0]

LPC1776FBD208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0]

LPC1776FET180 EMC_D[15:0] EMC_A[19:0] EMC_BLS[3:0]

LPC1774FBD208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0]

LPC1774FBD144 EMC_D[7:0] EMC_A[15:0] EMC_CS[1:0]

Control pins

pins

SRAM SDRAM

EMC_CS[3:0], EMC_OE, EMC_WE

EMC_CS[3:0] EMC_OE, EMC_WE

EMC_CS[1:0], EMC_OE

EMC_CS[1:0], EMC_OE, EMC_WE

EMC_CS_[3:0] EMC_OE, EMC_WE

EMC_CS[3:0], EMC_OE

EMC_CS[3:0], EMC_OE, EMC_WE

EMC_CS[3:0] EMC_OE, EMC_WE

EMC_CS[1:0], EMC_OE

EMC_OE

EMC_CS[3:0] EMC_OE

EMC_CS[3:0] EMC_OE, EMC_WE

EMC_CS[3:0] EMC_OE

EMC_OE, EMC_WE

, EMC_WE

, ,

EMC_RAS, EMC_CAS, EMC_DYCS[3:0], EMC_CLK[1:0], EMC_CKE[3:0], EMC_DQM[3:0]

EMC_RAS, EMC_CAS, EMC_DYCS[1:0], EMC_CLK[1:0], EMC_CKE[1:0], EMC_DQM[1:0]

not available

EMC_RAS, EMC_CAS, EMC_DYCS[3:0], EMC_CLK[1:0], EMC_CKE[3:0], EMC_DQM[3:0]

EMC_RAS, EMC_CAS, EMC_DYCS[1:0], EMC_CLK[1:0], EMC_CKE[1:0], EMC_DQM[1:0]

not available

EMC_RAS, EMC_CAS, EMC_DYCS[3:0], EMC_CLK[1:0], EMC_CKE[3:0], EMC_DQM[3:0]

EMC_RAS, EMC_CAS, EMC_DYCS[1:0], EMC_CLK[1:0], EMC_CKE[1:0], EMC_DQM[1:0]

EMC_RAS, EMC_CAS, EMC_DYCS[3:0], EMC_CLK[1:0], EMC_CKE[3:0], EMC_DQM[3:0]

not available

Product data sheet Rev. 5 — 9 September 2014 45 of 122

NXP Semiconductors

The LPC178x/7x EMC is an ARM PrimeCell MultiPort Memory Controller peripheral offering support for asynchronous static memory devices such as RAM, ROM, and flash. In addition, it can be used as an interface with off-chip memory-mapped devices and peripherals. The EMC is an Advanced Microcontroller Bus Architecture (AMBA) compliant peripheral.

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

See Table 6

7.10.1 Features

• Dynamic memory interface support including single data rate SDRAM.

• Asynchronous static memory device support including RAM, ROM, and flash, with or

without asynchronous page mode.

• Low transaction latency.

• Read and write buffers to reduce latency and to improve performance.

• 8/16/32 data and 16/20/26 address lines wide static memory support.

• 16 bit and 32 bit wide chip select SDRAM memory support.

• Static memory features include:

– Asynchronous page mode read. – Programmable Wait States. – Bus turnaround delay. – Output enable and write enable delays. – Extended wait.

• Four chip selects for synchronous memory and four chip selects for static memory

devices.

• Power-saving modes dynamically control EMC_CKE and EMC_CLK outputs to

SDRAMs.

• Dynamic memory self-refresh mode controlled by software.

• Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row

address synchronous memory parts. That is typical 512 MB, 256 MB, and 128 MB parts, with 4, 8, 16, or 32 data bits per device.

• Separate reset domains allow the for auto-refresh through a chip reset if desired.

for EMC memory access.

Note: Synchronous static memory devices (synchronous burst mode) are not supported.

7.11 General purpose DMA controller

The GPDMA is an AMBA AHB compliant peripheral allowing selected peripherals to have DMA support.

The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. The source and destination areas can each be either a memory region or a peripheral and can be accessed through the AHB master. The GPDMA controller allows data transfers between the various on-chip SRAM areas and supports the SD/MMC card interface, all SSPs, the

S, all UARTs, the A/D Converter, and the D/A Converter peripherals. DMA can also be

I triggered by selected timer match conditions. Memory-to-memory transfers and transfers to or from GPIO are supported.

Product data sheet Rev. 5 — 9 September 2014 46 of 122

NXP Semiconductors

7.11.1 Features

• Eight DMA channels. Each channel can support an unidirectional transfer.

• 16 DMA request lines.

• Single DMA and burst DMA request signals. Each peripheral connected to the DMA

• Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and

• Scatter or gather DMA is supported through the use of linked lists. This means that

• Hardware DMA channel priority.

• AHB slave DMA programming interface. The DMA Controller is programmed by

• One AHB bus master for transferring data. The interface transfers data when a DMA

• 32-bit AHB master bus width.

• Incrementing or non-incrementing addressing for source and destination.

• Programmable DMA burst size. The DMA burst size can be programmed to more

• Internal four-word FIFO per channel.

• Supports 8, 16, and 32-bit wide transactions.

• Big-endian and little-endian support. The DMA Controller defaults to little-endian

• An interru pt to the pr ocessor ca n be gene rated o n a DMA comp letion or when a DMA

• Raw interrupt status. The DMA error and DMA count raw interrupt status can be read

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Controller can assert either a burst DMA request or a single DMA requ est. The DMA burst size is set by programming the DMA Controller.

peripheral-to-peripheral transfe rs ar e su pp or te d.

the source and destination areas do not have to occupy contiguous areas of memory.

writing to the DMA control registers over the AHB slave interface.

request goes active.

efficiently transfer data.

mode on reset.

error has occurred.

prior to masking.

7.12 CRC engine

The Cyclic Redundancy Check (CRC) generator with programmable polynomial settings supports several CRC standards commonly used. To save system power and bus bandwidth, the CRC engine supports DMA transfers.

7.12.1 Features

• Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32.

– CRC-CCITT: x – CRC-16: x – CRC-32: x

+ x12 + x5 + 1

+ x15 + x2 + 1

+ x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1

• Bit order reverse and 1’s complement programmable setting for input data and CRC

sum.

• Programmable seed number setting.

• Supports CPU PIO or DMA back-to-back transfer.

Product data sheet Rev. 5 — 9 September 2014 47 of 122

NXP Semiconductors

• Accept any size of data width per write: 8, 16 or 32-bit.

7.13 LCD controller

Remark: The LCD controller is available on parts LPC1788/87/86/85.

The LCD controller provides all of the necessary control signals to interface directly to a variety of color and monochrome LCD panels. Both ST N (sing le a nd dua l panel) and TFT panels can be operated. The disp lay resolutio n is selectable and can be up to 1024  768 pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode. An on-chip 512-byte color palette allows reducing bus utilization (i.e. memory size of the displayed data) while still supporting a large number of colors.

The LCD interface includes its own DMA controller to allow it to operate independently of the CPU and other system functions. A built-in FIFO acts as a buffer for display da ta, providing flexibility for system timing. Hardware cursor support can further reduce the amount of CPU time needed to operate the display.

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

– 8-bit write: 1-cycle operation. – 16-bit write: 2-cycle operation (8-bit x 2-cycle). – 32-bit write: 4-cycle operation (8-bit x 4-cycle).

7.13.1 Features

• AHB master interface to access frame buffer.

• Setup and control via a separate AHB slave interface.

• Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data.

• Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays

with 4-bit or 8-bit interfaces.

• Supports single and dual-panel color STN displays.

• Supports Thin Film Transistor (TFT) color displays.

• Programmable display resolution including, but not limited to: 320  200, 320  240,

640  200, 640  240, 640  480, 800  600, and 1024  768.

• Hardware cursor support for single-panel displays.

• 15 gray-level monochrome, 3375 color STN, and 32 K color palettized TFT support.

• 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN.

• 1, 2, 4, or 8 bpp palettized color displays for color STN and TFT.

• 16 bpp true-color non-palettized, for color STN and TFT.

• 24 bpp true-color non-palettized, for color TFT.

• Programmable timing for different display panels.

• 256 entry, 16-bit palette RAM, arranged as a 128  32-bit RAM.

• Frame, line, and pixel clock signals.

• AC bias signal for STN, data enable signal for TFT panels.

• Supports little and big-endian, and Windows CE data formats.

• LCD panel clock may be generated from the peripheral clock, or from a clock input

pin.

Product data sheet Rev. 5 — 9 September 2014 48 of 122

NXP Semiconductors

7.14 Ethernet

Remark: The Ethernet block is available on parts LPC1788/86 and LPC1778/76.

The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity. Automatic frame transmission and reception with scatter-gather DMA off-loads many operations from the CPU.

The Ethernet block and the CPU share the ARM Cortex-M3 D-code and system bus through the AHB-multilayer matrix to access the various on-chip SRAM blocks for Ethernet data, control, and status information.

The Ethernet block interfaces between an off-chip Ethernet PHY using the Media Independent Interface (MII) or Reduced MII (RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial bus.

7.14.1 Features

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

• Ethernet standards support:

– Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX,

100 Base-FX, and 100 Base-T4.

– Fully compliant with IEEE standard 802.3. – Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back

pressure.

– Flexible transmit and receive frame options. – Virtual Local Area Network (VLAN) frame support – .

• Memory management:

– Independent transmit and receive buffers memory mapped to shared SRAM. – DMA managers with scatter/gather DMA and arrays of frame descriptors. – Memory traffic optimized by buffering and pre-fetching.

• Enhanced Ethernet features:

– Receive filtering. – Multicast and broadcast frame support for both transmit and receive. – Optional automatic Frame Check Sequence (FCS) insertion with Circular

Redundancy Check (CRC) for transmit.

– Selectable automatic transmit frame padding. – Over-length frame support for both transmit and receive allows any length frames. – Promiscuous receive mode. – Automatic collision back-off and frame retransmission. – Includes power management by clock switching. – Wake-on-LAN power management support allows system wake-up: using the

receive filters or a magic frame detection filter.

Product data sheet Rev. 5 — 9 September 2014 49 of 122

NXP Semiconductors

• Physical interface:

7.15 USB interface

Remark: The USB Device/Host/OTG controller is available on parts LPC1788/87/86/85

and LPC1778/77/76. The USB Device-only controller is available on parts LPC1774. The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a

host and one or more (up to 127) peripherals. The host controller allocates the USB bandwidth to attached devices through a token-based protocol. The bus supports hot plugging and dynamic configuration of the devices. All transactions are initiated by the host controller.

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

– Attachment of external PHY chip through standar d MII or RMII interface. – PHY register access is available via the MIIM interface.

Details on typical USB interfacing solutions can be found in Section 14.1

7.15.1 USB device controller

The device controller enables 12 Mbit/s data exchange with a USB host controller. It consists of a register interface, serial interface engine, endpoint buffer memory, and a DMA controller. The seria l interface e ngine decod es the USB dat a strea m and writes dat a to the appropriate endpoint buffer. The status of a completed USB transfer or error condition is indicated via status registers. An interrupt is also generated if enabled. When enabled, the DMA controller transfers data between the endpoint buffer and the USB RAM.

7.15.1.1 Features

• Fully compliant with USB 2.0 Specification (full speed).

• Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM.

• Supports Control, Bulk, Interrupt and Isochronous endpoints.

• Scalable realization of endpoints at run time.

• Endpoint Maximum packet size selection (up to USB maximum specification) by

software at run time.

• Supports SoftConnect and GoodLink features.

• While USB is in the Suspend mode, the LPC178x/7x can enter one of the reduced

power modes and wake up on USB activity.

• Supports DMA transfers with all on-chip SRAM blocks on all non-control endpoints.

• Allows dynamic switching between CPU-controlled and DMA modes.

• Double buffer implementation for Bulk and Isochronous endpoints.

7.15.2 USB host controller

The host controller enables full- and low-speed dat a exchange with USB devices attached to the bus. It consists of register interface, serial interface engine and DMA controller. The register interface complies with the Open Host Controller Interface (OHCI) specification.

7.15.2.1 Features

• OHCI compliant.

Product data sheet Rev. 5 — 9 September 2014 50 of 122

NXP Semiconductors

• Two downstream ports.

• Supports per-port power switching.

7.15.3 USB OTG controller

USB OTG is a supplement to the USB 2.0 Specification that augments the capability of existing mobile devices and USB peripherals by adding host functionality for connection to USB peripherals.

The OTG Controller integrates the host controller, device controller, and a master-o nly I interface to implement OTG dual-role device functionality. The dedicated I controls an external OTG transceiver.

7.15.3.1 Features

• Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision

• Hardware support for Host Negotiation Protocol (HNP).

• Includes a programmable timer required for HNP an d Session Request Protocol

• Supports any OTG transceiver compliant with the OTG Transceiver Specification

1.0a.

(SRP).

(CEA-2011), Rev. 1.0.

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

C interface

7.16 SD/MMC card interface

Remark: The SD/MMC card interface is available on parts LPC1788/87/86/85 and parts

LPC1778/77/76. The Secure Digital and Multimedia Card Interface (MCI) allows access to external SD

memory cards. The SD card interface conforms to the SD Multimedia Card Specification Version 2.11.

7.16.1 Features

• The MCI provides all functions specific to the SD/MMC memory card. These include

the clock generation unit, power management control, and command and data transfer.

• Conforms to Multimedia Card Specification v2.11.

• Conforms to Secure Digital Memory Card Physical Layer Specification, v0.96.

• Can be used as a mu ltimedia card bus or a secure d igit al memo ry card bus ho st. The

SD/MMC can be connected to several multimedia cards or a single secure digital memory card.

• DMA supported through the GPDMA controller.

7.17 Fast general purpose parallel I/O

Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simult an eou sly. The value of the output register may be read back as well as the current state of the port pins.

LPC178x/7x use accelerated GPIO functions:

Product data sheet Rev. 5 — 9 September 2014 51 of 122

NXP Semiconductors

• GPIO registers are accessed through the AHB multilayer bus so that the fastest

• Mask registers allow treating sets of port bits as a group, leaving other bits

• All GPIO registers are byte and half-word addressable.

• Entire port value can be written in one instruction.

• Support for Cortex-M3 bit banding.

• Support for use with the GPDMA controller.

Additionally, any pin on Port 0 and Port 2 providing a digital function can be programmed to generate an interrupt on a rising edge, a falling edge, or both. The edge detection is asynchronous, so it may operate when clocks are not present such as during Power-down mode. Each enabled interrupt can be used to wake up the chip from Power-down mode.

7.17.1 Features

• Bit leve l set and clear registers allow a singl e instruction to set or clear an y number of

• Direction control of individual bits.

• All I/O default to inputs after reset.

• Pull-up/pull-down resistor configuration and open-drain configuration can be

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

possible I/O timing can be achieved.

unchanged.

bits in one port.

programmed through the pin connect block for each GPIO pin.

7.18 12-bit ADC

The LPC178x/7x contain one ADC. It is a single 12-bit successive approximation ADC with eight channels and DMA support.

7.18.1 Features

• 12-bit successive approximation ADC.

• Input multiplexing among eight pins.

• Power-down mode.

• Measurement range V

• 12-bit conversion rate: up to 400 kHz.

• Individual channels can be selected for conversion.

• Burst conversion mode for single or multiple inputs.

• Optional conversion on transition of input pin or Timer Match signal.

• Individual result registers for each ADC channel to reduce interrupt overhead.

• DMA support.

7.19 10-bit DAC

The LPC178x/7x contain one DAC. The DAC allo ws to generate a variable analog output. The maximum output value of the DAC is VREFP.

to VREFP.

Product data sheet Rev. 5 — 9 September 2014 52 of 122

NXP Semiconductors

7.19.1 Features

• 10-bit DAC.

• Resistor string architecture.

• Buffered output.

• Power-down mode.

• Selectable output drive.

• Dedicated conversion timer.

• DMA support.

7.20 UARTs

Remark: USART4 is not available on part LPC1774FBD144.

The LPC178x/7x contain five UARTs. In addition to sta ndard transmit and receive data lines, UART1 also provides a full modem control handshake interface and support for RS-485/9-bit mode allowing both software address detection and automatic address detection using 9-bit mode.

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

The UARTs include a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz.

7.20.1 Features

• Maximum UART data bit rate of 7.5 MBit/s.

• 16 B Receive and Transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

• Built-in fractional baud rate generator covering wide range of baud rates with out a

need for external crystals of particular values.

• Auto-baud capability.

• Fractional divider for baud rate control, auto baud capabilities and FIFO control

mechanism that enables software flow control implementation.

• Support for RS-485/9-bit/EIA-485 mode and multiprocessor addressing.

• All UARTs have DMA support for both transm it an d re ce ive.

• UART1 equipped with standard modem interface signals. This module also provides

full support for hardware flow control (auto-CTS/RTS).

• USART4 includes an IrDA mode to support infrared communication.

• USART4 supports synchronous mode and a smart card mode conforming to

ISO7816-3.

7.21 SSP serial I/O controller

The LPC178x/7x contain three SSP controllers. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus

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during a given data transfer . The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data.

7.21.1 Features

• Maximum SSP speed of 33 Mbit/s (master) or 10 Mbit/s (slave).

• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

• Synchronous serial communication.

• Master or slave operation.

• 8-frame FIFOs for both transmit and receive.

• 4-bit to 16-bit frame.

• DMA transfers supported by GPDMA.

7.22 I2C-bus serial I/O controllers

The LPC178x/7x contain three I2C-bus controllers.

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Semiconductor Microwire buses.

C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line

The I (SCL) and a Serial Data Line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or sla ve mode, de pending o n whether the chip ha s to initiate a data transfer or is only addressed. The I controlled by more than one bus master connected to it.

7.22.1 Features

• All I

(Fast I up to 400 kbit/s.

• The I

using pins P5[2] and P5[3].

• Easy to configure as master, slave, or master/slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Ser ial clock synchronization can be used as a handshake mechani sm to suspend and

resume serial transfer.

• The I

• Both I

mode.

C is a multi-master bus and can be

C-bus controllers can use standard GPIO pins with bit rates of up to 400 kbit/s

C-bus). The I2C0-bus interface uses special open-drain pins with bit rates of

C-bus interface supports Fast-mode Plus with bit rates up to 1 Mbit/s for I2C0

C-bus can be used for test and diagnostic purposes.

C-bus controllers support multiple address recognition and a bus monitor

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7.23 I2S-bus serial I/O controllers

The LPC178x/7x contain one I2S-bus interface. The I2S-bus provides a standard communication interface for digital audio applications.

The I and one word select signal. The basic I master, and one slave. The I and receive channel, each of which can operate as either a master or a slave.

7.23.1 Features

• Th e interface has separate input/output channels each of which can operate in master

• Capable of handling 8-bit, 16-bit, and 32-bit word sizes.

• Mono and stereo audio data supported.

• The sampling frequency can range from 16 kHz to 48 kHz (16, 22.05, 32, 44.1,

• Configurable word select period in master mode (separately for I

• Two 8 word FIFO data buffers are provided, one for transmit and one for receive.

• Generates interrupt requests when buffer levels cross a programmable boundary.

• Two DMA requests, controlled by programmable buffer levels. These are connected

• Controls include reset, stop and mute options separately for I

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

S-bus specification defines a 3-wire serial bus using one data line, one clock line,

S interface on the LPC178x/7x provides a separate transmit

or slave mode.

48) kHz.

to the GPDMA block.

S connection has one master , which is always the

S input and output).

S input and I2S output.

7.24 CAN controller and acceptance filters

The LPC178x/7x contain one CAN controller with two channels. The Controller Area Network (CAN) is a serial communications protocol which efficiently

supports distributed real-time control with a very high level of security. Its domain of application ranges from high-speed networks to low cost multiplex wiring.

The CAN block is intended to support multiple CAN buses simultaneously, allowing the device to be used as a gateway, switch, or router between two of CAN buses in industrial or automotive applications.

Each CAN controller has a register structure similar to the NXP SJA1000 and the PeliCAN Library block, but the 8-bit registers of those devices have been combined in 32-bit words to allow simultaneous access in the ARM environment. The main op erational dif fer ence is that the recognition of received Identifiers, known in CAN terminology as Acceptance Filtering, has been removed from the CAN controllers and centralized in a global Acceptance Filter.

7.24.1 Features

• Two CAN controllers and buses.

• Data rates to 1 Mbit/s on each bus.

• 32-bit register and RAM access.

• Compatible with CAN specification 2.0B, ISO 11898-1.

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• Global Acceptance Filter recognizes 11-bit and 29-bit receive identifiers for all CAN

• Acceptance Filter can provide FullCAN-style automatic reception for selected

• FullCAN messages can generate interrupt s.

7.25 General purpose 32-bit timers/external event counters

The LPC178x/7x include four 32-bit timer/counters. The timer/counter is designed to count cycles of the system derived clock or an

externally-supplied clock. It can optionally generate interrupts, generate timed DMA requests, or perform other actions at specified timer values, based on four match registers. Each timer/counter also includes two capture input s to trap the timer value when an input signal transitions, optionally generating an interrupt.

7.25.1 Features

• A 32-bit timer/counter with a programmable 32-bit prescaler.

• Counter or timer operation.

• Two 32-bit capture channels per timer, that can take a snapshot of the timer value

• Four 32-bit match registers that allow:

• Up to four external outputs corresponding to match registers, with the following

• Up to two match registers can be used to generate timed DMA requests.

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

buses.

Standard Identifiers.

when an input signal transitions. A capture event may also generate an interrupt.

– Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation.

capabilities:

– Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match.

7.26 Pulse Width Modulator (PWM)

The LPC178x/7x contain two standard PWMs. The PWM is based on the standard Timer block and inherits all of its features, although

only the PWM function is pinned out on the LPC17 8x/7x. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur , based on seve n match registers. The PWM function is in addition to these features, and is based on match register events.

The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions.

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Two match registers can be used to provide a single edge controlled PWM output. One match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single edge controlled PWM outputs require only one match re gister each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs.

Three match registers can be used to provide a PWM output with both edges controlled. Again, the PWMMR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs.

With double edge controlled PWM outputs, specific match registers control the rising and falling edge of the output. This allows both positive going PWM pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge occurs prior to the rising edge).

7.26.1 Features

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

• LPC178x/7x has two PWM blocks with Counter or Timer operation (may use the

peripheral clock or one of the capture inputs as the clock source ).

• Seven match registers allow up to 6 single edge controlled or 3 double edge

controlled PWM outputs, or a mix of both types. The match registers also allow:

– Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation.

• Supports single edge controlled and/or double edge controlled PWM outputs. Single

edge controlled PWM outputs all go high at the beginning of each cycle unless the output is a constant low. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses.

• Pulse period and width can be any number of timer counts. This allows complete

flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate.

• Double edge controlled PWM outputs can be programmed to be either positive going

or negative going pulses.

• Match register updates are synchronized with pulse outputs to prevent generation of

erroneous pulses. Software must ‘release’ new match values before they can b ecome effective.

• Ma y be used as a st andard 32- bit timer/co unter with a prog rammable 32-bit prescaler

if the PWM mode is not enabled.

7.27 Motor control PWM

The LPC178x/7x contain one motor control PWM. The motor control PWM is a specialized PWM supporting 3-phase motors and other

combinations. Feedback inputs are provided to automatically sense rotor position and use that information to ramp speed up or down. An abort input is also provided that causes the

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PWM to immediately release all motor drive outputs. At the same time, the motor control PWM is highly configurable for other generalized timing, counting, capture, and compare applications.

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

The maximum PWM speed is determined by the PWM resolution (n) and the operating frequency f: PWM speed = f/2

Table 8. PWM spe ed at operating frequency 120 MHz

PWM resolution PWM speed

6 bit 1.875 MHz 8 bit 0.468 MHz 10 bit 0.1 17 MHz

(see Table 8).

7.28 Quadrature Encoder Interface (QEI)

Remark: The QEI is available on parts LPC1788/87/86 and LPC1778/77/76

A quadrature encoder, also known as a 2-channel incremental encoder, converts angular displacement into two pulse signals. By monitoring both the number of pulses and the relative phase of the two signals, the user ca n tr ack th e position, d ire ction of rotation, and velocity. In addition, a third channel, or index signal, can be used to reset the position counter. The quadrature encoder interface decodes the digital pulses from a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, the QEI can capture the velocity of the encoder wheel.

7.28.1 Features

• Tracks encoder position.

• Increments/decrements depending on direction.

• Programmable for 2 or 4 position counting.

• Velocity capture using built-in timer.

• Velocity compare function with “less than” interrupt.

• Uses 32-bit registers for position and velocity.

• Three position compare registers with interrupts.

• Index counter for revolution counting.

• Index compare register with interrupts.

• Can combine index and position interrupts to produce an interrupt for whole and

partial revolution displacement.

• Digital filter with programmable delays for encoder input signals.

• Can accept decoded signal inputs (clk and direction).

• Connected to APB.

7.29 ARM Cortex-M3 system tick timer

The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception at a 10 ms interval. In the LPC178x/7x, this timer can be clocked from the internal AHB clock or from a device pin.

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7.30 Windowed WatchDog Timer (WWDT)

The purpose of the watchdog is to reset the controller if software fails to periodically service it within a programmable time window.

7.30.1 Features

• Internally resets chip if not periodically reloaded during the programmable time-out

• Optional windowed operation requires reload to occur between a minimum and

• Optional warning interrupt can be generated at a programmable time prior to

• Ena bled by softwar e but requires a hardware r eset or a watchdog reset/interrupt to be

• Incorrect feed sequence causes reset or interrupt if enabled.

• Flag to indicate watchdog reset.

• Programmable 24-bit timer with internal prescaler.

• Selectable time period from (T

• The Watchdog Clock (WDCLK) source is a dedicated watchdog oscillator, which is

32-bit ARM Cortex-M3 microcontroller

period.

maximum time period, both programmable.

watchdog time-out.

disabled.

cy(WDCLK)

multiples of T

always running if the watchdog timer is enabled.

cy(WDCLK)

 4.

 256  4) to (T

LPC178x/7x

cy(WDCLK)

 224 4) in

7.31 RTC and backup registers

The RTC is a set of counters for measuring ti me when system power is on, and optiona lly when it is off. The RTC on the LPC178x/7x is designed to have very low power consumption. The RTC will typically run from the main chip power supply conserving battery power while the rest of the device is powered up. When operating from a battery, the RTC will continue working down to 2.1 V. Battery power can be provided from a standard 3 V lithium button cell.

An ultra-low power 32 kHz oscillator provides a 1 Hz clock to the time counting portion of the RTC, moving most of the power consumption out of the time counting function.

The RTC includes a calibration mechanism to allow fine-tuning the count rate in a way that will provide less than 1 second per day error when operated at a constant voltage and temperature.

The RTC contains a small set of backup registers (20 bytes) for holding data while the main part of the LPC178x/7x is powered off.

The RTC includes an alarm function that can wake up the LPC178x/7x from all reduced power modes with a time resolution of 1 s.

7.31.1 Features

• Measures the passage of time to maintain a calendar and clock.

• Ultra low power design to support battery powered systems.

• Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and

Day of Year.

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• Dedicated power supply pin can be connected to a battery or to the main 3.3 V.

• Per iodic inter rupt s can be g enerate d from increme nts of a ny field of the time regi sters.

• Backup registers (20 bytes) powered by VBAT.

• RTC power supply is isolated from the rest of the chip.

7.32 Event monitor/recorder

The event monitor/recorder allows recording of tampering events in sealed product enclosures. Sensors report any attempt to open the enclosure, or to tamper with the device in any other way. The event monitor/recorder stores records of such events when the device is powered only by the backup battery.

7.32.1 Features

• Supports three digital event inputs in the VBAT power domain.

• An event is defined as a level change at the digital event inputs.

• For each event channel, two timestamps mark the first and the last occurrence of an

• Runs in VBAT power domain, independent of system power supply. The

• Very low power consumption .

• Interrupt available if system is running.

• A qualified event can be used as a wake-up trigger.

• State of event interrupts accessible by software through GPIO.

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

event. Each channel also has a dedicated counter tr acking the total numb er of events. Timestamp values are taken from the RTC.

event/recorder/monitor can theref or e op er a te in Deep pow er -d ow n mo d e.

7.33 Clocking and power control

7.33.1 Crystal oscillators

The LPC178x/7x include four independent oscillators. These are the main oscillator, the IRC oscillator, the watchdog oscillator, and the RTC oscillator.

Following reset, the LPC178x/7x will operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the boot loader code to operate at a known frequency.

See Figure 7

Product data sheet Rev. 5 — 9 September 2014 60 of 122

for an overview of the LPC178x/7x clock generation.

NXP Semiconductors

IRC oscillator

main oscillator

(osc_clk)

LPC178x/7x

CLKSRCSEL

(system clock select)

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

MAIN PLL0

pll_clk

sysclk

ALT PLL1

sysclk

pll_clk

CCLKSEL

(CPU clock select)

sysclk

pll_clk

alt_pll_clk

USBCLKSEL

(USB clock select)

Fig 7. LPC178x/7x clock generation block diagram

alt_pll_clk

CPU CLOCK

DIVIDER

PERIPHERAL

CLOCK DIVIDER

EMC

CLOCK DIVIDER

USB

CLOCK DIVIDER

cclk

pclk

emc_clk

usb_clk

002aaf531

7.33.1.1 Internal RC oscillator

The IRC may be used as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed to 1 % accuracy over the entire voltage and temperature range.

Upon power-up or any chip reset, the LPC178x/7x use the IRC as the clock source. Software may later switch to one of the other available clock sources.

7.33.1.2 Main oscillator

The main oscillator can be used as the clock source for the CPU, with or without using the PLL. The main oscillator also provides the clock source for the alternate PLL1.

The main oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the main PLL. The clock selected as the PLL input is PLLCLKIN. The ARM processor clock frequency is referred to as CCLK elsewhere in this document. The frequencies of PLLCLKIN and CCLK are the same value unless the PLL is active and connected. The clock frequency for each peripheral can be selected individually and is referred to as PCLK. Refer to Section 7.33.2

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for additional information.

NXP Semiconductors

7.33.1.3 RTC oscillator

The RTC oscillator provides a 1 Hz clock to the RTC and a 32 kHz clock output that can be output on the CLKOUT pin in order to allow trimming the RTC oscillator without interference from a probe.

7.33.1.4 Watchdog oscillator

The Watchdog T imer has a dedicated watchdog oscillator that provides a 500 kHz clock to the Watchdog Timer. The watchdog oscillator is always running if the Watchdog Timer is enabled. The Watchdog oscillator clock can be output on the CLKOUT pin in order to allow observe its frequency.

In order to allow Watchdo g Timer operation with minimum power consumption, which can be important in reduced power modes, the Watchdog oscillator frequency is not tightly controlled. The Watchdog oscillator frequency will vary over temperature and power supply within a particular part, and may vary by processing across different parts. This variation should be taken into account when determin ing Watchdog reload values .

Within a particular part, temperature and power supply variations can produce up to a 17 % frequency variation. Frequency variation between devices under the same operating conditions can be up to 30 %.

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

7.33.2 Main PLL (PLL0) and Alternate PLL (PLL1)

PLL0 (also called the Main PLL) and PLL1 (also called the Alternate PLL) are functionally identical but have somewhat different input possibilities and output connections. These possibilities are shown in Figure 7 or the main oscillator and can potentially be used to provide the clocks to nearly everything on the device. The Alternate PLL receives its input only from the main oscillator and is intended to be used as an alternate source of clocking to the USB. The USB has timing needs that may not always be filled by the Main PLL.

Both PLLs are disabled and powered of f on reset. If the Alternate PLL is left disabled, the USB clock can be supplied by PLL0 if everything is set up to provide 48 MHz to the USB clock through that route. The source for each clock must be selected via the CLKSEL registers and can be further reduced by clock dividers as needed.

PLL0 accepts an input clock frequency from either the IRC or the main oscillator. If only the Main PLL is used, then its output frequency must be an integer multiple of all other clocks needed in the system. PLL1 takes its input only from the main oscillator, requiring an external crystal in the range of 10 to 25 MHz. In each PLL, the Current Controlled Oscillator (CCO) operates in the range of 156 MHz to 320 MHz, so there are additional dividers to bring the output down to the desired frequencies. The minimum output divider value is 2, insuring that the output of the PLLs have a 50 % duty cycle.

If the USB is used, the possibilities for the CPU clock and other clocks will be limited by the requirements that the frequency be precise and very low jitter, and that the PLL0 output must be a multiple of 48 MHz. Even multiples of 48 MHz that are within the operating range of the PLL are 192 MHz and 288 MHz. Also, only the main oscillator in conjunction with the PLL can meet the precision and jitter specifications for USB. It is du e to these limitations that the Alternate PLL is provided.

. The Main PLL can receive its input from either the IRC

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The alternate PLL accepts an input clock frequency from the main oscillator in the range of 10 MHz to 25 MHz only. When used as the USB clock, the input fre quency is multiplied up to a multiple of 48 MHz (192 MHz or 288 MHz as described above).

7.33.3 Wake-up timer

The LPC178x/7x begin operation at power-up and when awakened fr om Power-down mode by using the 12 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source.

When the main oscillator is initially activated, the wake-up timer allows sof twa re to ensure that the main oscillator is fully functional before the processor uses it as a clock source and starts to execute instructions. This is important at power on, all types of reset, and whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the wake-up Timer.

The wake-up timer monitors the crystal oscillator to check whether it is safe to begin code execution. When power is applied to the chip, or when some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depen ds on many factors, including the rate of V characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient conditions.

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

ramp (in the case of power on), the type of crystal and its electrical

DD(3V3)

7.33.4 Power control

The LPC178x/7x support a variety of power control features. There are four special modes of processor power reduction: Sleep mode, Deep-sleep mode, Po wer-down mode, and Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, the peripheral power control allows shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Each of the peripherals has its own clock divider which provides even better power control.

The integrated PMU (Power Management Unit) automatically adjusts internal regulators to minimize power consumption during Sleep, Deep-sleep, Power-down, and Deep power-down modes.

The LPC178x/7x also implement a separate power domain to allow turning off power to the bulk of the device while maintaining operation of the RTC and a small set of registers for storing data during any of the power-down modes.

7.33.4.1 Sleep mode

When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep mode does not need any special sequence other than re-enabling the clock to the ARM core.

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In Sleep mode, execution of instructions is suspended until either a Reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses.

The DMA controller can continue to work in Sleep mode and has a ccess to the p eriphe ral RAMs and all peripheral registers. The flash memory and the main SRAM are not available in Sleep mode, they are disabled in order to save power.

Wake-up from Sleep mode will occur whenever any enabled interrupt occurs.

7.33.4.2 Deep-sleep mode

In Deep-sleep mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Deep-sleep mode and the logic levels of chip pins remain static. The output of the IRC is disabled but the IRC is not powered down to allow fast wake-up. The RTC oscillator is not stopped because the RTC interrupts may be used as the wake-up source. The PLL is automatically turned off and disconnected. The clock divider registers are automatically reset to zero.

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

The Deep-sleep mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Deep-sleep mode reduces chip p ower consumption to a very low value. Power to the flash memory is left on in Deep-sleep mode, allowing a very quick wake-up.

Wake-up from Deep-sleep mode can initiated by the NMI, External Interrupts EINT0 through EINT3 an RTC Alarm interrupt, a USB input pin transition (USB activity interrupt), a CAN input pin transition, or a Watchdo g Timer time-out, when the related interrupt is enabled. Wake-up will occur whenever any enabled interrupt occurs.

On wake-up from Deep-sleep mode, the code execution and peripherals activities will resume after four cycles expire if the IRC was used before entering Deep-sleep mode. If the main external oscillator was used, the code execution will resume when 4096 cycles expire. PLL and clock dividers need to be reconfigured accordingly.

7.33.4.3 Power-down mode

Power-down mode does everything that Deep-sleep mode does but also turns off the power to the IRC oscillator and the flash memory. This saves more power but requires waiting for resumption of flash operation before execution of code or data access in the flash memory can be accomplished.

When the chip enters Power-down mode, the IRC, the main oscillator, and all clocks are stopped. The RTC remains running if it has been enabled and RTC interrupts may be used to wake up the CPU. The flash is forced into Power-down mode. The PLLs are automatically turned off and the clock selection multiplexers are set to use the system clock sysclk (the reset state). The clock divider control registers are automatically reset to zero. If the Watchdog timer is running, it will continue running in Power-down mode.

, GPIO interrupts, the Ethernet Wake-on -LAN interrupt, Brownout Detect,

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On the wake-up of Power-down mode, if the IRC was used before entering Power-down mode, it will take IRC 60 s to start-up. After this, four IRC cycles will expire before the code execution can then be resumed if the code was running from SRAM. In the meantime, the flash wake-up timer then counts 12 MHz IRC clock cycles to make the 100 s flash start-up time. When it times out, access to the flash will be allowed. Users need to reconfigure the PLL and clock dividers accordingly.

7.33.4.4 Deep power-down mode

In Deep power-down mode, power is shut off to the entire chip with the exception of the RTC module and the RESET pin.

To optimize power conservation, the user has the additional option of turning off or retaining power to the 32 kHz oscillator. It is also possible to use external circuitry to turn off power to the on-chip regulator via the V V

DD(3V3)

device operation can be restarted.

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

DD(REG)(3V3)

pins after entering Deep Power-down mode. Power must be restored before

pins and/or the I/O power via the

The LPC178x/7x can wake up from Deep power-down mode via the RESET alarm match event of the RTC.

7.33.4.5 Wake-up Interrupt Controller (WIC)

The WIC allows the CPU to automatically wake up from any enabled prior ity inte rrupt tha t can occur while the clocks are stopped in Deep-sleep, Power-down, and Deep power-down modes.

The WIC works in connection with the Nested Vectored Interrupt Controller (NVIC). When the CPU enters Deep-sleep, Power-down, or Deep power-down mode, the NVIC se nds a mask of the current interrupt situation to the WIC.This mask includes all of the interrupts that are both enabled and of sufficient priority to be serviced immediately. With this information, the WIC simply notices when one of the interrupts has occurred and then it wakes up the CPU.

The WIC eliminates the need to periodically wake up the CPU and poll the interrupts resulting in additional power savings.

7.33.5 Peripheral power control

A power control for peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings.

7.33.6 Power domains

pin or an

The LPC178x/7x provide two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the backup registers.

On the LPC178x/7x, I/O pads are powered by V

DD(3V3)

, while V

DD(REG)(3V3)

powers the on-chip voltage regulator which in turn provides power to the CPU and most of the peripherals.

Depending on the LPC178x/7x application, a design can use two power options to manage power consumption.

Product data sheet Rev. 5 — 9 September 2014 65 of 122

NXP Semiconductors

REAL-TIME CLOCK

BACKUP REGISTERS

REGULATOR

32 kHz

OSCILLATOR

POWER

SELECTOR

ULTRA-LOW

POWER

REGULATOR

RTC POWER DOMAIN

MAIN POWER DOMAIN

002aaf530

RTCX1

VBAT

(typical 3.0 V)

DD(REG)(3V3)

(typical 3.3 V)

RTCX2

DD(3V3)

to memories, peripherals, oscillators, PLLs

to core

to I/O pads

ADC

DAC

ADC POWER DOMAIN

DDA

VREFP

SSA

LPC178x/7x

The first option assumes that power consumption is not a concern and the design ties the V

DD(3V3)

supply for both pads, the CPU, and peripherals. While this solution is simple, it does not support powering down the I/O pad ring “on the fly” while keeping the CPU and peripherals alive.

and V

DD(REG)(3V3)

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

pins together. This approach requires only one 3.3 V power

The second option uses two power supplies; a 3.3 V supply for the I/O pads (V a dedicated 3.3 V supply for the CPU (V

DD(REG)(3V3)

). Having the on-chip voltage regulator

DD(3V3)

) and

powered independently from the I/O pad ring enables shutting down of the I/O pad power supply “on the fly” while the CPU and peripherals stay active.

The VBAT pin supplies power only to the RTC domain. The RTC operates at very low power, which can be supplied by an external battery. The device core power (V

DD(REG)(3V3)

) is used to operate the RTC whenever V power drain from the RTC battery when V V

DD(REG)(3V3)

> V

BAT

DD(REG)(3V3)

is at nominal levels and

is present. There is no

Fig 8. Power distribution

Product data sheet Rev. 5 — 9 September 2014 66 of 122

NXP Semiconductors

7.34 System control

7.34.1 Reset

Reset has four sources on the LPC178x/7x: the RESET pin, the Watchdog reset, Power-On Reset (POR), and the BrownOut Detection (BOD) circuit. The RESET Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains a usable level, starts the Wake-up timer (see description in

Section 7.33.3

the oscillator is running, a fixed number of clocks have passed, and the flash controller has completed its initialization.

When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values.

7.34.2 Brownout detection

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

pin is a

), causing reset to remain asserted until the external Reset is de-asserted,

The LPC178x/7x include 2-stage monitoring of the volt age on the V voltage falls below 2.2 V (typical), the BOD asserts an interrupt signal to the Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register.

The second stage of low-voltage detection asserts a reset to inactivate the LPC178x/7x when the voltage on the V alteration of the flash as operation of the vario us elem en ts of the chip woul d oth erwise become unreliable due to low voltage. The BOD circuit maintains this reset down below 1 V, at which point the power-on reset circuitry maintains the overall reset.

Both the 2.2 V and 1.85 V thresholds include some hysteresis. In normal operation, this hysteresis allows the 2.2 V detection to reliably interrupt, or a regularly executed event loop to sense the condition.

DD(REG)(3V3)

pins falls below 1.85 V (typical). This reset prevents

7.34.3 Code security (Code Read Protection - CRP)

This feature of the LPC178x/7x allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JT AG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP.

There are three levels of the Code Read Protection. CRP1 disables access to chip via the JTAG and allows partial flash update (excluding

flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased.

DD(REG)(3V3)

pins. If this

CRP2 disables access to chip via the JTAG and only allows full flash erase and update using a reduced set of the ISP commands.

Running an application with level CRP3 selected fully disables any access to chip via the JT AG pins and the ISP. This mode effectively disables ISP override using P2[10] pin, too. It is up to the user’s application to provide (if needed) flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via UART0.

Product data sheet Rev. 5 — 9 September 2014 67 of 122

NXP Semiconductors

CAUTION

7.34.4 APB interface

The APB peripherals are split into two separate APB buses in order to distribute the bus bandwidth and thereby reducing stalls caused by contention between the CPU and the GPDMA controller.

7.34.5 AHB multilayer matrix

The LPC178x/7x use an AHB multilayer matrix. This matrix connects the instruction (I-code) and data (D-code) CPU buses of the ARM Cortex-M3 to the flash memory, the main (64 kB) SRAM, and the Boot ROM. The GPDMA can also access all of these memories. Additionally, the matrix connects the CPU system bus and all of the DMA controllers to the various peripheral function s.

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device.

7.34.6 External interrupt inputs

The LPC178x/7x include up to 30 edge sensitive interrupt inputs combined with one level sensitive external interrupt input as selectable pin function. The external interrupt input can optionally be used to wake up the processor from Power-down mode.

7.34.7 Memory mapping control

The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table to alternate locations in the memory map. This is controlled via the Vector Table Offset Register contained in the NVIC.

The vector table may be located anywhere within the bottom 1 GB of Cortex-M3 address space. The vector table must be located on a 128 word (512 byte) boundary because the NVIC on the LPC178x/7x is configured for 128 total interrupts.

7.35 Debug control

Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and trace functions are supported in addition to a standard JTAG debug and parallel trace functions. The ARM Cortex-M3 is configured to support up to eight breakpoints and four watch points.

Product data sheet Rev. 5 — 9 September 2014 68 of 122

NXP Semiconductors

8. Limiting values

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 9. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

[1]

Symbol Parameter Conditions Min Max Unit

DD(3V3)

DD(REG)(3V3)

DDA

i(VBAT)

i(VREFP)

supply voltage (3.3 V) external rail 2.4 3.6 V regulator supply voltage (3.3 V) 2.4 3.6 V analog 3.3 V pad supply voltage 0.5 +4.6 V input voltage on pin VBAT for the RTC 0.5 +4.6 V input voltage on pin VREFP 0.5 +4.6 V analog input voltage on ADC related

0.5 +5.1 V

pins

input voltage 5 V tolerant digital

[2]

0.5 +5.5 V

I/O pins;

V V

other I/O pins

 2.4V

DD(3V3)

 0 V 0.5 +3.6 V

DD(3V3)

[2][3]

0.5 V

DD(3V3)

0.5

latch

supply current per supply pin - 100 mA ground current per ground pin - 100 mA I/O latch-up current (0.5V

< (1.5V

DD(3V3)

) < VI

);

- 100 mA

Tj < 125 C

stg

tot(pack)

storage temperature non-operating total power dissipation (per package) based on package

[4]

65 +150 C

-1.5W heat transfer, not device power consumption

ESD

electrostatic discharge voltage human body

[5]

-4000V model; all pins

[1] The following applies to the limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V

otherwise noted. [2] Including voltage on outputs in 3-state mode. [3] Not to exceed 4.6 V. [4] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined

based on the required shelf lifetime. Please refer to the JEDEC spec for further details.

[5] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.

Product data sheet Rev. 5 — 9 September 2014 69 of 122

unless

NXP Semiconductors

TjT

amb

PDR

th j a–

+=

9. Thermal characteristics

The average chip junction temperature, Tj (C), can be calculated using the following equation:

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

(1)

• T

• R

• P

Table 10. Thermal characteristics

= ambient temperature (C),

amb

= the package junction-to-ambient thermal resistance (C/W)

th(j-a)

= sum of internal and I/O power dissipation

= 3.0 V to 3.6 V; T

=40C to +85C unless otherwise specified;

amb

Symbol Parameter Min Typ Max Unit

j(max)

maximum junction

- - 125 C

temperature

Table 11. Thermal resistance (LQFP packages)

=40C to +85C unless otherwise specified.

amb

Symbol Conditions Thermal resistance in C/W ±15 %

LQFP208 LQFP144

ja JEDEC (4.5 in  4 in)

0 m/s 27.4 31.5 1 m/s 25.7 28.1

2.5 m/s 24.4 26 .2

Single-layer (4.5 in  3 in)

0 m/s 35.4 43.2 1 m/s 31.2 35.7

2.5 m/s 29.2 32 .8

jc - 8.8 7.8 jb - 15.4 13.8

Table 12. Thermal resistance value (TFBGA packages)

=40C to +85C unless otherwise specified.

amb

Symbol Conditions Thermal resistance in C/W ±15 %

TFBGA208 TFBGA180

ja JEDEC (4.5 in  4 in)

0 m/s 41 45.5 1 m/s 35 38.3

2.5 m/s 31 33.8

8-layer (4.5 in  3 in)

0 m/s 34.9 38 1 m/s 30.9 33.5

2.5 m/s 28 29.8

jc - 8.3 8.9 jb - 13.6 12

Product data sheet Rev. 5 — 9 September 2014 70 of 122

NXP Semiconductors

10. Static characteristics

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 13. Static characteristics

=40C to +85C, unless otherwise specified.

amb

Symbol Parameter Conditions Min Typ

Supply pins

DD(3V3)

DD(REG)(3V3)

supply voltage (3.3 V) external rail regulator supply voltage

[2]

2.4 3.3 3.6 V

(3.3 V)

DDA

analog 3.3 V pad supply

[3]

2.7 3.3 3.6 V

voltage

i(VBAT)

input voltage on pin

[4]

2.1 3.0 3.6 V

VBAT

i(VREFP)

input voltage on pin

[3]

2.7 3.3 V

VREFP

DD(REG)(3V3)

regulator supply current (3.3 V)

active mode; code

while(1){}

executed from flash; all peripherals disabled PCLK = CCLK/4

[5][6]

CCLK = 12 MHz; PLL

-7-mA

disabled

[5][7]

CCLK = 120 MHz; PLL

-51-mA

enabled

active mode; code

while(1){}

executed from flash; all peripherals enabled; PCLK = CCLK/4

BAT

CCLK = 12 MHz; PLL disabled

CCLK = 120 MHz; PLL

enabled Sleep mode Deep-sleep mode Power-down mode

battery supply current RTC running;

part powered down;

DD(REG)(3V3)

= 3.0 V;

i(VBAT)

DD(3V3)

= 0 V.

part powered;

DD(REG)(3V3)

= 3.0 V

i(VBAT)

=0 V;

= 3.3 V;

[5][6]

[5][7]

[5][8]

-5-mA

[5][9]

-550-A

[5][9]

-280-A

[10]

[11]

100 mA

1- A <10 nA

[1]

Max Unit

DDA

Product data sheet Rev. 5 — 9 September 2014 71 of 122

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 13. Static characteristics …continued

=40C to +85C, unless otherwise specified.

amb

Symbol Parameter Conditions Min Typ

Standard port pins, RESET

LOW-level input current VI= 0 V; on-chip pull-up

- 0.5 10 nA

resistor disabled

HIGH-level input current

VI=V

DD(3V3)

; on-chip

pull-down resistor

- 0.5 10 nA

disabled

OFF-state output current

VO=0V; VO=V

DD(3V3)

on-chip pull-up/down

;

- 0.5 10 nA

resistors disabled

input voltage pin configured to provide

a digital function

output voltage output active 0 - V HIGH-level input

[15][16]

0- 5.0V

[17]

0.7V

DD(3V3)

voltage

hys

LOW-level input voltage - - 0.3V hysteresis voltage 0.4 - - V HIGH-level output

voltage LOW-level output

IOH= 4 mA V

DD(3V3)



0.4

IOL=4 mA --0.4V

voltage

HIGH-level output

VOH=V

 0.4 V 4--mA

DD(3V3)

current

LOW-level output

VOL=0.4V 4--mA

current

OHS

HIGH-level short-circuit

VOH=0V

[18]

--45 mA

output current

OLS

LOW-level short-circuit

VOL=V

DD(3V3)

[18]

--50mA

output current

C-bus pins (P0[27] and P0[28])

pull-down current VI=5V 10 50 150 A pull-up current VI=0V 15 50 85 A

<5V 000A

0.7V

DD(3V3)

HIGH-level input

DD(3V3)<VI

voltage

hys

LOW-level input voltage - - 0.3V hysteresis voltage - 0.05 

LOW-level output

=3 mA --0.4V

OLS

voltage

input leakage current VI=V

=5V - 10 22 A

DD(3V3)

[19]

-24A

USB pins

OFF-state output

0V<VI<3.3V

[20]

--10 A

current

BUS

Product data sheet Rev. 5 — 9 September 2014 72 of 122

bus supply voltage

[20]

--5.25V

[1]

Max Unit

DD(3V3)

--V

DD(3V3)

--V

DD(3V3)

-V

DD(3V3)

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 13. Static characteristics

=40C to +85C, unless otherwise specified.

amb

…continued

Symbol Parameter Conditions Min Typ

differential input

(D+)  (D)

[20]

0.2--V

sensitivity voltage

differential common

includes VDI range

[20]

0.8 - 2.5 V

mode voltage range

th(rs)se

single-ended receiver

[20]

0.8 - 2.0 V switching threshold voltage

LOW-level output

RL of 1.5 k to 3.6 V

[20]

--0.18V voltage for low-/full-speed

HIGH-level output

RL of 15 k to GND

[20]

2.8 - 3.5 V voltage (driven) for low-/full-speed

trans

transceiver capacitance pin to GND

Oscillator pins (see Section 14.2

i(XTAL1)

input voltage on pin

)

[20]

--20pF

0.5 1.8 1.95 V

XTAL1

o(XTAL2)

output voltage on pin

0.5 1.8 1.95 V

XTAL2

i(RTCX1)

input voltage on pin

0.5 - 3.6 V

RTCX1

o(RTCX2)

output voltage on pin

0.5 - 3.6 V

RTCX2

[1]

Max Unit

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [2] For USB operation 3.0 V  V [3] V [4] The RTC typically fails when V [5] V [6] Boost control bits in the PBOOST register set to 0x0 (see LPC178x/7x User manual UM10470). [7] Boost control bits in the PBOOST register set to 0x3 (see LPC178x/7x User manual UM10470). [8] IRC running at 12 MHz; main oscillator and PLL disabled; PCLK = CCLK/4. [9] BOD disabled. [10] On pin VBAT; V [11] On pin VBAT; V [12] All internal pull-ups disabled. All pins configured as output and driven LOW. V [13] V [14] V [15] Including voltage on outputs in 3-state mode. [16] V [17] 3-state outputs go into 3-state mode in Deep power-down mode. [18] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [19] To V [20] 3.0 V  V

and VREFP should be tied to V

DDA

DD(REG)(3V3)

DDA i(VREFP)

DD(3V3)

= 3.3 V; T

supply voltages must be present.

DD(3V3)

amb

DD(REG)(3V3) DD(REG)(3V3)

=25C.

amb

=25C.

amb

 3.6 V.

 3.6 V. Guaranteed by design.

DD(3V3)

if the ADC and DAC are not used.

DD(3V3)

drops below 1.6 V.

i(VBAT)

=25C for all power consumption measurements.

= V = V

DD(3V3) DD(3V3)

= V = V

= 0; T

DDA

= 3.3 V; T

DDA

amb

=25C.

amb

DD(3V3)

= 3.3 V; T

amb

=25C.

Product data sheet Rev. 5 — 9 September 2014 73 of 122

NXP Semiconductors

temperature (°C)

-40 853510 60-15

002aah051

0.7

1.1

1.5

0.3

DD(REG)(3V3)

= 3.6 V

3.3 V

3.0 V

2.4 V

DD(REG)(3V3)

(mA)

temperature (°C)

-40 853510 60-15

002aah052

300

600

900

DD(REG)(3V3)

= 3.6 V

3.3 V

3.0 V

2.4 V

DD(REG)(3V3)

(μA)

10.1 Power consumption

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Conditions: BOD disabled.

Fig 9. Deep-sleep mode: Typical regulator supply current I

temperature

Conditions: BOD disabled.

Fig 10. Power-down mode: Typical regulator supply current I

temperature

DD(REG)(3V3)

versus

Product data sheet Rev. 5 — 9 September 2014 74 of 122

NXP Semiconductors

002aah074

temperature (°C)

-40 853510 60-15

0.8

1.6

0.4

1.2

2.0

BAT

(μA)

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Conditions: V

DD(REG)(3V3)

= V

DDA

= V

DD(3V3)

= 0; V

BAT

= 3.0 V.

Fig 11. Part powered off: Typical battery supply current (I

) versus temperature

BAT

Product data sheet Rev. 5 — 9 September 2014 75 of 122

NXP Semiconductors

10.2 Peripheral power consumption

The supply current per peripheral is measured a s the difference in supply current between the peripheral block enabled and the peripher al block disabled in the PCONP register. All other blocks are disabled and no code is executed. Measured on a typical sample at T

amb

48 MHz, and 120 MHz. The combined current of several peripherals running at the same time can be less than

the sum of each individual peripheral current measured separately.

Table 14. Power consumption for individual analog and digital blocks

amb

Peripheral

Timer0 - 0.01 0.06 0.15 Timer1 - 0.02 0.07 0.16 Timer2 - 0.02 0.07 0.17 Timer3 - 0.01 0.07 0.16 Timer0 + Timer1 + Timer2 + Timer3 - 0.07 0.28 0.67 UART0 - 0.05 0.19 0.45 UART1 - 0.06 0.24 0.56 UART2 - 0.05 0.2 0.47 UART3 - 0.06 0.23 0.56 USART4 - 0.07 0.27 0.66 UART0 + UART1 + UAR T 2 + UART3 +

USART4 PWM0 + PWM1 - 0.08 0.31 0.75 Motor control PWM - 0.04 0.15 0.36 I2C0 - 0 .01 0.03 0.08 I2C1 - 0 .01 0.03 0.1 I2C2 - 0 .01 0.03 0.08 I2C0 + I2C1 + I2C2 - 0.02 0.1 0.26 SSP0 - 0.03 0.1 0.26 SSP1 - 0.02 0.11 0.27 DAC - 0.3 0.31 0.33 ADC (12 MHz clock) - 1.51 1.61 1.7 CAN1 - 0.11 0.44 1.08 CAN2 - 0.1 0.4 0.98 CAN1 + CAN2 - 0.15 0.59 1.44 DMA PCLK = CCLK 1.1 4.27 10.27 QEI - 0.02 0.11 0.28 GPIO - 0.4 1.72 4.16 LCD - 0.99 3.84 9.25 I2S - 0.04 0.18 0.46

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

=25C. The peripheral clock was set to PCLK = CCLK/4 with CCLK = 12 MHz,

=25C; V

DD(REG)(3V3)

= V

DD(3V3)

= V

= 3.3 V; PCLK = CCLK/4.

DDA

Conditions Typical supply current in mA

12 MHz

[1]

48 MHz

[1]

- 0.29 1.13 2.74

120 MHz

[2]

Product data sheet Rev. 5 — 9 September 2014 76 of 122

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 14. Power consumption for individual analog and digital blocks

=25C; V

amb

Peripheral

DD(REG)(3V3)

= V

DD(3V3)

= V

= 3.3 V; PCLK = CCLK/4.

DDA

Conditions Typical supply current in mA

…continued

12 MHz

[1]

48 MHz

[1]

120 MHz

EMC - 0.82 3.17 7.63 RTC - 0.01 0.01 0.05 USB + PLL1 - 0.62 0.97 1.67 Ethernet PCENET bit set

0.54 2.08 5.03 to 1 in the PCONP register

[1] Boost control bits in the PBOOST register set to 0x0 (see LPC178x/7x User manual UM10470). [2] Boost control bits in the PBOOST register set to 0x3 (see LPC178x/7x User manual UM10470).

[2]

Product data sheet Rev. 5 — 9 September 2014 77 of 122

NXP Semiconductors

IOH (mA)

0 24168

002aaf112

2.8

2.4

3.2

3.6

(V)

2.0

T = 85 °C

25 °C

−40 °C

VOL (V)

0 0.60.40.2

002aaf111

(mA)

T = 85 °C

25 °C

−40 °C

10.3 Electrical pin characteristics

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Conditions: V

DD(REG)(3V3)

= V

= 3.3 V; standard port pins.

DD(3V3)

Fig 12. Typical HIGH-level output voltage VOH versus HIGH-level output source current

Conditions: V

DD(REG)(3V3)

Fig 13. Typical LOW-level ou tput current IOL versus LOW-level output voltage V

= V

= 3.3 V; standard port pins.

DD(3V3)

Product data sheet Rev. 5 — 9 September 2014 78 of 122

NXP Semiconductors

0 54231

002aaf108

−30

−50

−10

(μA)

−70

T = 85 °C

25 °C

−40 °C

VI (V)

002aaf109

VI (V)

0 53241

(μA)

−10

T = 85 °C

25 °C

−40 °C

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Conditions: V

DD(REG)(3V3)

= V

= 3.3 V; standard port pins.

DD(3V3)

Fig 14. Typical pull-up current Ipu versus input voltage V

Conditions: V

DD(REG)(3V3)

= V

= 3.3 V; standard port pins.

DD(3V3)

Fig 15. Typical pull-down current Ipd versus input voltage V

Product data sheet Rev. 5 — 9 September 2014 79 of 122

NXP Semiconductors

11. Dynamic characteristics

11.1 Flash memory

Table 15. Flash characteristics

=40C to +85C, unless otherwise specified.

amb

Symbol Parameter Conditions Min Typ Max Unit

endu

ret

prog

[1] Number of program/erase cycles. [2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash

in blocks of 256 bytes.

endurance retention time powered 10 - - years

erase time sector or multiple

programming time

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

[1]

10000 100000 - cycles

unpowered 20 - - years

95 100 105 ms

consecutive sectors

[2]

0.95 1 1.05 ms

Table 16. EEPROM characteristics

=40Cto+85C; V

amb

DD(REG)(3V3)

= 2.7 V to 3.6 V.

Symbol Parameter Conditions Min Typ Max Unit

f N t

clk

endu

ret

clock frequency - 200 375 400 kHz endurance - 100000 500000 - cycles retention time powered 10 - - years

unpowered 10 - - years

prog

erase time 64 bytes programming

64 bytes

[1]

-1.8-ms

[1]

-1.1-ms

time

[1] EEPROM clock frequency = 375 kHz. Programming/erase times increase with decreasing EEPROM clock

frequency.

Product data sheet Rev. 5 — 9 September 2014 80 of 122

NXP Semiconductors

1 1.2 External memory interface

[1]

[2]

= 3.0 V to 3.6 V. Values guaranteed by design.

DD(3V3)

Conditions

[1]

Min Typ Max Unit

2.7 3.5 4.7 ns

[3]

2.7 + T

cy(clk)



WAITOEN

RD3; PB = 1

[3]

2.8 3.8 5.1 ns

[3]

(WAITRD  WAITOEN + 1) 

 2.26

cy(clk)

[3]

[4]

(WAITRD  WAITOEN + 1)  T

 8.6

cy(clk)

[3]

[5]

4.1 5.8 - ns

PB = 1 2.8 3.7 5.1 ns

[3]

2.7 3.5 4.6 ns

[3]

0.1 0.1 0.16 ns

[3]

WR3; PB =1

- 3.4 4.7 ns

2.7 3.5 4.7 ns

2.8 3.9 5.1 ns

[3]

2.7 + T

cy(clk)



(1 + WAITWEN)

WR4; PB = 1

WR5; PB =1

[3]

2.8 3.9 5.1 ns

[3]

(WAITWR  WAITWEN + 1) 

 2.3

cy(clk)

PB = 1

[3]

(WAITWR  WAITWEN + 3)  T

 2.6

cy(clk)

WR6; PB =1

WR7; PB = 1

[3]

[3][6]

2.5 + T

cy(clk)

 2.7 T

cy(clk)

PB = 1 2.7 3.6 4.8 ns

PB = 1

[3]

2.4 + T

cy(clk)

Table 17. Dynamic characteristics: Static external memory interface

CL=30pF, T

=40C to 85C, V

amb

Symbol Parameter

Read cycle parameters

CSLAV

CS LOW to address valid time

CSLOEL

CS LOW to OE LOW time

CSLBLSL

CS LOW to BLS LOW time

OELOEH

OE LOW to OE HIGH time

h(D)

CSHBLSH

memory access time RD

data input hold time RD CS HIGH to BLS HIGH

time

CSHOEH

CS HIGH to OE HIGH time

OEHANV

OE HIGH to address invalid time

deact

deactivation time RD

Write cycle parameters

CSLAV

CS LOW to address valid time

CSLDV

CS LOW to data valid time

CSLWEL

CS LOW to WE LOW time

CSLBLSL

CS LOW to BLS LOW time

WELWEH

WE LOW to WE HIGH time

BLSLBLSH

BLS LOW to BLS HIGH time

WEHDNV

WE HIGH to data invalid time

WEHEOW

WE HIGH to end of write time

BLSHDNV

BLS HIGH to data invalid time

WEHANV

WE HIGH to address invalid time

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

3.4 + T WAITOEN

(WAITRD  WAITOEN + 1)  T

cy(clk)

(WAITRD  WAITOEN + 1)  T

cy(clk)

3.5 + T (1 + WAITWEN)

(WAITWR  WAITWEN + 1)  T

cy(clk)

(WAITWR  WAITWEN + 3)  T

cy(clk)

3.3 + T

cy(clk)

3.0 + T



cy(clk)

 2.83

 11.9



cy(clk)

 2.8

 3.4

cy(clk)

 3.4 T

cy(clk)

4.6 + T

cy(clk)



WAITOEN

(WAITRD  WAITOEN + 1)  T

 3.7

cy(clk)

(WAITRD  WAITOEN + 1)  T

 18.0

cy(clk)

4.6 + T

cy(clk)



(1 + WAITWEN)

(WAITWR  WAITWEN + 1)  T

 3.8

cy(clk)

(WAITWR  WAITWEN + 3)  T

 4.9

cy(clk)

4.3 + T

cy(clk)

 4.6 ns

cy(clk)

3.9 + T

cy(clk)

Product data sheet Rev. 5 — 9 September 2014 81 of 122

NXP Semiconductors

EOR

EOW

EMC_Ax

EMC_CSx

EMC_OE

EMC_BLSx

EMC_WE

EMC_Dx

002aag214

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 17. Dynamic characteristics: Static external memory interface

CL=30pF, T

Symbol Parameter

deact

=40C to 85C, V

amb

[1]

Conditions

= 3.0 V to 3.6 V. Values guaranteed by design.

DD(3V3)

[1]

deactivation time WR8; PB = 0;

Min Typ Max Unit

[3]

2.7 3.4 4.7 ns

…continued

PB = 1

CSLBLSL

BLSLBLSH

BLSHEOW

CS LOW to BLS LOW WR9; PB = 0

BLS LOW to BLS HIGH

WR10; PB = 0

time

BLS HIGH to end of

WR11; PB = 0

[3]

2.8 + T (1 + WAITWEN)

[3]

(WAITWR  WAITWEN + 3)  T

cy(clk)

[3][6]

2.6 + T

cy(clk)

 2.6

cy(clk)



3.7 + T (1 + WAITWEN)

(WAITWR  WAITWEN + 3)  T

cy(clk)

3.3 + T

write time

BLSHDNV

BLS HIGH to data invalid time

WR12; PB = 0

[1] Parameters are shown as RDn or WDn in Figure 16 as indicated in the Conditions column. [2] Parameters specified for 40 % of V [3] T

= 1/EMC_CLK (see LPC178x/7x User manual UM10470).

cy(clk)

[4] Latest of address valid, EMC_CSx

for rising edges and 60 % of V

DD(3V3)

LOW, EMC_OE LOW, EMC_BLSx LOW (PB = 1). [5] After End Of Read (EOR): Earliest of EMC_CSx [6] End Of Write (EOW): Earliest of address invalid, EMC_CSx

[3]

2.7 + T

cy(clk)

DD(3V3)

3.6 + T

for falling edges.

HIGH, EMC_OE HIGH, EMC_BLSx HIGH (PB = 1), address invalid.

HIGH, EMC_BLSx HIGH (PB = 1).

cy(clk)

 3.4

cy(clk)



5.1 + T

cy(clk)



(1 + WAITWEN) (WAITWR 

WAITWEN + 3)  T

 4.9

cy(clk)

4.4 + T

cy(clk)

4.8 + T

cy(clk)

Fig 16. External static memory read/write access (PB = 0)

Product data sheet Rev. 5 — 9 September 2014 82 of 122

NXP Semiconductors

EMC_Ax

EMC_CSx

EMC_OE

EMC_BLSx

EMC_WE

EMC_Dx

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

WR3WR

Fig 17. External static memory read/write access (PB =1)

EMC_Ax

EMC_CSx

EMC_OE

EMC_BLSx

EMC_WE

EMC_Dx

Fig 18. External static memory burst read cycle

EOR

EOW

002aag215

002aag216

Product data sheet Rev. 5 — 9 September 2014 83 of 122

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 18. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 00

CL=30pF, T

=40C to 85C, V

amb

= 3.0 V to 3.6 V. Values guaranteed by design.

DD(3V3)

Symbol Parameter Min Typ Max Unit

Common to read and write cycles

cy(clk)

d(SV)

h(S)

d(RASV)

h(RAS)

d(CASV)

h(CAS)

d(WV)

h(W)

d(AV)

h(A)

clock cycle time chip select valid delay time

chip select hold time

row address strobe valid delay time

row address strobe hold time

column address strobe valid delay time

column address strobe hold time

write valid delay time

write hold time

address valid delay time

address hold time

[1]

12.5 - - ns

[2]

(CLKDLY + 1) 

0.25 + 4.1

[2]

(CLKDLY + 1) 

0.25 + 0.5

[2]

(CLKDLY + 1) 

0.25 + 4.2

[2]

(CLKDLY + 1) 

0.25 + 0.6

[2]

(CLKDLY + 1) 

0.25 + 4.2

[2]

(CLKDLY + 1) 

0.25 + 0.6

[2]

(CLKDLY + 1) 

0.25 + 4.9

[2]

(CLKDLY + 1) 

0.25 + 0.9

[2]

(CLKDLY + 1) 

0.25 + 4.7

[2]

(CLKDLY + 1) 

0.25 + 0.4

(CLKDLY + 1) 

0.25 + 5.7 (CLKDLY + 1) 

0.25 + 1.1 (CLKDLY + 1) 

0.25 + 5.8 (CLKDLY + 1) 

0.25 + 1.2 (CLKDLY + 1) 

0.25 + 5.8 (CLKDLY + 1) 

0.25 + 1.2 (CLKDLY + 1) 

0.25 + 6.6 (CLKDLY + 1) 

0.25 + 1.7 (CLKDLY + 1) 

0.25 + 6.6 (CLKDLY + 1) 

0.25 + 0.8

(CLKDLY + 1) 

0.25 + 8.4 (CLKDLY + 1) 

0.25 + 2.7 (CLKDLY + 1) 

0.25 + 8.4 (CLKDLY + 1) 

0.25 + 2.9 (CLKDLY + 1) 

0.25 + 8.4 (CLKDLY + 1) 

0.25 + 2.9 (CLKDLY + 1) 

0.25 + 9.9 (CLKDLY + 1) 

0.25 + 3.6 (CLKDLY + 1) 

0.25 + 9.6 (CLKDLY + 1) 

0.25 + 2.4

Read cycle parameters

su(D)

h(D)

data input set-up time

data input hold time

[3]

(FBCLKDL Y + 1) 

0.25 + 0.3

[4]

(FBCLKDL Y + 1) 

0.25 + 3.7

(FBCLKDL Y + 1) 

0.25 + 3.1 (FBCLKDL Y + 1) 

0.25 + 4.3

-ns

(FBCLKDL Y + 1) 

0.25 + 5.2

Write cycle parameters

d(QV)

h(Q)

data output valid delay time

data output hold time

[2]

(CLKDLY + 1) 

0.25 + 4.8

[2]

(CLKDLY + 1) 

0.25  0.4

(CLKDLY + 1) 

0.25 + 6.8 (CLKDLY + 1) 

0.25 + 0

(CLKDLY + 1) 

0.25 + 9.8 (CLKDLY + 1) 

0.25 + 1.1

[1] Refers to SDRAM clock signal EMC_CLKx. [2] CLKDLY = CLKOUTnDLY, where n = 0, 1. [3] The data input set-up time has to be selected with the following margin:

+ delay time of feedback clock  SDRAM access time  board delay time  0.

su(D)

[4] The data input hold time has to be selected with the following margin:

+ SDRAM access time  board delay time  delay time of feedback clock  0.

h(D)

Product data sheet Rev. 5 — 9 September 2014 84 of 122

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 19. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 01

CL=30pF, T

=40C to 85C, V

amb

= 3.0 V to 3.6 V. Values guaranteed by design.

DD(3V3)

Symbol Parameter Min Typ Max Unit

Common to read and write cycles

cy(clk)

d(SV)

h(S)

d(RASV)

h(RAS)

d(CASV)

h(CAS)

d(WV)

h(W)

d(AV)

h(A)

clock cycle time chip select valid delay time (CMDDLY + 1) 

chip select hold time (CMDDLY + 1) 

row address strobe valid delay time

row address strobe hold time

column address strobe valid delay time

column address strobe hold time

write valid delay time (CMDDLY + 1) 

write hold time (CMDDLY + 1) 

address valid delay time (CMDDLY + 1) 

address hold time (CMDDLY + 1) 

[1]

12.5 - - ns

0.25 + 4.6

0.25 + 0.9 (CMDDLY + 1) 

0.25 + 4.6 (CMDDLY + 1) 

0.25 + 1.0 (CMDDLY + 1) 

0.25 + 4.6 (CMDDLY + 1) 

0.25 + 1.0

0.25 + 5.1

0.25 + 1.4

0.25 + 5.1

0.25 + 0.8

(CMDDLY + 1) 

0.25 + 6.4 (CMDDLY + 1) 

0.25 + 1.7 (CMDDLY + 1) 

0.25 + 6.4 (CMDDLY + 1) 

0.25 + 1.8 (CMDDLY + 1) 

0.25 + 6.5 (CMDDLY + 1) 

0.25 + 1.8 (CMDDLY + 1) 

0.25 + 7.1 (CMDDLY + 1) 

0.25 + 2.4 (CMDDLY + 1) 

0.25 + 7.2 (CMDDLY + 1) 

0.25 + 1.5

(CMDDLY + 1) 

0.25 + 9.5 (CMDDLY + 1) 

0.25 + 3.9 (CMDDLY + 1) 

0.25 + 9.5 (CMDDLY + 1) 

0.25 + 4.0 (CMDDLY + 1) 

0.25 + 9.6 (CMDDLY + 1) 

0.25 + 4.1 (CMDDLY + 1) 

0.25 + 10.6 (CMDDLY + 1) 

0.25 + 4.9 (CMDDLY + 1) 

0.25 + 10.6 (CMDDLY + 1) 

0.25 + 3.6

Read cycle parameters

su(D)

h(D)

data input set-up time

data input hold time

[2]

(FBCLKDL Y + 1) 

0.25 + 0.9

[3]

(FBCLKDLY + 1) 

0.25 + 3.7

(FBCLKDLY + 1) 

0.25 + 3.1 (FBCLKDLY + 1) 

0.25 + 4.3

-ns

(FBCLKDLY + 1) 

0.25 + 5.2

Write cycle parameters

d(QV)

h(Q)

data output valid delay time (CMDDLY + 1) 

0.25 + 5.1

data output hold time (CMDDL Y + 1) 

0.25 + 0.02

(CMDDLY + 1) 

0.25 + 7.4 (CMDDLY + 1) 

0.25 + 0.6

(CMDDLY + 1) 

0.25 + 10.8 (CMDDLY + 1) 

0.25 + 2.3

[1] Refers to SDRAM clock signal EMC_CLKx. [2] The data input set-up time has to be selected with the following margin:

+ delay time of feedback clock  SDRAM access time  board delay time  0.

su(D)

[3] The data input hold time has to be selected with the following margin:

+ SDRAM access time - board delay time - delay time of feedback clock  0.

h(D)

Product data sheet Rev. 5 — 9 September 2014 85 of 122

NXP Semiconductors

002aah129

cy(clk)

EMC_CLKn

delay = 0

EMC_DYCSn,

EMC_RAS, EMC_CAS,

EMC_WE,

EMC_CKEOUTn,

EMC_A[22:0],

EMC_DQMOUTn

h(Q)

h(D)

su(D)

EMC_D[31:0] write

EMC_D[31:0] read

d(QV)

h(x)

d(xV)

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Fig 19. Dynamic external memory interface signal timing

Table 20. Dynamic characteristics: Dynamic external memory interface programmable

clock delays

CL=30pF, T

=40C to 85C, V

amb

Symbol Parameter Conditions Min Max Unit

delay time Programmable delay block 0 (CMDDLY

or CLKOUTnDLY bit 0 = 1) Programmable delay block 1 (CMDDLY

or CLKOUTnDLY bit 1 = 1) Programmable delay block 2 (CMDDLY

or CLKOUTnDLY bit 2 = 1) Programmable delay block 3 (CMDDLY

or CLKOUTnDLY bit 3 = 1) Programmable delay block 4 (CMDDLY

or CLKOUTnDLY bit 4 = 1)

[1] The programmable delay blocks are controlled by the EMCDLYCTL register in the EMC register block. All

delay times are incremental delays for each element starting from delay block 0. See the LPC178x/7x user

manual for details.

= 3.0 V to 3.6 V.Values guaranteed by design.

DD(3V3)

[1]

0.1 0.2 ns

[1]

0.2 0.5 ns

[1]

0.5 1.3 ns

[1]

1.2 2.9 ns

[1]

2.4 6.0 ns

Product data sheet Rev. 5 — 9 September 2014 86 of 122

NXP Semiconductors

CHCL

CLCX

CHCX

cy(clk)

CLCH

002aaa907

1 1.3 External clock

Table 21. Dynamic characteristic: external clock (see Figure 36)

amb

Symbol Parameter Min Typ Max Unit

osc

cy(clk)

CHCX

CLCX

CLCH

CHCL

=40C to +85C; V

oscillator frequency 1 12 25 MHz clock cycle time 40 83.3 1000 ns clock HIGH time T clock LOW time T clock rise time - - 5 ns clock fall time - - 5 ns

over specified ranges.

DD(3V3)

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

 0.4 - - ns

cy(clk)

 0.4 - - ns

cy(clk)

Fig 20. External clock timing (with an amplitude of at least V

1 1.4 Internal oscillators

Table 22. Dynamic characteristic: internal oscillators

=40C to +85C; 2.7 V  V

amb

Symbol Parameter Min Typ

osc(RC)

i(RTC)

[1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

internal RC oscillator frequency 11.88 12 12.12 MH z RTC input frequency - 32.768 - kHz

1 1 .5 I/O pins

Table 23. Dynamic characteristic: I/O pins

CL=10pF, T

Symbol Parameter Conditions Min Typ Max Unit

=40C to +85C; V

amb

rise time pin configured as

fall time pin configured as

DD(REG)(3V3)

DD(3V3)

output

 3.6 V.

[1]

= 3.0 V to 3.6 V.

3.0 - 5.0 ns

2.5 - 5.0 ns

i(RMS)

= 200 mV)

[2]

Max Unit

[1] Applies to standard port pins.

Product data sheet Rev. 5 — 9 September 2014 87 of 122

NXP Semiconductors

1 1.6 SSP interface

Table 24. Dynamic characteristics: SSP pins in SPI mode

CL=10pF, T

Symbol Parameter Conditions Min Max Unit

SSP master

cy(clk)

v(Q)

h(Q)

SSP slave

cy(clk)

v(Q)

h(Q)

[1] The minimum clock cycle time, and therefore the maximum frequency of the SSP in master mode, is limited

[2] T [3] T [4] T

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

=40C to 85C, V

amb

clock cycle time full-duplex

data set-up time in SPI mode data hold time in SPI mode data output valid time in SPI mode data output hold time in SPI mode

clock cycle time data set-up time in SPI mode data hold time in SPI mode data output valid time in SPI mode data output hold time in SPI mode

by the pin electronics to the value given. The SSP block should not be configured to generate a clock faster than that. At and below the maximum frequency, T 5The clock cycle time derived from the SPI bit rate T SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0 register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register).

= 40 C to 85 C; V

amb

= 12  T

cy(clk)

= 25 C; V

amb

cy(PCLK)

DD(3V3)

. The maximum clock rate in slave mode is 1/12th of the PCLK rate.

= 3.3 V.

= 3.0 V to 3.6 V.

DD(3V3)

= 3.0 V to 3.6 V. Values guaranteed by design.

DD(3V3)

mode when only

transmitting

[1]

30 - ns

[2]

14.8 - ns

[2]

2- ns

[2]

-6.3ns

[2]

2.4 - ns

[3]

100 - ns

[3][4]

14.8 - ns

[3][4]

2- ns

[3][4]

-6.3ns

[3][4]

2.4 - ns

= (SSPCLKDIV  (1 + SCR)  CPSDVSR) / f

cy(clk)

is a function of the main clock frequency f

cy(clk)

main

, the

Product data sheet Rev. 5 — 9 September 2014 88 of 122

NXP Semiconductors

SCK (CPOL = 0)

MOSI

MISO

cy(clk)

v(Q)

DATA VA L ID DATA VA LID

h(Q)

SCK (CPOL = 1)

DATA VALID

MOSI

MISO

DATA VA L ID DATA VA LID

h(Q)

DATA VALID

v(Q)

CPHA = 1

CPHA = 0

002aae829

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Fig 21. SSP master timing in SPI mode

SCK (CPOL = 0)

SCK (CPOL = 1)

MOSI

MISO

MOSI

MISO

DATA VALID

DATA VA L ID DATA VA LID

cy(clk)

DATA VALID

v(Q)

DATA VA L ID DATA VA LID

v(Q)

DATA VALID

h(Q)

CPHA = 1

CPHA = 0

002aae830

Product data sheet Rev. 5 — 9 September 2014 89 of 122

Fig 22. SSP slave timing in SPI mode

NXP Semiconductors

11.7 I2C-bus

Table 25. Dynamic characteristic: I2C-bus pins

amb

Symbol Parameter Conditions Min Max Unit

SCL

LOW

HIGH

HD;DAT

SU;DAT

=40C to +85C.

SCL clock frequency

fall time

LOW period of the SCL clock

HIGH period of the SCL clock

data hold time

data set-up time

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

[1]

[2]

Standard-mode 0 100 kHz Fast-mode 0 400 kHz Fast-mode Plus 0 1 MHz

[4][5][6][7]

[3][4][8]

[9][10]

of both SDA and

- 300 ns

SCL signals

Standard-mode Fast-mode 20 + 0.1  C

300 ns

Fast-mode Plus - 120 ns Standard-mode 4.7 - s Fast-mode 1.3 - s Fast-mode Plus 0.5 - s Standard-mode 4.0 - s Fast-mode 0.6 - s Fast-mode Plus 0.26 - s Standard-mode 0 - s Fast-mode 0 - s Fast-mode Plus 0 - s Standard-mode 250 - ns Fast-mode 100 - ns Fast-mode Plus 50 - ns

[1] See the I2C-bus specification UM10204 for details. [2] Parameters are valid over operating temperature range unless otherwise specified. [3] tHD;DA T is the data hold time that is measured from the falling edge of SCL; applies to data in transmission

and the acknowledge.

[4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the

(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.

= total capacitance of one bus line in pF.

[5] C

[6] The maximum t

output stage t SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified t

[7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors

are used, designers should allow for this when considering bus timing.

[8] The maximum t

the maximum of t the device does not stretch the LOW period (t data must be valid by the set-up time before it releases the clock.

[9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in

transmission and the acknowledge.

[10] A Fast-mode I

250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.

Product data sheet Rev. 5 — 9 September 2014 90 of 122

for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA

is specified at 250 ns. This allows series protection resistors to be connected in between the

could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than

HD;DAT

or t

VD;DAT

C-bus device can be used in a Standard-mode I2C-bus system but the requirement t

r(max)

by a transition time (see UM10204). This maximum must only be met if

VD;ACK

+ t

= 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus

SU;DAT

) of the SCL signal. If the clock stretches the SCL, the

LOW

SU;DAT

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

70 %

SDA

30 %

SCL

70 %

30 %

1 / f

SCL

Fig 23. I2C-bus pins clock timing

11.8 I2S-bus interface

Table 26. Dynamic characteristics: I2S-bus interface pins

CL=10pF, T

Symbol Parameter Conditions Min Max Unit

common to input and output

SU;DAT

70 % 30 %

HD;DAT

70 %

30 %

=40C to 85C, V

amb

70 %

30 %

HIGH

LOW

= 3.0 V to 3.6 V. Values guaranteed by design.

DD(3V3)

70 %

30 %

VD;DAT

rise time fall time pulse width HIGH on pins I2S_TX_SCK and

I2S_RX_SCK

pulse width LOW on pins I2S_TX_SCK and

I2S_RX_SCK

002aaf425

[1]

-6.7ns

[1]

-8.0ns

[1]

25 - -

[1]

-25ns

output

v(Q)

data output valid time on pin I2S_TX_SDA;

[1]

-6ns

input

su(D)

h(D)

[1] CCLK = 100 MHz; peripheral clock to the I2S-bus interface PCLK = CCLK / 4. I2S clock cycle time T

1600 ns, corresponds to the SCK signal in the I

data input set-up time on pin I2S_RX_SDA data input hold time on pin I2S_RX_SDA

S-bus specification.

Product data sheet Rev. 5 — 9 September 2014 91 of 122

[1]

5- ns

[1]

2- ns

cy(clk)

NXP Semiconductors

002aag203

cy(clk)

su(D)

h(D)

su(D)

I2S_RX_SCK

I2S_RX_SDA

I2S_RX_WS

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

I2S_TX_SCK

I2S_TX_SDA

I2S_TX_WS

Fig 24. I2S-bus timing (transmit)

cy(clk)

v(Q)

002aag202

Fig 25. I

S-bus timing (receive)

11.9 LCD

Remark: The LCD controller is available on parts LPC1788/87/86/85.

Table 27. Dynamic characteristics: LCD

CL=10pF, T

Symbol Parameter Conditions Min Max Unit

clk

d(QV)

h(Q)

Product data sheet Rev. 5 — 9 September 2014 92 of 122

=40C to 85C, V

amb

= 3.0 V to 3.6 V. Values guaranteed by design.

DD(3V3)

clock frequency on pin LCD_DCLK - 50 MHz data output valid delay time - 12 ns data output hold time 0.5 - ns

NXP Semiconductors

002aag204

SD_CLK

SD_DATn (O)

SD_DATn (I)

d(QV)

h(D)

su(D)

cy(clk)

h(Q)

SD_CMD (O)

SD_CMD (I)

Fig 26. LCD timing

11.10 SD/MMC

Remark: The SD/MMC card interface is available on parts LPC1788/87/86 and parts

LPC1778/77/76.

Table 28. Dynamic characteristics: SD/MMC

=10pF, T

Symbol Parameter Conditions Min Max Unit

clk

su(D)

h(D)

d(QV)

h(Q)

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

cy(clk)

LCD_DCLK

d(QV)

LCD_VD[n]

The LCD panel clock is shown with the default polarity. The clock can be inverted via the IPC bit in the LCD_POL register. T ypically, the LCD panel uses the falling edge of the LCD_DCLK to sample the data.

=40C to 85C, V

amb

= 3.0 V to 3.6 V. Values guaranteed by design.

DD(3V3)

clock frequency on pin SD_CLK; data transfer mode - 25 MHz

on pin SD_CLK; identification mode 25 MHz

data input set-up time on pins SD_CMD, SD_DAT[3:0] as

inputs

data input hold time on pins SD_CMD, SD_DAT[3:0] as

inputs

data output valid delay time

on pins SD_CMD, SD_DAT [3:0] as outputs

data output hold time on pins SD_CMD, SD_DAT[3:0] as

outputs

h(Q)

002aah325

6- ns

-23ns

3.5 - ns

Fig 27. SD/MMC timing

Product data sheet Rev. 5 — 9 September 2014 93 of 122

NXP Semiconductors

12. ADC electrical characteristics

Table 29. 12-bit ADC characteristics

= 2.7 V to 3.6 V; T

DDA

Symbol Parameter Conditions Min Typ Max Unit

analog input voltage 0 - V

12-bit resolution

differential linearity error

L(adj)

clk(ADC)

c(ADC)

integral non-linearity offset error gain error absolute error ADC clock frequency - - 12.4 MHz ADC conversion

frequency

analog input capacitance

vsi

voltage source interface resistance

8-bit resolution

[10]

differential linearity error

L(adj)

clk(ADC)

c(ADC)

integral non-linearity offset error gain error absolute error ADC clock frequency - - 36 MHz ADC conversion

frequency

analog input capacitance

vsi

voltage source interface resistance

=40C to +85C unless otherwise specified.

amb

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

[1]

DDA

[2][3][4]

--1LSB

[2][5]

--6LSB

[2][6]

--5LSB

[2][7]

--5LSB

[2][8]

--<8LSB

single conversion

--400kSa

mode

burst mode - - 375 kSa

--5pF

[9]

--1k

[2][3][4]

- 1- LSB

[2][5]

- 1- LSB

[2][6]

- 1- LSB

[2][7]

- 1- LSB

[2][8]

--<1.5 LSB

--1.16Msa

--5pF

[9]

--1k

mple s/s

mple/ s

[1] V [2] Conditions: V [3] The ADC is monotonic, there are no missing codes. [4] The differential linearity error (E

[5] The integral non-linearity (E

Product data sheet Rev. 5 — 9 September 2014 94 of 122

and VREFP should be tied to V

DDA

=0V, V

SSA

See Figure 28

the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 28

=3.3V.

DDA

) is the difference between the actual step width and the ideal step width.

) is the peak difference between the center of the steps of the actual and

L(adj)

if the ADC and DAC are not used.

DD(3V3)

NXP Semiconductors

[6] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the

[7] The gain error (E

[8] The absolute error (E

[9] See Figure 29 [10] 8-bit resolution is achieved by ignoring the lower four bits of the ADC conversion result.

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

straight line which fits the ideal curve. See Figure 28

) is the relative difference in percent between the straight line fitting the actual transfer

curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 28

curve of the non-calibrated ADC and the ideal transfer curve. See Figure 28

) is the maximum difference between the center of the steps of the actual transfer

Product data sheet Rev. 5 — 9 September 2014 95 of 122

NXP Semiconductors

002aaf436

4095

4094

4093

4092

4091

(2)

(1)

40964090 4091 4092 4093 4094 4095

7123456

4090

(5)

(4)

(3)

1 LSB (ideal)

code

out

VREFP - V

4096

offset

error

gain error

offset error

VIA (LSB

ideal

)

1 LSB =

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

(1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E

L(adj)

(5) Center of a step of the actual transfer curve.

Fig 28. 12-bit ADC characteristics

Product data sheet Rev. 5 — 9 September 2014 96 of 122

NXP Semiconductors

LPC178x/7x

AD0[n]

110 fF

80 fF

1.6 pF

vsi

500 Ω - 2 kΩ

cmp

90 Ω - 300 Ω

EXT

002aag613

ADC

COMPARATOR

BLOCK

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

The values of resistor components R process-dependent.

Fig 29. ADC interface to pins ADC0_IN[n]

Table 30. ADC interface components

Component Range Description

cmp

90  to 300  Switch-on resistance for the comparator input switch. Varies

500  to 2 k Switch-on resistance for channel selection switch. Varies with

C1 110 fF Parasitic capacitance from the ADC block level. C2 80 fF Parasitic capacitance from the ADC block level. C3 1.6 pF Sampling capacitor.

13. DAC electrical characteristics

Table 31. 10-bit DAC electrical characteristics

= 2.7 V to 3.6 V; T

DDA

Symbol Parameter Min Typ Max Unit

E E E E C R

D L(adj) O G L L

differential linearity error - 1- LSB integral non-linearity - 1.5 - LSB offset error - 0.6 - % gain error - 0.6 - % load capacitance - - 200 pF load resistance 1 - - k

=40C to +85C unless otherwise specified

amb

and Rsw vary with temperature and input voltage and are

cmp

with temperature, input voltage, and process.

temperature, input voltage, and process.

Product data sheet Rev. 5 — 9 September 2014 97 of 122

NXP Semiconductors

LPC17xx

USB-B connector

USB_D+

USB_CONNECT

SoftConnect switch

USB_D−

BUS

DD(3V3)

1.5 kΩ

RS = 33 Ω

002aad939

RS = 33 Ω

USB_UP_LED

LPC17xx

DD(3V3)

1.5 kΩ

USB_UP_LED

002aad940

USB-B connector

USB_D+ USB_D−

BUS

RS = 33 Ω RS = 33 Ω

14. Application information

14.1 Suggested USB interface solutions

Remark: The USB controller is available as a device/Host/OTG controller on parts

LPC1788/87/86/85 and LPC1778/77/76 and as device-only controller on parts LPC1774.

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Fig 30. USB interface on a self-powered device

Fig 31. USB interface on a bus-powered device

Product data sheet Rev. 5 — 9 September 2014 98 of 122

NXP Semiconductors

RSTOUT

USB_SCL1

USB_SDA1

USB_INT1

USB_D+1

USB_D-1

USB_UP_LED1

R1 R2 R3 R4

R4 R5 R6

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

BUS

SSCORE

33 Ω

SSIO,

Mini-AB connector

OE_N/INT_N

SUSPEND

RESET_N

ADR/PSW

SPEED

ISP1302

SCL

SDA

INT_N

LPC178x/7x

USB_PPWR2

5 V

ENA

LM3526-L

OUTA

FLAGA

USB_OVRCR2

USB_PWRD2

USB_D+2

USB_D-2

USB_UP_LED2

33 Ω

15 kΩ 15 kΩ

Fig 32. USB OTG port configuration: port 1 OTG dual-role device, port 2 host

SSCORE

SSIO,

BUS

D+

USB-A connector

D-

002aag506

Product data sheet Rev. 5 — 9 September 2014 99 of 122

NXP Semiconductors

USB_TX_DP1

USB_TX_DM1

USB_RCV1

USB_RX_DP1

USB_RX_DM1

USB_SCL1

USB_SDA1

SPEED

ADR/PSW

SDA

SCL

RESET_N

INT_N

SUSPEND

OE_N/INT_N

SE0_VM

DAT_VP

RCV

BUS

LPC178x/7x

ISP1302

USB MINI-AB connector

33 Ω

002aag507

USB_TX_E1

RSTOUT

USB_INT1

USB_UP_LED1

SSIO,

SSCORE

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Fig 33. USB OTG port configuration: VP_VM mode

Product data sheet Rev. 5 — 9 September 2014 100 of 122

NXP LPC178x, LPC177x User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1. General description

2. Features and benefits

3. Applications

4. Ordering information

5. Block diagram

6. Pinning information

6.1 Pinning

6.2 Pin description

7. Functional description

7.1 Architectural overview

7.2 ARM Cortex-M3 processor

7.3 On-chip flash program memory

7.4 EEPROM

7.5 On-chip SRAM

7.6 Memory Protection Unit (MPU)

7.7 Memory map

7.8 Nested Vectored Interrupt Controller (NVIC)

7.8.1 Features

7.8.2 Interrupt sources

7.9 Pin connect block

7.10 External memory controller

7.10.1 Features

7.11 General purpose DMA controller

7.11.1 Features

7.12 CRC engine

7.12.1 Features

7.13 LCD controller

7.13.1 Features

7.14 Ethernet

7.14.1 Features

7.15 USB interface

7.15.1 USB device controller

7.15.1.1 Features

7.15.2 USB host controller

7.15.2.1 Features

7.15.3 USB OTG controller

7.15.3.1 Features

7.16 SD/MMC card interface

7.16.1 Features

7.17 Fast general purpose parallel I/O

7.17.1 Features

7.18 12-bit ADC

7.18.1 Features

7.19 10-bit DAC

7.19.1 Features

7.20 UARTs

7.20.1 Features

7.21 SSP serial I/O controller

7.21.1 Features

7.22 I2C-bus serial I/O controllers

7.22.1 Features

7.23 I2S-bus serial I/O controllers

7.23.1 Features

7.24 CAN controller and acceptance filters

7.24.1 Features

7.25 General purpose 32-bit timers/external event counters

7.25.1 Features

7.26 Pulse Width Modulator (PWM)

7.26.1 Features

7.27 Motor control PWM

7.28 Quadrature Encoder Interface (QEI)

7.28.1 Features

7.29 ARM Cortex-M3 system tick timer

7.30 Windowed WatchDog Timer (WWDT)

7.30.1 Features

7.31 RTC and backup registers

7.31.1 Features

7.32 Event monitor/recorder

7.32.1 Features

7.33 Clocking and power control

7.33.1 Crystal oscillators

7.33.1.1 Internal RC oscillator

7.33.1.2 Main oscillator

7.33.1.3 RTC oscillator

7.33.1.4 Watchdog oscillator

7.33.2 Main PLL (PLL0) and Alternate PLL (PLL1)