NXP LPC1311, LPC1313, LPC1342, LPC1343 User Manual

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller; up to 32 kB flash and 8 kB SRAM; USB device

Rev. 5 — 6 June 2012 Product data sheet

1. General description

The LPC1311/13/42/43 are ARM Cortex-M3 based microcontrollers for em bedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration.

The LPC1311/13/42/43 operate at CPU frequencies of up to 72 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Ha rvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching.

The peripheral complement of the LPC1311/13/42/43 includes up to 32 kB of flash memory , up to 8 kB of data memor y, USB Device (LPC1342/43 only), one Fast-mode Plus

C-bus interface, one UART, four general purpose timers, and up to 42 general purpose

I I/O pins.

Remark: The LPC1311/13/42/43 series consists of the LPC1300 series (parts LPC1311/13/42/43) and the LPC1300L series (parts LPC1311/01 and LPC1313/01). The LPC1300L series features the following enhancements over the LPC1300 series:

• Power profiles with lower power consumption in Active and Sleep modes.

• Four levels for BOD forced reset.

• Second SSP controller (LPC1313FBD48/01 only).

• Windowed Watchdog Timer (WWDT).

• Internal pull-up resistors pull up pins to full V

• Programmable pseudo open-drain mode for GPIO pins.

2. Features and benefits

 ARM Cortex-M3 processor, running at frequencies of up to 72 MHz.  ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).  32 kB (LPC1343/13)/16 kB (LPC1342)/8 kB (LPC1311) on-chip flash programming

memory.

 8 kB (LPC1343/13)/4 kB (LPC1342/11) SRAM.  In-System Programming (ISP) and In-Application Programming (IAP) via on-chip

bootloader software.

 Selectable boot-up: UART or USB (USB on LPC1342/43 only).  On LPC1342/43: USB MSC and HID on-chip drivers.

level.

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 Serial interfaces:

 USB 2.0 full-speed device controller with on-chip PHY for device (LPC1342/43

only).

 UART with fractional baud rate generation, modem, internal FIFO, and

RS-485/EIA-485 support.

 SSP controller with FIFO and multi-protocol capabilities.  Additional SSP controller on LPC1313FBD48/01.

C-bus interface supporting full I2C-bus specification and Fast-mode Plus with a

 I

data rate of 1 Mbit/s with multiple address recognition and monitor mode.

 Ot he r pe r ip her als :

 Up to 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down

resistors.

 Four general purpose counter/ tim er s wi th a to tal of four captu re inputs and 13

match outputs.

 Programmable WatchDog Timer (WDT).  Programmable Windowed Watchdog Timer (WWDT) on LPC1311/01 and

LPC1313/01.

 System tick timer.  Serial Wire Debug and Serial Wire Trace port.  High-current output driver (20 mA) on one pin.  High-current sink drivers (20 mA) on two I  Integrated PMU (Power Management Unit) to minimize power consumption during

Sleep, Deep-sleep, and Deep power-down modes.

 Power profiles residing in boot ROM allowing to optimize performance and minimize

power consumption for any given application through one simple fun ction call. (LPC1300L series, on LPC1311/01 and LPC1313/01 only.)

 Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.  Single power supply (2.0 V to 3.6 V).  10-bit ADC with input multiplexing among 8 pins.  GPIO pins can be used as edge and level sensitive interrupt sources.  Clock output function with divider that can reflect the system oscillator clock, IRC

clock, CPU clock, or the watchdog clock.

 Processor wake-up from Deep-sleep mode via a dedicated start logic using up to 40 of

the functional pins.

 Brownout detect with four separate thresholds for interrupt and one threshold for

forced reset (four thresholds for forced reset on the LPC1311/01 and LPC1313/01 parts).

 Power-On Reset (POR).  Integrated oscillator with an operating range of 1 MHz to 25 MHz.  12 MHz internal RC oscillator trimmed to 1 % accuracy over the entire temperature

and voltage range that can optionally be used as a system clock.

 Programmable watchdog oscillator with a frequency range of 7.8 kHz to 1.8 MHz.  System PLL allows CPU operation up to the maximum CPU rate without the need for a

high-frequency crystal. May be run from the system oscillator or the internal RC oscillator.

 For USB (LPC1342/43), a second, dedicated PLL is provided.  Code Read Protection (CRP) with different security levels.

Product data sheet Rev. 5 — 6 June 2012 2 of 74

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

C-bus pins in Fast-mode Plus.

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 Unique device serial number for identification.  Available as 48-pin LQFP package and 33-pin HVQFN package.

3. Applications

 eMetering  Lighting  Alarm systems  White goods

4. Ordering information

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

Table 1. Ordering information

Type number Package

LPC1311FHN33 HVQFN33 HVQFN33: plastic thermal enhanced very thin quad flat package; no

LPC1311FHN33/01 HVQFN33 HVQFN33: plastic thermal enhanced very thin quad flat package; no

LPC1313FHN33 HVQFN33 HVQFN33: plastic thermal enhanced very thin quad flat package; no

LPC1313FHN33/01 HVQFN33 HVQFN33: plastic thermal enhanced very thin quad flat package; no

LPC1313FBD48 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 × 7 ×

LPC1313FBD48/01 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 × 7 ×

LPC1342FHN33 HVQFN33 HVQFN33: plastic thermal enhanced very thin quad flat package; no

LPC1342FBD48 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 × 7 ×

LPC1343FHN33 HVQFN33 HVQFN33: plastic thermal enhanced very thin quad flat package; no

LPC1343FBD48 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 × 7 ×

Name Description Version

leads; 33 terminals; body 7 × 7 × 0.85 mm

1.4 mm

leads; 33 terminals; body 7 × 7 × 0.85 mm

1.4 mm

leads; 33 terminals; body 7 × 7 × 0.85 mm

1.4 mm

n/a

SOT313-2

n/a

SOT313-2

n/a

SOT313-2

4.1 Ordering options

Table 2. Ordering options for LPC1311/13/42/43

Type number Flash Total

LPC1311FHN33 8 kB 4 kB - no 1 1 1 8 33 HVQFN33 LPC1311FHN33/01 8 kB 4 kB - yes 1 1 1 8 33 HVQFN33 LPC1313FHN33 32 kB 8 kB - no 1 1 1 8 33 HVQFN33 LPC1313FHN33/01 32 kB 8 kB - yes 1 1 1 8 33 HVQFN33 LPC1313FBD48 32 kB 8 kB - no 1 1 1 8 48 LQFP48 LPC1313FBD48/01 32 kB 8 kB - yes 1 1 2 8 48 LQFP48

Product data sheet Rev. 5 — 6 June 2012 3 of 74

SRAM

USB Power

profiles

UART RS-485

I2C/ Fast+

SSP ADC

channels

Pins Package

NXP Semiconductors

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

Table 2. Ordering options for LPC1311/13/42/43

Type number Flash Total

SRAM

LPC1342FHN33 16 kB 4 kB Device no 1 1 1 8 33 HVQFN33 LPC1342FBD48 16 kB 4 kB Device no 1 1 1 8 48 LQFP48 LPC1343FHN33 32 kB 8 kB Device no 1 1 1 8 33 HVQFN33 LPC1343FBD48 32 kB 8 kB Device no 1 1 1 8 48 LQFP48

USB Power

…continued

profiles

UART RS-485

I2C/ Fast+

SSP ADC

channels

Pins Package

Product data sheet Rev. 5 — 6 June 2012 4 of 74

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5. Block diagram

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

GPIO ports

PIO0/1/2/3

RXD

TXD

DTR, DSR

DCD

CT32B0_MAT[3:0]

CT32B1_MAT[3:0]

CT16B0_MAT[2:0]

CT16B1_MAT[1:0]

(2)

, CTS,

(2)

, RI

, RTS

CT32B0_CAP0

CT32B1_CAP0

CT16B0_CAP0

CT16B1_CAP0

SWD

TEST/DEBUG

INTERFACE

ARM

CORTEX-M3

I-code bus

HIGH-SPEED

GPIO

32-bit COUNTER/TIMER 0

32-bit COUNTER/TIMER 1

16-bit COUNTER/TIMER 0

16-bit COUNTER/TIMER 1

D-code bus

UART

USB DEVICE

CONTROLLER

system bus

AHB-LITE BUS

AHB TO

BRIDGE

USB pins

USB PHY

slaveslave

APB

LPC1311/13/42/43

(1)

WDO

POR

(1)

slave

WDT/WWDT

IRC

FLASH

8/16/32 kB

10-bit ADC

SSP0

SSP1

I2C-BUS

IOCONFIG

XTALIN

XTALOUT

CLOCK

GENERATION,

POWER CONTROL,

SYSTEM

FUNCTIONS

clocks and

controls

slave

(3)

(4)

RESET

CLKOUT

ROM

SRAM 4/8 kB

AD[7:0]

SCK0,SSEL0 MISO0, MOSI0

SCK1,SSEL1 MISO1, MOSI0

SCL SDA

SYSTEM CONTROL

002aae722

(1) LPC1342/43 only. (2) LQFP48 package only. (3) On LPC1313FBD48/01 only. (4) Windowed WatchDog Timer (WWDT) on LPC1311/01 and LPC1313/01 only.

Fig 1. Block diagram

Product data sheet Rev. 5 — 6 June 2012 5 of 74

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6. Pinning information

6.1 Pinning

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

4847464544434241403938

PIO2_6 PIO3_0

PIO2_0/DTR R/PIO1_2/AD3/CT32B1_MAT1

RESET/PIO0_0 R/PIO1_1/AD2/CT32B1_MAT0

PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE R/PIO1_0/AD1/CT32B1_CAP0

XTALIN PIO2_11/SCK0

XTALOUT PIO1_10/AD6/CT16B1_MAT1

PIO1_8/CT16B1_CAP0 PIO0_9/MOSI0/CT16B0_MAT1/SWO

PIO0_2/SSEL0/CT16B0_CAP0 PIO0_8/MISO0/CT16B0_MAT0

PIO2_7 PIO2_2/DCD

PIO2_8 PIO2_10

1314151617181920212223

PIO2_1/DSR PIO3_3

LPC1342FBD48 LPC1343FBD48

PIO0_4/SCL PIO1_6/RXD/CT32B0_MAT0

PIO0_5/SDA PIO1_5/RTS/CT32B0_CAP0

PIO0_3/USB_VBUS PIO1_7/TXD/CT32B0_MAT1

PIO1_9/CT16B1_MAT0 V

PIO2_4 PIO3_2

USB_DM PIO1_11/AD7

USB_DP V

PIO2_3/RI

PIO3_1

R/PIO0_11/AD0/CT32B0_MAT3

SWCLK/PIO0_10/SCK0/CT16B0_MAT2

002aae505

PIO2_5 PIO1_4/AD5/CT32B1_MAT3/WAKEUP

PIO2_9

PIO0_7/CTS

PIO0_6/USB_CONNECT/SCK SWDIO/PIO1_3/AD4/CT32B1_MAT2

Fig 2. LPC1342/43 LQFP48 package

Product data sheet Rev. 5 — 6 June 2012 6 of 74

NXP Semiconductors

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

terminal 1

index area

PIO2_0/DTR R/PIO1_2/AD3/CT32B1_MAT1

RESET/PIO0_0 R/PIO1_1/AD2/CT32B1_MAT0

PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE R/PIO1_0/AD1/CT32B1_CAP0

XTALOUT PIO1_10/AD6/CT16B1_MAT1

PIO1_8/CT16B1_CAP0

PIO0_2/SSEL0/CT16B0_CAP0

Fig 3. LPC1342/43 HVQFN33 package

PIO3_2

PIO1_11/AD7

PIO1_4/AD5/CT32B1_MAT3/WAKEUP

PIO1_7/TXD/CT32B0_MAT1

PIO1_6/RXD/CT32B0_MAT0

PIO1_5/RTS/CT32B0_CAP0

32313029282726

1 24

2 23

3 22

XTALIN R/PIO0_11/AD0/CT32B0_MAT3

4 21

LPC1342FHN33

5 20

LPC1343FHN33

6 19

7 18

8 17

33 V

10111213141516

PIO0_4/SCL

PIO0_5/SDA

PIO0_3/USB_VBUS

PIO1_9/CT16B1_MAT0

Transparent top view

USB_DM

SWDIO/PIO1_3/AD4/CT32B1_MAT2

SWCLK/PIO0_10/SCK0/CT16B0_MAT2

PIO0_9/MOSI0/CT16B0_MAT1/SWO

PIO0_8/MISO0/CT16B0_MAT0

002aae516

USB_DP

PIO0_7/CTS

PIO0_6/USB_CONNECT/SCK0

Product data sheet Rev. 5 — 6 June 2012 7 of 74

NXP Semiconductors

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

(1)

PIO3_3

4847464544434241403938

PIO2_6 PIO3_0

PIO2_0/DTR/SSEL1

RESET/PIO0_0 R/PIO1_1/AD2/CT32B1_MAT0

PIO0_1/CLKOUT/CT32B0_MAT2 R/PIO1_0/AD1/CT32B1_CAP0

XTALIN PIO2_11/SCK0

XTALOUT PIO1_10/AD6/CT16B1_MAT1

PIO1_8/CT16B1_CAP0 PIO0_9/MOSI0/CT16B0_MAT1/SWO

PIO0_2/SSEL0/CT16B0_CAP0 PIO0_8/MISO0/CT16B0_MAT0

PIO2_7 PIO2_2/DCD/MISO1

PIO2_8 PIO2_10

(1)

1314151617181920212223

(1)

PIO0_3 PIO1_7/TXD/CT32B0_MAT1

PIO2_1/DSR/SCK1

LPC1313FBD48

LPC1313FBD48/01

PIO3_4 PIO3_2

PIO2_4 PIO1_11/AD7

PIO0_4/SCL PIO1_6/RXD/CT32B0_MAT0

PIO0_5/SDA PIO1_5/RTS/CT32B0_CAP0

PIO1_9/CT16B1_MAT0 V

PIO2_5 VSSPIO3_5 PIO1_4/AD5/CT32B1_MAT3/WAKEUP

PIO0_6/SCK0 SWDIO/PIO1_3/AD4/CT32B1_MAT2

PIO3_1

PIO2_3/RI/MOSI1

R/PIO1_2/AD3/CT32B1_MAT1

R/PIO0_11/AD0/CT32B0_MAT3

SWCLK/PIO0_10/SCK0/CT16B0_MAT2

002aae513

PIO2_9

PIO0_7/CTS

(1)

(1) SSP1 or UART function on LPC1313FBD48/01 only.

Fig 4. LPC1313 LQFP48 package

Product data sheet Rev. 5 — 6 June 2012 8 of 74

NXP Semiconductors

002aae517

LPC1311FHN33

LPC1311FHN33/01

LPC1313FHN33

LPC1313FHN33/01

Transparent top view

PIO0_8/MISO0/CT16B0_MAT0

PIO1_8/CT16B1_CAP0

PIO0_2/SSEL0/CT16B0_CAP0

PIO0_9/MOSI0/CT16B0_MAT1/SWO

SWCLK/PIO0_10/SCK0/CT16B0_MAT2

XTALOUT PIO1_10/AD6/CT16B1_MAT1

XTALIN R/PIO0_11/AD0/CT32B0_MAT3

PIO0_1/CLKOUT/CT32B0_MAT2 R/PIO1_0/AD1/CT32B1_CAP0

RESET/PIO0_0 R/PIO1_1/AD2/CT32B1_MAT0

PIO2_0/DTR R/PIO1_2/AD3/CT32B1_MAT1

PIO0_3

PIO0_4/SCL

PIO0_5/SDA

PIO1_9/CT16B1_MAT0

PIO3_4

PIO3_5

PIO0_6/SCK0

PIO0_7/CTS

PIO1_7/TXD/CT32B0_MAT1

PIO1_6/RXD/CT32B0_MAT0

PIO1_5/RTS/CT32B0_CAP0

PIO3_2

PIO1_11/AD7

PIO1_4/AD5/CT32B1_MAT3/WAKEUP

SWDIO/PIO1_3/AD4/CT32B1_MAT2

8 17

7 18

6 19

5 20

4 21

3 22

2 23

1 24

10111213141516

32313029282726

terminal 1

index area

33 V

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

Fig 5. LPC1311/13 HVQFN33 package

Product data sheet Rev. 5 — 6 June 2012 9 of 74

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6.2 Pin description

Table 3. LPC1313/42/43 LQFP48 pin description table

Symbol Pin Start

/PIO0_0 3

RESET

PIO0_1/CLKOUT/ CT32B0_MAT2/ USB_FTOGGLE

PIO0_2/SSEL0/ CT16B0_CAP0

PIO0_3/USB_VBUS 14

PIO0_4/SCL 15

PIO0_5/SDA 16

PIO0_6/ USB_CONNECT

SCK0

PIO0_7/CTS

PIO0_8/MISO0/ CT16B0_MAT0

Type Reset logic input

[2]

yes I I; PU RESET — External reset input with 20 ns glitch filter. A LOW-going

state

[1]

Description

pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0.

I/O - PIO0_0 — General purpose digital input/output pin with 10 ns glitch

filter.

[3]

yes I/O I; PU PIO0_1 — General purpose digital input/output pin. A LOW level on

this pin during reset starts the ISP command handler or the USB device enumeration (USB on LPC1342/43 only, see description of

PIO0_3). O- CLKOUT — Clockout pin. O- CT32B0_MAT2 — Match output 2 for 32-bit timer 0. O- USB_FTOGGLE — USB 1 ms Start-of-Frame signal (LPC1342/43

only).

[3]

yes I/O I; PU PIO0_2 — General purpose digital input/output pin.

I/O - SSEL0 — Slave select for SSP0. I- CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.

[3]

yes I/O I; PU PIO0_3 — General purpose digital input/output pin. LPC1342/43

only: A LOW level on this pin during reset starts the ISP command

handler, a HIGH level starts the USB device enumeration. I- USB_VBUS — Monitors the presence of USB bus power

(LPC1342/43 only).

[4]

yes I/O I; IA PIO0_4 — General purpose digital input/output pin (open-drain).

I/O - SCL — I

only if I

[4]

yes I/O I; IA PIO0_5 — General purpose digital input/output pin (open-drain).

I/O - SDA — I

only if I

[3]

yes I/O I; PU PIO0_6 — General purpose digital input/output pin.

O- USB_CONNECT

resistor under software control. Used with the SoftConnect USB

feature (LPC1342/43 only). I/O - SCK0 — Serial clock for SSP0.

[3]

yes I/O I; PU PIO0_7 — General purpose digital input/output pin (high-current

output driver). I- CTS

[3]

yes I/O I; PU PIO0_8 — General purpose digital input/output pin.

I/O - MISO0 — Master In Slave Out for SSP0. O- CT16B0_MAT0 — Match output 0 for 16-bit timer 0.

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

C-bus clock input/output (open-drain). High-current sink

C Fast-mode Plus is selected in the I/O configuration

C-bus data input/output (open-drain). High-current sink

C Fast-mode Plus is selected in the I/O configuration

— Signal used to switch an external 1.5 kΩ

— Clear To Send input for UART.

Product data sheet Rev. 5 — 6 June 2012 10 of 74

NXP Semiconductors

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

Table 3. LPC1313/42/43 LQFP48 pin description table

Symbol Pin Start

logic input

PIO0_9/MOSI0/

[3]

yes I/O I; PU PIO0_9 — General purpose digital input/output pin. CT16B0_MAT1/ SWO

Type Reset

Description

state

[1]

I/O - MOSI0 — Master Out Slave In for SSP0. O- CT16B0_MAT1 — Match output 1 for 16-bit timer 0. O- SWO — Serial wire trace output.

[3]

SWCLK/PIO0_10/ SCK0/CT16B0_MAT2

yes I I; PU SWCLK — Serial wire clock.

I/O - PIO0_10 — General purpose dig ital input/ou tput pin. I/O - SCK0 — Serial clock for SSP0. O- CT16B0_MAT2 — Match output 2 for 16-bit timer 0.

[5]

R/PIO0_11/ AD0/CT32B0_MAT3

yes - I; PU R — Reserved. Configure for an alternate function in the IOCONFIG

block. I/O - PIO0_11 — General purpose digital input/output pin. I- AD0 — A/D converter, input 0. O- CT32B0_MAT3 — Match output 3 for 32-bit timer 0.

[5]

R/PIO1_0/ AD1/CT32B1_CAP0

yes - I; PU R — Reserved. Configure for an alternate function in the IOCONFIG

block. I/O - PIO1_0 — General purpose digital input/output pin. I- AD1 — A/D converter, input 1. I- CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.

[5]

R/PIO1_1/ AD2/CT32B1_MAT0

yes - I; PU R — Reserved. Configure for an alternate function in the IOCONFIG

block. I/O - PIO1_1 — General purpose digital input/output pin. I- AD2 — A/D converter, input 2. O- CT32B1_MAT0 — Match output 0 for 32-bit timer 1.

[5]

R/PIO1_2/ AD3/CT32B1_MAT1

yes - I; PU R — Reserved. Configure for an alternate function in the IOCONFIG

block. I/O - PIO1_2 — General purpose digital input/output pin. I- AD3 — A/D converter, input 3. O- CT32B1_MAT1 — Match output 1 for 32-bit timer 1.

[5]

SWDIO/PIO1_3/ AD4/ CT32B1_MAT2

yes I/O I; PU SWDIO — Serial wire debug input/output.

I/O - PIO1_3 — General purpose digital input/output pin. I- AD4 — A/D converter, input 4. O- CT32B1_MAT2 — Match output 2 for 32-bit timer 1.

[5]

PIO1_4/AD5/

yes I/O I; PU PIO1_4 — General purpose digital input/output pin.

40 CT32B1_MAT3/ WAKEUP

I- AD5 — A/D converter, input 5. O- CT32B1_MAT3 — Match output 3 for 32-bit timer 1. I- WAKEUP — Deep power-down mode wake-up pin with 20 ns glitch

filter. This pin must be pulled HIGH externally to enter Deep power-down mode and pulled LOW to exit Deep power-down mode. A LOW-going pulse as short as 50 ns wakes up the part.

…continued

Product data sheet Rev. 5 — 6 June 2012 11 of 74

NXP Semiconductors

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

Table 3. LPC1313/42/43 LQFP48 pin description table

Symbol Pin Start

logic input

PIO1_5/RTS/

[3]

yes I/O I; PU PIO1_5 — General purpose digital input/output pin.

CT32B0_CAP0

Type Reset

Description

state

[1]

O- RTS I- CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.

[3]

PIO1_6/RXD/ CT32B0_MAT0

yes I/O I; PU PIO1_6 — General purpose digital input/output pin.

I- RXD — Receiver input for UART. O- CT32B0_MAT0 — Match output 0 for 32-bit timer 0.

[3]

PIO1_7/TXD/ CT32B0_MAT1

yes I/O I; PU PIO1_7 — General purpose digital input/output pin.

O- TXD — Transmitter output for UART. O- CT32B0_MAT1 — Match output 1 for 32-bit timer 0.

[3]

PIO1_8/CT16B1_CAP0 9

yes I/O I; PU PIO1_8 — General purpose digital input/output pin.

I- CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.

[3]

PIO1_9/CT16B1_MAT0 17

yes I/O I; PU PIO1_9 — General purpose digital input/output pin.

O- CT16B1_MAT0 — Match output 0 for 16-bit timer 1.

[5]

PIO1_10/AD6/ CT16B1_MAT1

yes I/O I; PU PIO1_10 — General purpose dig ital input/ou tput pin.

I- AD6 — A/D converter, input 6. O- CT16B1_MAT1 — Match output 1 for 16-bit timer 1.

[5]

PIO1_11/AD7 42

yes I/O I; PU PIO1_11 — General purpose digital input/output pin.

I- AD7 — A/D converter, input 7.

PIO2_0/DTR

/SSEL1 2

[3]

yes I/O I; PU PIO2_0 — General purpose digital input/output pin.

O- DTR I/O - SSEL1 — Slave Select for SSP1 (LPC1313FBD48/01 only).

PIO2_1/DSR

/SCK1 13

[3]

yes I/O I; PU PIO2_1 — General purpose digital input/output pin.

I- DSR I/O - SCK1 — Serial clock for SSP1 (LPC1313FBD48/01 only).

PIO2_2/DCD

/MISO1 26

[3]

yes I/O I; PU PIO2_2 — General purpose digital input/output pin.

I- DCD I/O - MISO1 — Master In Slave Out for SSP1 (LPC1313FBD48/01 only).

PIO2_3/RI

/MOSI1 38

[3]

yes I/O I; PU PIO2_3 — General purpose digital input/output pin.

I- RI

— Ring Indicator input for UART.

I/O - MOSI1 — Master Out Slave In for SSP1 (LPC1313FBD48/01 only).

[3]

PIO2_4 18

yes I/O I; PU PIO2_4 — General purpose digital input/output pin (LPC1342/43

only).

[3]

PIO2_4 19 PIO2_5 21

yes I/O I; PU PIO2_4 — General purpose digital input/output pin (LPC1313 only).

[3]

yes I/O I; PU PIO2_5 — General purpose digital input/output pin (LPC1342/43

only).

[3]

PIO2_5 20 PIO2_6 1 PIO2_7 11 PIO2_8 12 PIO2_9 24

yes I/O I; PU PIO2_5 — General purpose digital input/output pin (LPC1313 only).

[3]

yes I/O I; PU PIO2_6 — General purpose digital input/output pin.

[3]

yes I/O I; PU PIO2_7 — General purpose digital input/output pin.

[3]

yes I/O I; PU PIO2_8 — General purpose digital input/output pin.

[3]

yes I/O I; PU PIO2_9 — General purpose digital input/output pin.

…continued

— Request To Send output for UART.

— Data Terminal Ready output for UART.

— Data Set Ready input for UART.

— Data Carrier Detect input for UART.

Product data sheet Rev. 5 — 6 June 2012 12 of 74

NXP Semiconductors

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

Table 3. LPC1313/42/43 LQFP48 pin description table

Symbol Pin Start

logic input

PIO2_10 25 PIO2_11/SCK0 31

[3]

yes I/O I; PU PIO2_10 — General purpose dig ital input/ou tput pin.

[3]

yes I/O I; PU PIO2_11 — General purpose digital input/output pin.

Type Reset

state

[1]

Description

I/O - SCK0 — Serial clock for SSP0.

[3]

PIO3_0/DTR

yes I/O I; PU PIO3_0 — General purpose digital input/output pin.

O- DTR

LPC1313/01 only).

[3]

PIO3_1/DSR

yes I/O I; PU PIO3_1 — General purpose digital input/output pin.

I- DSR

LPC1313/01 only).

[3]

PIO3_2/DCD

yes I/O I; PU PIO3_2 — General purpose digital input/output pin.

I- DCD

LPC1313/01 only).

[3]

PIO3_3/RI

yes I/O I; PU PIO3_3 — General purpose digital input/output pin.

I- RI

— Ring Indicator input for UART (LPC1311/01 and LPC1313/01

only).

[3]

PIO3_4 18 PIO3_5 21 USB_DM 19 USB_DP 20 V

no I/O I; PU PIO3_4 — General purpose digital input/output pin (LPC1313 only).

[3]

no I/O I; PU PIO3_5 — General purpose digital input/output pin (LPC1313 only).

[6]

no I/O F USB_DM — USB bidirectional D− line (LPC1342/43 on ly).

[6]

no I/O F USB_DP — USB bidirectional D+ line (LPC1342/43 only).

8; 44- I - 3.3 V supply voltage to the internal regulator, the external rail, and

the ADC. Also used as the ADC reference voltage.

[7]

XTALIN 6

- I - Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V.

[7]

XTALOUT 7 V

- O - Output from the oscillator amplifier.

5; 41- I - Ground.

…continued

— Data Terminal Ready output for UART (LPC1311/01 and

— Data Set Ready input for UART (LPC1311/01 and

— Data Carrier Detect input for UART (LPC1311/01 an d

[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (for VDD = 3.3 V, pin is pulled up to 2.6 V for

parts LPC1311/13/42/43 and pulled up to 3.3 V for parts LPC1311/01 and LPC1313/01); IA = inactive, no pull-up/down enabled; F = floating; floating pins, if not used, should be tied to ground or power to minimize power consumption.

[2] 5 V tolerant pad. See Figure 37

WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode.

[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 36

C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus.

[4] I [5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 36

[6] Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode

only). This pad is not 5 V tolerant.

[7] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

Product data sheet Rev. 5 — 6 June 2012 13 of 74

for pad characteristics. RESET functionality is not available in Deep power-down mode. Use the

NXP Semiconductors

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

Table 4. LPC1311/13/42/43 HVQFN33 pin description table

Symbol Pin Start

/PIO0_0 2

RESET

Type Reset logic input

[2]

yes I I; PU RESET — External reset input with 20 ns glitch filter. A LOW-going pulse

state

[1]

Description

as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0.

I/O - PIO0_0 — General purpose digital input/output pin with 10 ns glitch filter.

[3]

PIO0_1/CLKOUT/ CT32B0_MAT2/ USB_FTOGGLE

yes I/O I; PU PIO0_1 — General purpose digital input/output pin. A LOW level on this

pin during reset starts the ISP command handler or the USB device

enumeration (USB on LPC1342/43 only, see description of PIO0_3). O- CLKOUT — Clock out pin. O- CT32B0_MAT2 — Match output 2 for 32-bit timer 0. O- USB_FTOGGLE — USB 1 ms Start-of-Frame signal (LPC1342/43 only).

[3]

PIO0_2/SSEL0/ CT16B0_CAP0

yes I/O I; PU PIO0_2 — General purpose digital input/output pin.

I/O - SSEL0 — Slave select for SSP0. I- CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.

[3]

PIO0_3/ USB_VBUS

yes I/O I; PU PIO0_3 — General purpose digital input/output pin. LPC1342/43 only: A

LOW level on this pin during reset starts the ISP command handler, a

HIGH level starts the USB device enumeration. I- USB_VBUS — Monitors the presence of USB bus power (LPC1342/43

only).

[4]

PIO0_4/SCL 10

PIO0_5/SDA 11

PIO0_6/ USB_CONNECT

SCK0

yes I/O I; IA PIO0_4 — General purpose digital input/output pin (open-drain).

I/O - SCL — I

C Fast-mode Plus is selected in the I/O configuration register.

[4]

yes I/O I; IA PIO0_5 — General purpose digital input/output pin (open-drain).

I/O - SDA — I

C Fast-mode Plus is selected in the I/O configuration register.

[3]

yes I/O I; PU PIO0_6 — General purpose digital input/output pin.

C-bus clock input/output (open-drain). High-current sink only if

C-bus data input/output (open-drain). High-current sink only if

O- USB_CONNECT

under software control. Used with the SoftConnect USB feature

(LPC1342/43 only). I/O - SCK0 — Serial clock for SSP0.

[3]

PIO0_7/CTS

yes I/O I; PU PIO0_7 — General purpose digital input/output pin (high-current output

driver).

— Clear To Send input for UART.

PIO0_8/MISO0/ CT16B0_MAT0

I- CTS

[3]

yes I/O I; PU PIO0_8 — General purpose digital input/output pin.

I/O - MISO0 — Master In Slave Out for SSP0. O- CT16B0_MAT0 — Match output 0 for 16-bit timer 0.

[3]

PIO0_9/MOSI0/ CT16B0_MAT1/ SWO

yes I/O I; PU PIO0_9 — General purpose digital input/output pin.

I/O - MOSI0 — Master Out Slave In for SSP0. O- CT16B0_MAT1 — Match output 1 for 16-bit timer 0. O- SWO — Serial wire trace output.

— Signal used to switch an external 1.5 kΩ resistor

Product data sheet Rev. 5 — 6 June 2012 14 of 74

NXP Semiconductors

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

Table 4. LPC1311/13/42/43 HVQFN33 pin description table

Symbol Pin Start

SWCLK/PIO0_10/

[3]

SCK0/ CT16B0_MAT2

logic input

Type Reset

state

[1]

Description

yes I I; PU SWCLK — Serial wire clock.

I/O - PIO0_10 — General purpose digital input/output pin. I/O - SCK0 — Serial clock for SSP0. O- CT16B0_MAT2 — Match output 2 for 16-bit timer 0.

[5]

R/PIO0_11/AD0/ CT32B0_MAT3

yes - I; PU R — Reserved. Configure for an alternate function in the IOCONFIG

block. I/O - PIO0_11 — General purpose digital input/output pin. I- AD0 — A/D converter, input 0. O- CT32B0_MAT3 — Match output 3 for 32-bit timer 0.

[5]

R/PIO1_0/AD1/ CT32B1_CAP0

yes - I; PU R — Reserved. Configure for an alternate function in the IOCONFIG

block. I/O - PIO1_0 — General purpose digital input/output pin. I- AD1 — A/D converter, input 1. I- CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.

[5]

R/PIO1_1/AD2/ CT32B1_MAT0

yes - I; PU R — Reserved. Configure for an alternate function in the IOCONFIG

block. I/O - PIO1_1 — General purpose digital input/output pin. I- AD2 — A/D converter, input 2. O- CT32B1_MAT0 — Match output 0 for 32-bit timer 1.

[5]

R/PIO1_2/AD3/ CT32B1_MAT1

yes - I; PU R — Reserved. Configure for an alternate function in the IOCONFIG

block. I/O - PIO1_2 — General purpose digital input/output pin. I- AD3 — A/D converter, input 3. O- CT32B1_MAT1 — Match output 1 for 32-bit timer 1.

[5]

SWDIO/PIO1_3/ AD4/ CT32B1_MAT2

yes I/O I; PU SWDIO — Serial wire debug input/output.

I/O - PIO1_3 — General purpose digital input/output pin. I- AD4 — A/D converter, input 4. O- CT32B1_MAT2 — Match output 2 for 32-bit timer 1.

[5]

PIO1_4/AD5/ CT32B1_MAT3/ WAKEUP

yes I/O I; PU PIO1_4 — General purpose digital input/output pin.

I- AD5 — A/D converter, input 5. O- CT32B1_MAT3 — Match output 3 for 32-bit timer 1. I- WAKEUP — Deep power-down mode wake-up pin with 20 ns glitch filter.

This pin must be pulled HIGH externally to enter Deep power-down mode

and pulled LOW to exit Deep power-down mode. A LOW-going pulse as

short as 50 ns wakes up the part.

PIO1_5/RTS

CT32B0_CAP0

[3]

yes I/O I; PU PIO1_5 — General purpose digital input/output pin.

O- RTS

— Request To Send output for UART.

I- CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.

[3]

PIO1_6/RXD/ CT32B0_MAT0

yes I/O I; PU PIO1_6 — General purpose digital input/output pin.

I- RXD — Receiver input for UART. O- CT32B0_MAT0 — Match output 0 for 32-bit timer 0.

…continued

Product data sheet Rev. 5 — 6 June 2012 15 of 74

NXP Semiconductors

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

Table 4. LPC1311/13/42/43 HVQFN33 pin description table

Symbol Pin Start

PIO1_7/TXD/

[3]

CT32B0_MAT1

logic input

Type Reset

state

[1]

Description

yes I/O I; PU PIO1_7 — General purpose digital input/output pin.

O- TXD — Transmitter output for UART. O- CT32B0_MAT1 — Match output 1 for 32-bit timer 0.

[3]

PIO1_8/ CT16B1_CAP0

PIO1_9/ CT16B1_MAT0

PIO1_10/AD6/ CT16B1_MAT1

yes I/O I; PU PIO1_8 — General purpose digital input/output pin.

I- CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.

[3]

yes I/O I; PU PIO1_9 — General purpose digital input/output pin.

O- CT16B1_MAT0 — Match output 0 for 16-bit timer 1.

[5]

yes I/O I; PU PIO1_10 — General purpose digital input/output pin.

I- AD6 — A/D converter, input 6. O- CT16B1_MAT1 — Match output 1 for 16-bit timer 1.

[5]

PIO1_11/AD7 27

yes I/O I; PU PIO1_11 — General purpose digital input/output pin.

I- AD7 — A/D converter, input 7.

[3]

PIO2_0/DTR

PIO3_2 28 PIO3_4 13 PIO3_5 14 USB_DM 13 USB_DP 14 V

yes I/O I; PU PIO2_0 — General purpose digital input/output pin.

O- DTR

[3]

yes I/O I; PU PIO3_2 — General purpose digital input/output pin.

[3]

no I/O I; PU PIO3_4 — General purpose digital input/output pin (LPC1311/13 only).

[3]

no I/O I; PU PIO3_5 — General purpose digital input/output pin (LPC1311/13 only).

[6]

no I/O F USB_DM — USB bidirectional D− line (LPC1342/43 only).

[6]

no I/O F USB_DP — USB bidirectional D+ line (LPC1342/43 only).

— Data Terminal Ready output for UART.

6; 29- I - 3.3 V supply voltage to the internal regulator, the external rail, and the

ADC. Also used as the ADC reference voltage.

[7]

XTALIN 4

- I - Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V.

[7]

XTALOUT 5 V

- O - O utput from the oscillator amplifier.

33 - - - Thermal pad. Connect to ground.

…continued

[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (for VDD = 3.3 V, pin is pulled up to 2.6 V for

parts LPC1311/13/42/43 and pulled up to 3.3 V for parts LPC1311/01 and LPC1313/01); IA = inactive, no pull-up/down enabled. F = floating; floating pins, if not used, should be tied to ground or power to minimize power consumption.

[2] 5 V tolerant pad. See Figure 37

WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode.

[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 36

[4] I

C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus.

[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as a ADC input, digital section of the pad is disabled, and the pin is not 5 V tolerant (see Figure 36

[6] Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode

only). This pad is not 5 V tolerant.

[7] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

Product data sheet Rev. 5 — 6 June 2012 16 of 74

for pad characteristics. RESET functionality is not available in Deep power-down mode. Use the

NXP Semiconductors

7. Functional description

7.1 Architectural overview

The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and the D-code bus (see Figure 1 system bus and are used similarly to TCM interfaces: one bus dedicated for instruction fetch (I-code) and one bus for data access (D-c ode). The use of two core buses allows for simultaneous operations if concurrent operations target different devices.

7.2 ARM Cortex-M3 processor

The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. The ARM Cortex-M3 offers ma ny new features, including a Thumb-2 instruction set, low interrupt latency, hardware multiply and divide, interruptible/continuable multiple load and store instructions, automatic state save and restore for interrupts, tightly integrated interrupt controller, and multiple core buses capable of simultaneous accesses.

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

). The I-code and D-code core buses are faster than the

Pipeline techniques are employed so that all pa rts of the p rocessing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory.

The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical Reference Manual which is available on the official ARM website.

7.3 On-chip flash program memory

The LPC1311/13/42/43 contain 32 kB (LPC1313 and LPC1343), 16 kB (LPC1342), or 8 kB (LPC1311) of on-chip flash memory.

7.4 On-chip SRAM

The LPC131 1/13/42/43 cont ain a total of 8 kB (LPC1343 and LPC1313) or 4 kB (L PC1342 and LPC1311) on-chip static RAM memory.

7.5 Memory map

The LPC1311/13/42/43 incorporate several distinct memory regions. Figure 6 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping.

The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals. The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals. Each peripheral of either type is allocated 16 kB of space. This allows simplifying the address decoding for each peripheral.

Product data sheet Rev. 5 — 6 June 2012 17 of 74

NXP Semiconductors

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

4 GB

1 GB

0.5 GB

I-code/D-code memory space

0 GB

LPC1311/13/42/43

reserved

private peripheral bus

reserved

AHB peripherals

reserved

APB peripherals

reserved

16 kB boot ROM

reserved

8 kB SRAM (LPC1313/1343)

4 kB SRAM (LPC1311/1342)

reserved

32 kB on-chip flash (LPC1313/43)

16 kB on-chip flash (LPC1342)

8 kB on-chip flash (LPC1311)

0xFFFF FFFF

0xE010 0000

0xE000 0000

0x5020 0000

0x5000 0000

0x4008 0000

0x4000 0000

0x2000 0000

0x1FFF 4000

0x1FFF 0000

0x1000 2000

0x1000 1000

0x1000 0000

0x0000 8000

0x0000 4000

0x0000 2000

0x0000 0000

+ 256 words

active interrupt vectors

AHB peripherals

16 - 127 reserved

12-15

8-11

4-7

0-3

16 15

GPIO PIO3

GPIO PIO2

GPIO PIO1

GPIO PIO0

APB peripherals

23 - 31 reserved

SSP1 (LPC1313FBD48/01)

19 - 21 reserved

system control

IOCONFIG

SSP0

flash controller

PMU

10 - 13 reserved

reserved

USB (LPC1342/43 only)

ADC

32-bit counter/timer 1

32-bit counter/timer 0

16-bit counter/timer 1

16-bit counter/timer 0

UART

WDT/WWDT

C-bus

0x0000 0400

0x0000 0000

0x5020 0000

0x5004 0000

0x5003 0000

0x5002 0000

0x5001 0000

0x5000 0000

0x4008 0000

0x4005 C000

0x4005 8000

0x4004 C000

0x4004 8000

0x4004 4000

0x4004 0000

0x4003 C000

0x4003 8000

0x4002 8000

0x4002 4000

0x4002 0000

0x4001 C000

0x4001 8000

0x4001 4000

0x4001 0000

0x4000 C000

0x4000 8000

0x4000 4000

0x4000 0000

002aae723

Fig 6. LPC1311/13/42/43 memory map

7.6 Nested Vectored Interrupt Controller (NVIC)

The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts.

Product data sheet Rev. 5 — 6 June 2012 18 of 74

NXP Semiconductors

7.6.1 Features

• Controls system exceptions and peripheral interrupts.

• On the LPC1311/13/42/43, the NVIC supports up to 17 vectored interrupts. In

• 8 programmable interrupt priority levels, with hardware priority level masking

• Relocatable vector table.

• Software interrupt generation.

7.6.2 Interrupt sources

Each peripheral device has one interrupt line con nected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source.

Any GPIO pin (total of up to 42 pins) regardless of the selected function, can be programmed to generate an interrupt on a level, or rising edge or falling edge, or both.

7.7 IOCONFIG block

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

addition, up to 40 of the individual GPIO inputs are NVIC-vector capable.

The IOCONFIG block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals.

Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined.

7.8 Fast general purpose parallel I/O

Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Multip le outputs can be set or cleared in one write operation.

LPC1311/13/42/43 use accelerated GPIO functions:

• GPIO block is a dedicated AHB peripheral so that the fastest possible I/O timing can

be achieved.

• Entire port value can be written in one instruction.

Additionally, any GPIO pin (total of up to 42 pins) providing a digital function can be programmed to generate an interrupt on a level, a rising or falling edge, or both.

7.8.1 Features

• Bit level port registers allow a single instruction to set or clear any number of bits in

one write operation.

• Direction control of individual bits.

• All I/O default to inputs with pull-up resistors enabled after reset with the exception of

the I

C-bus pins PIO0_4 and PIO0_5.

• Pull-up/pull-down resistor configuration can be programmed through the IOCONFIG

block for each GPIO pin.

Product data sheet Rev. 5 — 6 June 2012 19 of 74

NXP Semiconductors

• On the LPC1311/13/42/43, all GPIO pins (except PIO0_4 and PIO0_5) are pulled up

• On the LPC131 1/01 and LPC1313/01, all GPIO pins (except PIO0_4 and PIO0_5) ar e

7.9 USB interface (LPC1342/43 only)

The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The host controller allocates the USB bandwidth to attached devices through a token-based protocol. The bus supports hot-plugging and dynamic configuration of the d evices. All transactions are initiated by the host controller.

The LPC1342/43 USB interface is a device controller with on-chip PHY for device functions.

7.9.1 Full-speed USB device controller

The device controller enables 12 Mbit/s data exchange with a USB Host controller. It consists of a register interface, serial interface engine, and endpoint buffer memory. The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer. The status of a completed USB transfer or error condition is indicated via status registers. An interrupt is also generated if enabled.

to 2.6 V (V

= 3.3 V) if their pull-up resistor is enabled in the IOCONFIG block.

pulled up to 3.3 V (V block.

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

= 3.3 V) if their pull-up resistor is enabled in the IOCONFIG

7.9.1.1 Features

• Dedicated USB PLL available.

• Fully compliant with USB 2.0 specification (full speed).

• Supports 10 physical (5 logical) endpoints with up to 64 bytes buffer RAM per

endpoint (see Table 5

• Supports Control, Bulk, Isochronous, and Interrupt endpoints.

• Supports SoftConnect feature.

• Double buffer implementation for Bulk and Isochronous endpoints.

Table 5. USB device endpoint configuration

Logical endpoint

0 0 Control out 64 no 0 1 Control in 64 no 1 2 Interrupt/Bulk out 64 no 1 3 Interrupt/Bulk in 64 no 2 4 Interrupt/Bulk out 64 no 2 5 Interrupt/Bulk in 64 no 3 6 Interrupt/Bulk out 64 yes 3 7 Interrupt/Bulk in 64 yes 4 8 Isochronous out 512 yes 4 9 Isochronous in 512 yes

Physical endpoint

Endpoint type Direction Packet size

(byte)

Double buffer

Product data sheet Rev. 5 — 6 June 2012 20 of 74

NXP Semiconductors

7.10 UART

The LPC1311/13/42/43 contains one UART. Support for RS-485/9-bit mode allows both software addr ess detection and automatic

address detection using 9-bit mode. The UART includes a fractional baud rate generator. Standard baud rates such as

115200 Bd can be achieved with any crystal frequency above 2 MHz.

7.10.1 Features

• Maximum UART data bit rate of 4.5 MBit/s.

• 16-byte receive and transmit FIFOs.

• Register locations conform to 16C550 industry standard .

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

• Built-in fractional baud rate generator covering wide range of baud rates without a

• Fractional divider for baud rate control, auto baud capabilities and FIFO control

• Support for RS-485/9-bit mode.

• Support for modem control.

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

need for external crystals of particular values.

mechanism that enables software flow control implementation.

7.1 1 SSP serial I/O controller

The LPC1311/13/42/43 contain one SSP controller. An additional SSP controller is available on the LPC1313FBD48/01 package.

The SSP controller is capable of operation on a SSP, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data.

7.11.1 Features

• Maximum SSP speed of 36 Mbit/s (master) or 6 Mbit/s (slave)

• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

Semiconductor Microwire buses

• Synchronous serial communication

• Master or slave operation

• 8-frame FIFOs for both transmit and receive

• 4-bit to 16-bit frame

7.12 I2C-bus serial I/O controller

The LPC1311/13/42/43 contain one I2C-bus controller.

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The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line (SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or sla ve mode, de pending o n whether the chip ha s to initiate a data transfer or is only addressed. The I controlled by more than one bus master connected to it.

7.12.1 Features

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

C is a multi-master bus and can be

• The I

pins. The I

• Easy to configure as master, slave, or master/slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

• The I

7.13 10-bit ADC

The LPC1311/13/42/43 contains one ADC. It is a single 10-bit successive approximation ADC with eight channels.

7.13.1 Features

C-bus interface is a standard I2C-bus compliant interface with true open-drain

C-bus interface also supports Fast-mode Plus with bit rates up to 1 Mbit/s.

C-bus can be used for test and diagnostic purposes.

C-bus controller supports multiple address recognition a nd a bus monitor mode.

• 10-bit successive approximation ADC.

• Input multiplexing among 8 pins.

• Power-down mode.

• Measurement range 0 V to V

• 10-bit conversion time ≥ 2.44 μs (up to 400 kSamples/s).

• Burst conversion mode for single or multiple inputs.

• Optional conversion on transition of input pin or timer match signal.

• Individual result registers for each ADC channel to reduce interrupt overhead.

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7.14 General purpose external event counter/timers

The LPC1311/13/42/43 includes two 32-bit counter/timers and two 16-bit counter/timers. The counter/timer is designed to count cycles of the system derived clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. Each counter/timer also includes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt.

7.14.1 Features

• A 32-bit/16-bit counter/timer with a programmable 32-bit/16-bit prescaler.

• Counter or timer operation.

• One capture channel per timer , that can take a snapshot of the timer value when an

• Four match registers per timer that allow:

• Up to four external outputs corresponding to match registers, with the following

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

input signal transitions. A capture event may also generate an interrupt.

– Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation.

capabilities:

– Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match.

7.15 System tick timer

The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception at a fixed time interval, normally set to 10 ms.

7.16 Watchdog timer

Remark: The standard Watchdog timer is available on parts LPC1311/13/42/43.

The purpose of the watchdog is to reset the microcontroller within a selectable time period. When enabled, the watchdog will generate a system reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined amount of time.

7.16.1 Features

• Internally resets chip if not periodically reloaded.

• Debug mode.

• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be

disabled.

• Incorrect/incomplete feed sequence causes reset/interrupt if enabled.

• Flag to indicate watchdog reset.

• Programmable 24-bit timer with internal prescaler.

Product data sheet Rev. 5 — 6 June 2012 23 of 74

+ 51 hidden pages

NXP LPC1311, LPC1313, LPC1342, LPC1343 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1. General description

2. Features and benefits

3. Applications

4. Ordering information

4.1 Ordering options

5. Block diagram

6. Pinning information

6.1 Pinning

6.2 Pin description

7. Functional description

7.1 Architectural overview

7.2 ARM Cortex-M3 processor

7.3 On-chip flash program memory

7.4 On-chip SRAM

7.5 Memory map

7.6 Nested Vectored Interrupt Controller (NVIC)

7.6.1 Features

7.6.2 Interrupt sources

7.7 IOCONFIG block

7.8 Fast general purpose parallel I/O

7.8.1 Features

7.9 USB interface (LPC1342/43 only)

7.9.1 Full-speed USB device controller

7.9.1.1 Features

7.10 UART

7.10.1 Features

7.1 1 SSP serial I/O controller

7.11.1 Features

7.12 I2C-bus serial I/O controller

7.12.1 Features

7.13 10-bit ADC

7.13.1 Features

7.14 General purpose external event counter/timers

7.14.1 Features

7.15 System tick timer

7.16 Watchdog timer

7.16.1 Features