NXP IW416 User Manual

IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

Rev. 3 — 12 March 2021 Preliminary data sheet

1 Product overview

The IW416 is a highly integrated Wi-Fi 4 and Bluetooth 5.1 System-on-Chip (SoC) enabling a low-cost connectivity solution. Supporting a 1x1 SISO Wi-Fi operation in the

2.4 GHz and the 5 GHz band, the SoC provides a full-feature Wi-Fi subsystem with a peak PHY date rate of 150 Mbit/s. In addition to classic Bluetooth features, the IW416 enables Bluetooth 5.1 capabilities including Low Energy (LE), LE long range and LE data up to 2 Mbit/s.

With integrated transmit (Tx) PAs, receive (Rx) LNAs and Tx/Rx switches for the Wi-Fi and Bluetooth radios, the IW416 simplifies design allowing quick integration of either dual or single-antenna operation. The dual-antenna configuration enables simultaneous Wi-Fi and Bluetooth operation. With the single-antenna configuration, simultaneous 5 GHz WiFi and Bluetooth is supported and in the 2.4 GHz band, the single-antenna configuration allows arbitrated transmit and receive operation of Wi-Fi and Bluetooth.

Promoting synergistic operation, the IW416 implements advanced Wi-Fi and Bluetooth co-existence hardware in conjunction with algorithms to optimize collaborative performance. In addition, support for external radio co-existence (e.g. cellular) is provided through an external interface.

Available in both HVQFN and WLCSP packages with two operating temperature ranges of 0 to 70°C and -40 to 85°C, the IW416 supports a SDIO host interface for the Wi-Fi radio and a UART host interface for Bluetooth radio.

SDIO interface

UART interface

Audio interface

(I2S/PCM)

GPIO interface

Supply voltages

Power-down

XTAL_IN

XTAL_OUT

Figure 1. Application block diagram

IW416

Wi-Fi antenna

Wi-Fi 5 GHz Tx/Rx

Diplexer

Wi-Fi 2.4 GHz Tx/Rx

Bluetooth antenna

Bluetooth Tx/Rx

Coexistence

NXP Semiconductors

1.1 Applications

• Smart home: Voice assist device, smart printer, smart speaker, home automation

gateway, and IP camera

• Industrial and building automation

• Asset management

• Retail/POS

• Healthcare and medical devices

• Smart city

1.2 Wi-Fi key features

• Support 802.11 a/b/g/n

• Dual band: 2.4 GHz and 5 GHz

• Single stream 802.11n with 20 MHz and 40 MHz channels

• Up to MCS7 data rates (150 Mbit/s)

• Dynamic Rapid Channel Switching (DRCS) for simultaneous operation in 2.4 GHz and

5 GHz bands

• Interface to coexist with 802.15.4, LTE, or other radios

• Security: WPA3, WPA2, WPA2 and WPA mixed mode, WEP

IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

1.3 Bluetooth key features

• Full Bluetooth 5.1 features

• Long range - 4x coverage

• 2 Mbit/s data rate - 2x faster

• Improved advertisement capability - enables more IoT services

• I2S and PCM audio interfaces

• AES security

1.4 Host interfaces

Wi-Fi and Bluetooth host interface options

Wi-Fi Bluetooth

SDIO 3.0 UART

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1.5 Operating characteristics

• Supply voltage: 1.05V, 1.8V, 2.2V and 3.3V (optional)

• Operating temperature: – Commercial: 0 to 70°C – Industrial: -40 to 85°C

1.6 General features

• Package options – 68-pin HVQFN (8 mm x 8 mm) – 76-bump WLCSP (3.95 mm x 3.565 mm)

• Simultaneous Wi-Fi and Bluetooth operation supported with dual antenna configuration – Shared Wi-Fi and Bluetooth operation with single antenna is possible

• Power saving features – Efficient power management system – Sleep and standby modes – Deep-sleep mode

• Independent ARM-based Wi-Fi and Bluetooth CPUs – Wi-Fi CPU: 160 MHz clock speed – Bluetooth CPU: 128 MHz clock speed

• Memory: – Internal SRAM – Boot ROM – OTP memory to store the MAC address and calibration data

• Peripheral Interface – General-Purpose I/O (GPIO) interface

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Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

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1.7 Internal block diagram

IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

SDIO 3.0

Host interface

UART

I2S/PCM

Supply voltages

Figure 2. Internal block diagram

Wi-Fi CPU

Bluetooth

CPU

Power regulator

Wi-Fi 4

MAC/Baseband

Bluetooth/

Bluetooth LE

Baseband

SPDT5 GHz PA/LNA

2.4 GHz PA/LNA SPDT

Bluetooth RF

CoexistenceOTP

Wi-Fi 5G Tx/Rx

Wi-Fi 2.4G Tx/Rx

Bluetooth Tx/Rx

Coexistence

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2 Ordering information

IW416xx/xxxxx

IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

Packing code

Part number

Package code

Figure 3. Part numbering scheme

Table 1. Part order codes

Part order code Package type Operating

IW416HN/A1CK 68-pin HVQFN - 8 x 8 x 0.85 mm, with 0.4 mm pitch Commercial Tray

IW416HN/A1CMP 68-pin HVQFN - 8 x 8 x 0.85 mm, with 0.4 mm pitch Commercial Tape and Reel

IW416HN/A1IK 68-pin HVQFN - 8 x 8 x 0.85 mm, with 0.4 mm pitch Industrial Tray

IW416HN/A1IMP 68-pin HVQFN - 8 x 8 x 0.85 mm, with 0.4 mm pitch Industrial Tape and Reel

IW416UK/A1CZ 76-bump WLCSP - 3.95 x 3.565 x 0.495 mm Commercial Tape and Reel

IW416UK/A1IZ 76-bump WLCSP - 3.95 x 3.565 x 0.495 mm Industrial Tape and Reel

Temperature code C = Commercial I = Industrial

Die version

Packing

temperature range

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3 Wi-Fi subsystem

3.1 IEEE 802.11 standards

• 802.11n maximum data rates up to 72 Mbit/s (20 MHz channel bandwidth), 150 Mbit/s

(40 MHz channel bandwidth)

• 802.11a/g/b backward compatibility

• 802.11d international roaming

• 802.11e quality of service

• 802.11h transmit power control

• 802.11h DFS radar pulse detection

• 802.11i enhanced security

• 802.11k radio resource measurement

• 802.11n block acknowledgment extension

• 802.11r fast hand-off for AP roaming

• 802.11u Hotspot 2.0 (STA mode only)

• 802.11v TIM frame transmission/reception

• 802.11w protected management frames

• Fully supports clients (stations) implementing IEEE Power Save mode

IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

3.2 Wi-Fi MAC

The Wi-Fi MAC has the following features:

• Simultaneous peer-to-peer and infrastructure modes

• RTS/CTS for operation under DCF

• Hardware filtering of 32 multicast addresses and duplicate frame detection for up to 32

unicast addresses

• On-chip Tx and Rx FIFO for maximum throughput

• Open System and Shared Key Authentication services

• A-MPDU Rx (de-aggregation) and Tx (aggregation)

• 20/40 MHz coexistence

• Reduced Inter-Frame Spacing (RIFS) receive

• Packet drop scheme

• Management information base counters

• Radio resource measurement counters

• Quality of service queues

• Block acknowledgment extension

• Dynamic frequency selection

• TIM frame transmission/reception

• Multiple BSS/Station

• Transmit rate adaptation

• Transmit power control

• Long and short preamble generation on a frame-by-frame basis for 802.11b frames

• NXP mobile hotspot

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3.3 Wi-Fi baseband

The Wi-Fi baseband has the following features:

• 802.11n 1x1 SISO

• Bandwidth supported: – 20 MHz – 20 in 40 MHz (upper and lower) – 40 MHz – 20 MHz duplicate

• 802.11n modulation coding scheme (MCS) 0-7 and MCS 32 (HT duplicate mode)

• 802.11n 400 ns and 800 ns guard interval

• Dynamic frequency selection (radar detection) – Enhanced radar detection for long and short pulse radar – Enhanced AGC scheme for DFS channel

• Radio resource measurement

• Optional 802.11n SISO features: – 20/40 MHz coexistence – 1 spatial stream STBC reception – Short guard interval – RIFS on receive path for 802.11n packets – 802.11n greenfield Tx/Rx

• Power save features

IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

3.4 Wi-Fi radio

The Wi-Fi radio has the following features:

• Integrated direct-conversion radio

• 20 MHz and 40 MHz channel bandwidths

Wi-Fi Rx path

• Direct conversion architecture: no need for an external SAW filter

• On-chip gain selectable LNA with optimized noise figure and power consumption

• High dynamic range AGC function in receive mode

Wi-Fi Tx path

• Internal PA with power control

• Optimized Tx gain distribution for linearity and noise performance

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Radio channel frequencies

The Wi-Fi RF radio integrates all the necessary functions for transmit and receive operation.

The channel frequencies are controlled through an internal bus and software programmable.

Table 2 shows the frequencies supported by the 20 MHz channels.

Table 2. Frequencies supported by 20 MHz channels

Channel Frequency (GHz)

1 2.412

2 2.417

3 2.422

4 2.427

5 2.432

6 2.437

7 2.442

8 2.447

9 2.452

10 2.457

11 2.462

12 2.467

13 2.472

-- --

36 5.180

40 5.200

44 5.220

48 5.240

52 5.260

56 5.280

60 5.300

64 5.320

100 5.500

104 5.520

108 5.540

112 5.560

116 5.580

120 5.600

124 5.620

128 5.640

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Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

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Table 2. Frequencies supported by 20 MHz channels...continued

Channel Frequency (GHz)

132 5.660

136 5.680

140 5.700

149 5.745

153 5.765

157 5.785

161 5.805

165 5.825

128 5.640

132 5.660

136 5.680

140 5.700

149 5.745

153 5.765

157 5.785

161 5.805

165 5.825

IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

Table 3 shows the frequencies supported by the 40 MHz channels.

Table 3. Frequencies Supported by the 40 MHz channels

Channel Frequency (GHz)

1–5 2.422

2–6 2.427

3–7 2.432

4–8 2.437

5–9 2.442

6–10 2.447

7–11 2.452

-- --

36–40 5.190

44–48 5.230

52–56 5.270

60–64 5.310

100–104 5.510

108–112 5.550

116–120 5.590

124–128 5.630

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Table 3. Frequencies Supported by the 40 MHz channels...continued

Channel Frequency (GHz)

132–136 5.670

149–153 5.755

157–161 5.795

3.5 Wi-Fi encryption

• WEP 64 bit and 128 bit encryption with hardware TKIP processing (WPA)

• AES/CCMP as part of the 802.11i security standard (WPA2 and WPA mixed mode)

• AES/CMAC as part of the 802.11w security standard

3.6 Wi-Fi host interfaces

• SDIO 3.0 device interface

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Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

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4 Bluetooth subsystem

4.1 Bluetooth 2.4 GHz Tx/Rx

• Bluetooth 5.1

• Bluetooth Class 2 and Bluetooth Class 1

• Single-ended, shared Tx/Rx path for Bluetooth

• PCM interface for voice applications

• Baseband and radio Basic Data Rate (BDR)/Enhanced Data Rate (EDR) packet types

—1 Mbit/s (GFSK), 2 Mbit/s (π/4-DQPSK), and 3 Mbit/s (8DPSK)

• Fully functional Bluetooth baseband—Adaptive Frequency Hopping (AFH), forward error correction, header error control, access code correlation, Cyclic Redundancy Check (CRC), encryption bit stream generation, and whitening

• Adaptive Frequency Hopping (AFH) using Packet Error Rate (PER)

• Interlaced scan for faster connection setup

• Simultaneous active Asynchronous Connection-Less (ACL) connection support

• Automatic ACL packet type selection

• Full master and slave piconet support

• Scatternet support

• Bluetooth-based indoor location with up to 16 antenna support

• Standard UART HCI transport layer

• HCI layer to integrate with profile stack

• SCO/eSCO links with hardware accelerated audio signal processing and hardware

supported PPEC algorithm for speech quality improvement

• All standard SCO/eSCO voice coding

• All standard pairing, authentication, link key, and encryption operations

• Standard Bluetooth power saving mechanisms (hold, sniff modes, and sniff sub-rating)

• Enhanced Power Control (EPC)

• Channel Quality Driven Data Rate (CQDDR)

• Wide Band Speech (WBS) support (2 WBS link)

• Encryption (AES) support

• Low Latency Reconnection (LLR) (future BT standard)

IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

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4.2 Bluetooth Low Energy (LE)

• Broadcaster, Observer, Central, and Peripheral roles

• Supports link layer topology to be master and slave (connects up to 16 links)

• Wi-Fi/Bluetooth Coexistence protocol support

• Shared RF with BDR/EDR

• Encryption (AES) support

• Intelligent Adaptive Frequency Hopping (AFH)

• LE Privacy 1.2

• LE Secure Connection

• LE Data Length Extension

• LE Advertising Extension

• 2 Mbit/s LE

4.3 Bluetooth host interfaces

• High-Speed UART interface up to 4 Mbit/s

IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

4.4 Audio interfaces

4.4.1 I2S interface

• I2S (Inter-IC Sound) interface for audio data connection to Analog-to-Digital Converter

(ADC)

• Master and slave modes for I2S, MSB, and LSB audio interfaces

• Tri-state I2S interface compatibility

• I2S pins shared with PCM pins

4.4.2 PCM interface

The PCM interface is used to exchange audio data between the host and the Bluetooth/ LE functional block.

• Master or slave mode

• PCM bit width size of 8 bits or 16 bits

• Up to 4 slots with configurable bit width and start positions

• PCM short frame and long frame 1 synchronization

• Tri-state PCM interface capability

• PCM pins shared with I2S pins

1 In PCM Master mode, PCM long frame synchronization is 1 clock wide. In PCM Slave mode, PCM

Master’s long frame synchronization pattern is supported.

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aaa- 036047

CLK

DOUT

SYNC

DIN

MSb MSb-1 MSb-2 MSb-3 d1

d1 d0

MSbDon't Care Don't CareMSb-1 MSb-2 MSb-3

4.4.2.1 Protocol description

The PCM interface supports short frame sync. Figure 4 shows an example of a PCM interface with 4 signals.

Figure 4. PCM Short Frame Sync

4.5 Coexistence

The advanced coexistence framework provides packet traffic arbitration (PTA) for the following use cases:

IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

• Coexistence between internal Wi-Fi and internal Bluetooth radios

• Coexistence between internal Wi-Fi and Bluetooth radios and an external radio such

as 802.15.4, LTE or 5G. The external radio can be connected to the PTA interface or WCI-2 interface. WCI-2 message format and message type comply with Bluetooth special interest group (SIG) core specification volume 7 part C.

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5 Pin information

5.1 Signal diagram

Figure 5 shows the signals for the device. Some signals are muxed through GPIO.

IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

SD_CLK

SD_CMD

SD_DAT[3:0]

UART_SIN

UART_SOUT

UART_RTSn UART_CTSn

UART_DTRn

UART_DSRn

WCI-2_SIN

WCI-2_SOUT

EXT_STATE

EXT_GNT

EXT_FREQ

EXT_PRI

EXT_REQ

GPIO[15:0]

JTAG_TCK

JTAG_TDI JTAG_TDO JTAG_TMS

SDIO Interface

UART Interface (through GPIO)

WCI-2 interface

PTA interface

GPIO Interface

JTAG Interface (through GPIO)

IW416

Wi-Fi Radio Interface

Bluetooth Radio Interface

RF Front End

Control Interface

I2S Interface

(through GPIO)

PCM Interface

(through GPIO)

Power Management

Interface

(through GPIO)

LDO Interface

Clock Interface

RF_TR_2

RF_TR_5

BRF_ANT

RF_CNTL0_N RF_CNTL1_P RF_CNTL2_N

RF_CNTL3_P

I2S_LRCLK I2S_BCLK I2S_DOUT I2S_DIN I2S_CCLK

PCM_SYNC PCM_CLK PCM_MCLK PCM_DIN PCM_DOUT

DVSC[0] DVSC[1]

LDO_VIN LDO_VOUT

XTAL_IN

XTAL_OUT

SLP_CLK_IN

XOSC_EN

PDnPower-down

Signals may be muxed. See Section 5.5 "Pin description".

Figure 5. Signal diagram

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5.2 Pin assignment - 68-pin HVQFN package

Note that some pins have muxed signals. See Section 5.5 "Pin description".

IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

AVDD33

AVDD18

DNC

GPIO[9]

GPIO[10]

VIO

GPIO[11]

GPIO[12]

GPIO[13]

GPIO[0]

VCORE

VIO_RF

RF_CNTL1_P

RF_CNTL0_N

RF_CNTL3_P

RF_CNTL2_N

SD_CMD

LDO_VOUT

LDO_VIN

IW416

VCORE

PDn

AVDD18

GPIO[6]

GPIO[2]

GPIO[4]

GPIO[3]

GPIO[1]

VIO

GPIO[7]

GPIO[5]

GPIO[14]

GPIO[15]

GPIO[8]

WCI-2_SOUT

WCI-2_SIN

DNC

SLP_CLK_IN

AVDD18

XTAL_OUT

XTAL_IN

AVDD18

AVSS

SD_DAT[3]

SD_CLK

VIO_SD

SD_DAT[0]

SD_DAT[1]

SD_DAT[2]

AVDD18

VCORE

BRF_ANT

RF_TR_2

VPA

AVDD18

RF_TR_5

Figure 6. Pin assignment (package top view)

Note: See Section 9.10 "Reference clock specifications" for electrical specifications. See Section 10.3 "Package marking" for more information on package marking and pin 1 location.

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5.2.1 Pin list by number

The following table shows the pin list sorted by pin number.

Table 4. Pin list by number

Pin number Pin name Power Type

1 AVDD33 -- Power

2 AVDD18 -- Power

3 DNC — DNC

4 DNC — DNC

5 GPIO[9] VIO I/O

5 DNC — Do not connect

6 GPIO[10] VIO I/O

7 VIO -- Power

8 GPIO[11] VIO I/O

9 GPIO[12] VIO I/O

10 GPIO[13] VIO I/O

11 GPIO[0] VIO I/O

12 VCORE -- Power

13 VIO_RF -- Power

14 RF_CNTL1_P VIO_RF O

15 RF_CNTL0_N VIO_RF O

16 RF_CNTL3_P VIO_RF O

17 RF_CNTL2_N VIO_RF O

18 AVDD18 -- Power

19 AVDD18 -- Power

20 AVDD18 -- Power

21 BRF_ANT AVDD18 A, I/O

22 NC -- NC

23 VCORE -- Power

24 NC -- NC

25 RF_TR_2 AVDD18 A, I/O

26 AVDD18 -- Power

27 NC -- NC

28 VPA -- Power

29 VPA -- Power

30 RF_TR_5 AVDD18 A, I/O

31 AVDD18 -- Power

32 NC -- NC

33 NC -- NC

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Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

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Table 4. Pin list by number...continued

Pin number Pin name Power Type

34 NC -- NC

35 AVSS -- Ground

36 AVDD18 -- Power

37 AVDD18 -- Power

38 AVDD18 -- Power

39 XTAL_IN AVDD18 A, I/O

40 XTAL_OUT AVDD18 A, I/O

41 AVDD18 -- Power

42 SLP_CLK_IN AVDD18 I

43 DNC -- DNC

44 WCI-2_SIN AVDD18 I

45 WCI-2_SOUT AVDD18 O

46 GPIO[8] VIO I/O

47 GPIO[15] VIO I/O

48 GPIO[14] VIO I/O

49 GPIO[5] VIO I/O

50 GPIO[7] VIO I/O

51 VIO -- Power

52 GPIO[1] VIO I/O

53 GPIO[4] VIO I/O

54 GPIO[2] VIO I/O

55 GPIO[6] VIO I/O

56 GPIO[3] VIO I/O

57 AVDD18 -- Power

58 PDn AVDD18 I

59 VCORE -- Power

60 LDO_VOUT -- Power

61 LDO_VIN -- Power

62 SD_CMD VIO_SD I/O

63 SD_CLK VIO_SD I

64 VIO_SD -- Power

65 SD_DAT[0] VIO_SD I/O

66 SD_DAT[1] VIO_SD I/O

67 SD_DAT[2] VIO_SD I/O

68 SD_DAT[3] VIO_SD I/O

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Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

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5.2.2 Pin list by name

The following table shows the pin list sorted by pin name.

Table 5. Pin by name

Pin name Pin number Power Type

AVDD18 2 -- Power

AVDD18 18 -- Power

AVDD18 19 -- Power

AVDD18 20 -- Power

AVDD18 26 -- Power

AVDD18 31 -- Power

AVDD18 36 -- Power

AVDD18 37 -- Power

AVDD18 38 -- Power

AVDD18 41 -- Power

AVDD18 57 -- Power

AVDD33 1 -- Power

AVSS 35 -- Ground

BRF_ANT 21 AVDD18 A, I/O

DNC 43 -- DNC

GPIO[0] 11 VIO I/O

GPIO[1] 52 VIO I/O

GPIO[10] 6 VIO I/O

GPIO[11] 8 VIO I/O

GPIO[12] 9 VIO I/O

GPIO[13] 10 VIO I/O

GPIO[14] 48 VIO I/O

GPIO[15] 47 VIO I/O

GPIO[2] 54 VIO I/O

GPIO[3] 56 VIO I/O

GPIO[4] 53 VIO I/O

GPIO[5] 49 VIO I/O

GPIO[6] 55 VIO I/O

GPIO[7] 50 VIO I/O

GPIO[8] 46 VIO I/O

GPIO[9] 5 VIO I/O

LDO_VIN 61 -- Power

LDO_VOUT 60 -- Power

NC 22 -- NC

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Table 5. Pin by name...continued

Pin name Pin number Power Type

NC 24 -- NC

NC 27 -- NC

NC 32 -- NC

NC 33 -- NC

NC 34 -- NC

PDn 58 AVDD18 I

RF_CNTL0_N 15 VIO_RF O

RF_CNTL1_P 14 VIO_RF O

RF_CNTL2_N 17 VIO_RF O

RF_CNTL3_P 16 VIO_RF O

RF_TR_2 25 AVDD18 A, I/O

RF_TR_5 30 AVDD18 A, I/O

SD_CLK 63 VIO_SD I

SD_CMD 62 VIO_SD I/O

SD_DAT[0] 65 VIO_SD I/O

SD_DAT[1] 66 VIO_SD I/O

SD_DAT[2] 67 VIO_SD I/O

SD_DAT[3] 68 VIO_SD I/O

SLP_CLK_IN 42 AVDD18 I

DNC 4 — DNC

DNC 3 — DNC

VCORE 12 -- Power

VCORE 23 -- Power

VCORE 59 -- Power

VIO 7 -- Power

VIO 51 -- Power

VIO_RF 13 -- Power

VIO_SD 64 -- Power

VPA 28 -- Power

VPA 29 -- Power

WCI-2_SIN 44 AVDD18 I

WCI-2_SOUT 45 AVDD18 O

XTAL_IN 39 AVDD18 A, I/O

XTAL_OUT 40 AVDD18 A, I/O

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Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

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5.3 Bump locations - 76-bump WLCSP package

IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

Figure 7. Bump locations - 76-bump WLCSP (non-bump side view, bumps down)

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IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

5.3.1 Bump positions relative to die center

Table 6. Bump names and locations on 76-bump WLCSP top view

Alpha-numeric

designation

A2 SD_DAT[1] -1080.696 1562.352

A3 SD_DAT[3] -730.696 1562.352

A5 VIO -380.696 1562.352

A7 VIO_RF 81.805 1562.352

A8 RF_CNTL1_P 431.805 1562.352

A9 AVDD18 781.805 1562.352

A10 AVDD18 1131.805 1562.352

B11 VSS 1506.805 1377.352

C1 LDO_VIN -1430.696 1124.852

C2 VIO_SD -1080.696 1212.352

C3 SD_DAT[2] -730.696 1212.352

C5 VCORE -380.696 1212.352

C7 GPIO[0] 81.805 1212.352

C8 VSS 431.805 1212.352

C9 VSS 781.805 1212.352

C10 VSS 1131.805 1212.352

D1 LDO_VOUT -1430.696 774.852

D2 SD_CLK -1080.696 862.352

D3 SD_DAT[0] -730.696 862.352

D5 GPIO[10] -380.696 862.352

D7 GPIO[13] 81.805 862.352

D8 RF_CNTL0_N 431.805 862.352

D9 RF_CNTL3_P 781.805 774.852

D10 VSS 1156.805 774.852

D11 BRF_ANT 1506.805 724.852

E1 VCORE -1430.696 424.852

E2 SD_CMD -1080.696 512.352

E3 VSS -730.696 512.352

E5 GPIO[9] -380.696 512.352

E7 GPIO[11] 81.805 512.352

E8 GPIO[12] 431.805 512.352

E9 RF_CNTL2_N 781.805 424.852

E10 VSS 1131.805 424.852

Signal name

Bump location relative to die center (non-bump side view)

X ( um ) Y ( um )

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Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

Table 6. Bump names and locations on 76-bump WLCSP top view...continued

Alpha-numeric

designation

E11 AVDD18 1506.805 374.852

F1 VSS -1430.696 74.852

F2 GPIO[3] -1080.696 74.852

F3 GPIO[7] -618.196 74.852

F5 VSS -268.196 74.852

F7 WCI-2_SOUT 81.805 74.852

F8 WCI-2_SIN 431.805 74.852

F10 VSS 1131.805 74.852

G1 GPIO[6] -1430.696 -275.148

G2 GPIO[4] -1080.696 -275.148

G3 GPIO[5] -618.196 -275.148

G5 GPIO[14] -268.196 -275.148

G7 SLP_CLK_IN 81.805 -275.148

G8 DNC 431.805 -275.148

G10 AVDD18 1116.805 -275.148

G11 RF_TR_2 1481.805 -275.148

H1 PDn -1430.696 -625.148

H2 GPIO[1] -1080.696 -625.148

H3 GPIO[8] -618.196 -625.148

H5 VSS -268.196 -625.148

H9 VCORE 781.805 -625.148

H10 VSS 1131.805 -625.148

J1 AVDD18 -1430.696 -975.148

J2 VSS -1080.696 -975.148

J3 AVDD18 -618.196 -975.148

J5 VSS -268.196 -975.148

J7 VSS 81.805 -975.148

J8 VSS 431.805 -975.148

J9 VSS 781.805 -975.148

J10 VPA 1131.805 -975.148

J11 RF_TR_5 1481.805 -975.148

K1 GPIO[2] -1430.696 -1325.148

K2 VIO -1080.696 -1325.148

K4 XTAL_OUT -518.196 -1325.148

K6 VSS -168.196 -1325.148

Preliminary data sheet Rev. 3 — 12 March 2021

Signal name

Bump location relative to die center (non-bump side view)

X ( um ) Y ( um )

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Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

Table 6. Bump names and locations on 76-bump WLCSP top view...continued

Alpha-numeric

designation

K7 AVDD18 181.805 -1325.148

K9 VSS 781.805 -1325.148

K10 VSS 1131.805 -1325.148

L2 GPIO[15] -1080.696 -1675.148

L4 XTAL_IN -493.196 -1675.148

L6 AVDD18 -143.195 -1675.148

L9 AVDD18 781.805 -1675.148

L10 VSS 1131.805 -1675.148

Signal name

Bump location relative to die center (non-bump side view)

X ( um ) Y ( um )

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5.4 Pin types

Table 7. Pin types

Pin type Description

I/O Digital input/output

I Digital input

O Digital output

A, I Analog input

A,O Analog output

A, I/O Analog input/output

NC No connect

DNC Do not connect

Power Power

Ground Ground

IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

5.5 Pin description

5.5.1 Pin states

The pin state information provided in the tables includes:

• No Pad Power State indicates the state when there is no power.

• PwrDwn State denotes the power-down state in default configuration. Many pads have

programmable power-down values, which can be set by firmware.

• Reset State is the state after the power-on-reset state and before the hardware state

(HW State).

• HW State (hardware state) is the state after boot code finishes and before firmware

download begins (firmware may change the pin state). HW State may differ based on the pin muxing/strap setting. For example, for UART_RTSn and UART_SOUT, the boot code will enable the UART interface when the device is in SDIO-UART mode, making the HW states output high and output low, respectively.

• PwrDwn Prog indicates if the power-down state can be programmed.

• PU denotes whether the pull-up can be programmed or not.

• PD denotes whether the pull-down can be programmed or not.

• Pull-up and pull-down are only effective when the pad is in input mode.

• After firmware is downloaded, the pads (GPIO, RF control, and so on) are programmed

in functional mode per the functionality of the pins.

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Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

5.5.2 General purpose I/O (GPIO) (MFP)

Table 8. GPIO

Pins may be Multi-Functional Pins (MFP).

Pin Name Supply No Pad

GPIO[15] VIO tristate input input drive high yes nominal PU yes yes

GPIO mode: GPIO[15] (input/output) JTAG mode: JTAG_TMS - JTAG test mode select (input). See Section 5.5.13 "JTAG interface". Reset recovery mode: Independent software reset for Bluetooth subsystem (input)

GPIO[14] VIO tristate input input tristate yes nominal PU yes yes

GPIO mode: GPIO[14] (input/output) JTAG mode: JTAG_TCK - JTAG test clock (input). See Section 5.5.13 "JTAG interface". Reset recovery mode: Independent software reset for Wi-Fi subsystem (input)

GPIO[13] VIO tristate input input drive high yes nominal PU yes yes

GPIO mode: GPIO[13] (input/output) UART mode: UART_DTRn - UART data-terminal-ready (output). See Section 5.5.6 "UART host interface". Out-of-band wake-up mode: Host to IW416 Wi-Fi wake-up (input)

GPIO[12] VIO tristate input input tristate yes nominal PU yes yes

GPIO mode: GPIO[12] (input/output) UART mode: UART_DSRn - UART data-set-ready (input) (active low).See Section 5.5.6 "UART host interface". Host wake-up mode: Host to IW416 Bluetooth wake-up (input)

GPIO[11] VIO tristate output input drive high yes weak PU yes yes

GPIO mode: GPIO[11] (input/output) This pin is used as a configuration pin: CON[8] (input) See Section 5.6 "Configuration pins". UART mode: UART_RTSn - UART request-to-send (output) (active low). See Section 5.5.6 "UART host interface".

GPIO[10] VIO tristate input input tristate yes nominal PU yes yes

GPIO mode: GPIO[10] (input/output) UART mode: UART_SOUT - UART serial (output). See Section 5.5.6 "UART host interface".

GPIO[9] VIO tristate output input tristate yes nominal PU yes yes

GPIO mode: GPIO[9] (input/output) UART mode: UART_SIN - UART serial (input). See Section 5.5.6 "UART host interface".

GPIO[8] VIO tristate input input drive low yes weak PU yes yes

GPIO mode: GPIO[8] (input/output) This pin is used as a configuration pin: CON7 (input) See Section 5.6 "Configuration pins". UART mode: UART_CTSn - UART clear-to-send input signal (input, active low). See Section 5.5.6 "UART host interface".

GPIO[7] VIO tristate input input tristate yes nominal PU yes yes

GPIO mode: GPIO[7] (input/output) PCM mode: PCM_SYNC - PCM frame sync (input if slave, output if master). See Section 5.5.7 "Audio interface". I2S mode: I2S_LRCLK - I2S left-right clock (input if slave, output if master). See Section 5.5.7 "Audio interface". PTA mode: EXT_REQ - Request from the external radio (input). See Section 5.5.8 "PTA interface".

[1]

(MFP)

Power State

Reset State

HW State PwrDwn

State

PwrDwn Prog

Internal PU/PDPU PD

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Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

Table 8. GPIO

[1]

(MFP)...continued

Pins may be Multi-Functional Pins (MFP).

Pin Name Supply No Pad

Power

Reset State

HW State PwrDwn

State

PwrDwn Prog

Internal PU/PDPU PD

State

GPIO[6] VIO tristate input input tristate yes nominal PU yes yes

GPIO mode: GPIO[6] (input/output) PCM mode: PCM_CLK - PCM data clock (input if slave, output if master). See Section 5.5.7 "Audio interface". I2S mode: I2S_BCLK - I2S bit clock (input if slave, output if master). See Section 5.5.7 "Audio interface". PTA mode: EXT_PRI - External radio priority signal (input). See Section 5.5.8 "PTA interface".

GPIO[5] VIO tristate input input tristate yes weak PU yes yes

GPIO mode: GPIO[5] (input/output) PCM mode: PCM_DIN

[2]

- PCM receive signal (input). See Section 5.5.7 "Audio interface".

I2S mode: I2S_DOUT/I2S_DIN - I2S transmit/receive signal (output/input) (depending on the configuration). See

Section 5.5.7 "Audio interface".

PTA mode: EXT_GNT - External radio grant signal (output). See Section 5.5.8 "PTA interface".

GPIO[4] VIO tristate output input tristate yes nominal PU yes yes

GPIO mode: GPIO[4] (input/output) PCM mode: PCM_DOUT

[3]

- PCM transmit signal (output). See Section 5.5.7 "Audio interface".

I2S mode: I2S_DOUT/I2S_DIN (depending on the configuration. If GPIO[5] is configured as I2S_DIN, then GPIO[4] is set as I2S_DOUT, and vice-verse). See Section 5.5.7 "Audio interface".

PTA mode: EXT_FREQ - External radio frequency signal (input). See Section 5.5.8 "PTA interface". Out-of-band wake-up mode: IW416 Bluetooth to host wake-up signal (output)

[4]

GPIO[3] VIO tristate input input tristate yes weak PU yes yes

GPIO mode: GPIO[3] (input/output) Power management mode: DVSC[1], Digital voltage scaling control (output) JTAG mode: JTAG_TDO, JTAG test data (output). See Section 5.5.13 "JTAG interface". PCM mode: PCM_MCLK (output) - PCM clock signal (output, optional). See Section 5.5.7 "Audio interface". I2S mode: I2S_CCLK - I2S clock (output, optional). See Section 5.5.7 "Audio interface".

GPIO[2] VIO tristate input input tristate yes weak PU yes yes

GPIO mode: GPIO[2] (input/output) Power management mode: DVSC[0], Digital voltage scaling control (output) JTAG mode: JTAG_TDI, JTAG test data (input). See Section 5.5.13 "JTAG interface".

GPIO[1] VIO tristate input input tristate yes weak PU yes yes

GPIO mode: GPIO[1] (input/output) This pin is used as a configuration pin: CON[9] (input). See Section 5.6 "Configuration pins".

PTA mode: EXT_STATE - External radio state signal (input). See Section 5.5.8 "PTA interface". Out-of-band wake-up mode: IW416 Wi-Fi to host wake-up signal (output)

GPIO[0] VIO tristate output output drive low yes nominal PU yes yes

GPIO mode: GPIO[0] (input/output) Oscillator enable mode: XOSC_EN (output) (active high). See Section 5.5.10 "Clock interface".

[1] Not all GPIO pins can be used for Host-to-SoC wake-up signals. [2] The function can be swapped with GPIO[4] using a software command without affecting the hardware connection. [3] The function can be swapped with GPIO[5] using a software command without affecting the hardware connection. [4] If PCM and UART interfaces are used in application, use GPIO[0] as alternative for this wake-up signal

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Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

5.5.3 Wi-Fi/Bluetooth radio interface

Table 9. Wi-Fi/Bluetooth radio interface

Pin Name Type Supply Description

RF_TR_2 A, I/O AVDD18 Wi-Fi Transmit/Receive (2.4 GHz)

RF_TR_5 A, I/O AVDD18 Wi-Fi Transmit/Receive (5 GHz)

BRF_ANT A, I/O AVDD18 Bluetooth Transmit/Receive

5.5.4 Wi-Fi RF front-end control interface

Table 10. Wi-Fi RF front-end control interface

Pin Name Supply No Pad

Power State

RF_CNTL0_N VIO_RF tristate input output drive low yes weak PU no no

RF Control 0—RF Control Output Low (output) This pin is used as a configuration pin: CON[0] (input) See Section 5.6 "Configuration pins".

RF_CNTL1_P VIO_RF tristate input output drive high yes weak PU no no

RF Control 1—RF Control Output High (output) This pin is used as a configuration pin: CON[6] (input)

RF_CNTL2_N VIO_RF tristate input output drive low yes weak PU no no

RF Control 2—RF Control Output Low (output) This pin is used as a configuration pin: CON[1] (input) See Section 5.6 "Configuration pins".

RF_CNTL3_P VIO_RF tristate input output drive high yes weak PU no no

RF Control 3—RF Control Output High (output) This pin is used as a configuration pin: CON[5] (input) See Section 5.6 "Configuration pins".

Reset State

HW State PwrDwn

State

PwrDwn Prog

Internal PU/PD

PU PD

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IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

5.5.5 SDIO host interface (MFP)

Table 11. SDIO host i (MFP)

Pins may be Multi-Functional Pins (MFP). See pin descriptions for functional modes.

Pin Name Supply No Pad

Power State

SD_CLK VIO_SD tristate input input tristate no nominal PU yes yes

SDIO 4-bit mode: Clock input SDIO 1-bit mode: Clock input

SD_CMD VIO_SD tristate input input tristate no nominal PU yes yes

SDIO 4-bit mode: Command/response (input/output) SDIO 1-bit mode: Command line

SD_DAT[3] VIO_SD tristate input input tristate no nominal PU yes yes

SDIO 4-bit mode: Data line Bit[3] SDIO 1-bit mode: Reserved

SD_DAT[2] VIO_SD tristate input input tristate no nominal PU yes yes

SDIO 4-bit mode: Data line Bit[2] or read wait (optional) SDIO 1-bit mode: Read wait (optional)

SD_DAT[1] VIO_SD tristate input input tristate no nominal PU yes yes

SDIO 4-bit mode: Data line Bit[1] SDIO 1-bit mode: Interrupt

SD_DAT[0] VIO_SD tristate input input tristate no nominal PU yes yes

SDIO 4-bit mode: Data line Bit[0] SDIO 1-bit mode: Data line

Reset State

HW State PwrDwn

State

PwrDwn Prog

Internal PU/PDPU PD

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Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

5.5.6 UART host interface

Table 12. UART host interface (MFP)

Pins may be Multi-Functional Pins (MFP).

Pin Name Type Supply Description

UART_SIN I VIO UART serial input signal - muxed with GPIO[9]

UART_SOUT O VIO UART serial output signal - muxed with GPIO[10]

UART_RTSn O VIO UART request-to-send output signal (active low) - muxed with

GPIO[11]

UART_CTSn I VIO UART clear-to-send input signal (active low) - muxed with GPIO[8]

UART_DTRn O VIO UART data-terminal-ready output signal (active low) - muxed with

GPIO[13]

UART_DSRn I VIO UART data-set-ready input signal (active low) - muxed with GPIO[12]

5.5.7 Audio interface

Table 13. Audio interface pins (MFP)

Pins may be Multi-Functional Pins (MFP). See pin descriptions for functional modes.

Pin Name Type Supply Description

PCM_DIN I VIO PCM receive input signal - muxed with GPIO[4]/GPIO[5]

PCM_DOUT O VIO PCM transmit output signal - muxed with GPIO[4]/GPIO[5]

PCM_SYNC I/O VIO PCM frame sync - muxed with GPIO[7]

• Output if master

• Input if slave

PCM_CLK I/O VIO PCM data clock - muxed with GPIO[6]

• Output if master

• Input if slave

PCM_MCLK O VIO PCM clock signal (output, optional) - muxed with GPIO[3]

Optional clock used for some codecs.

I2S_DIN I VIO I2S receive input signal - muxed with GPIO[4]/GPIO[5] , depending

on the configuration.

I2S_DOUT O VIO I2S transmit output data signal - muxed with GPIO[4]/GPIO[5] ,

depending on the configuration.

I2S_LRCLK I/O VIO I2S left-right clock - muxed with GPIO[7]

• Output if master

• Input if slave

I2S_BCLK I/O VIO I2S bit clock - muxed with GPIO[6]

• Output if master

• Input if slave

I2S_CCLK O VIO I2S clock (output/optional) - muxed with GPIO[3] .

Optional clock used for some codecs.

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5.5.8 PTA interface

Table 14. PTA interface (MFP)

Pins may be Multi-Functional Pins (MFP). See pin descriptions for functional modes.

Pin Name Type Supply Description

EXT_STATE I VIO External radio state input signal - muxed with GPIO[1]

External radio traffic direction (Tx/Rx):

• 1: Tx

• 0: rx

EXT_GNT O VIO External radio grant output signal - muxed with GPIO[5]

EXT_FREQ I VIO External radio frequency input signal - muxed with GPIO[4]

Frequency overlap between external radio and Wi-Fi:

• 1: overlap

• 0: non-overlap

This signal is useful when the external radio is a frequency hopping device.

EXT_PRI I VIO External radio input priority signal - muxed with GPIO[6]

Priority of the request from the external radio. Can support 1 bit priority (sample once) and 2 bit priority (sample twice). Can also have Tx/Rx info following the priority info if EXT_STATE is not used.

EXT_REQ I VIO Request from the external radio - muxed with GPIO[7]

IW416

5.5.9 WCI-2 interface

Table 15. WCI-2 interface

Pin Name Supply No Pad

Power State

WCI-2_SIN AVDD18 tristate input input tristate no weak PU yes yes

WCI-2_SIN (input)

WCI-2_SOUT AVDD18 tristate output output tristate no weak PU yes yes

WCI-2_SOUT (output)

Reset StateHWState

PwrDwn State

PwrDwn Prog

Internal PU/PD

PU PD

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