NXP BSS84, BSS84/DG Schematic [ru]
BSS84
P-channel enhancement mode vertical DMOS transistor
Rev. 06 — 16 December 2008 Product data sheet
1. Product profile
1.1 General description
P-channel enhancement mode vertical Diffusion Metal-Oxide Semiconductor (DMOS)
transistor in a small Surface-Mounted Device (SMD) plastic package.
Table 1. Product overview
Type number
BSS84 SOT23 TO-236AB
BSS84/DG
[1] /DG: halogen-free
1.2 Features
[1]
Package
NXP JEDEC
n Low threshold voltage n Direct interface to CMOS and
Transistor-Transistor Logic (TTL)
n High-speed switching n No secondary breakdown
1.3 Applications
n Line current interrupter in telephone sets n Relay, high-speed and line transformer
drivers
1.4 Quick reference data
n VDS≤−50 V n ID≤−130 mA
n R
≤ 10 Ω n P
DSon
≤ 250 mW
tot
NXP Semiconductors
2. Pinning information
Table 2. Pinning
Pin Symbol Description Simplified outline Graphic symbol
1 G gate
2 S source
3 D drain
3. Ordering information
Table 3. Ordering information
Type number
BSS84 TO-236AB plastic surface-mounted package; 3 leads SOT23
BSS84/DG
BSS84
P-channel enhancement mode vertical DMOS transistor
3
12
SOT23 (TO-236AB)
[1]
Package
Name Description Version
G
001aaa025
D
S
4. Marking
[1] /DG: halogen-free
Table 4. Marking codes
Type number
[1]
Marking code
BSS84 13*
BSS84/DG ZV*
[1] /DG: halogen-free
[2] * = -: made in Hong Kong
* = p: made in Hong Kong
* = t: made in Malaysia
* = W: made in China
[2]
BSS84_6 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 06 — 16 December 2008 2 of 11
NXP Semiconductors
5. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DS
V
GS
I
D
I
DM
P
tot
T
stg
T
j
[1] Device mounted on a Printed-Circuit Board (PCB).
BSS84
P-channel enhancement mode vertical DMOS transistor
drain-source voltage 25 °C ≤ Tj≤ 150 °C-−50 V
gate-source voltage - ±20 V
drain current Tsp=25°C; VGS= −10 V;
see
Figure 1
= 100 °C;
T
sp
V
= −10 V
GS
peak drain current Tsp=25°C; tp≤ 10 µs;
see
Figure 1
total power dissipation Tsp=25°C; see Figure 2
storage temperature −65 +150 °C
junction temperature −65 +150 °C
- −130 mA
- −75 mA
- −520 mA
[1]
- 250 mW
3
−10
I
D
(mA)
2
−10
−10
−1
−1 −10
Tsp=25°C
(1) R
DSon
limitation
(1)
DC
−10
VDS (V)
tp =
10 µs
100 µs
1 ms
10 ms
100 ms
mld251
Fig 1. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
2
BSS84_6 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 06 — 16 December 2008 3 of 11
NXP Semiconductors
BSS84
P-channel enhancement mode vertical DMOS transistor
Fig 2. Power derating curve
6. Thermal characteristics
Table 6. Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
R
th(j-a)
thermal resistance from
junction to ambient
300
P
tot
(mW)
200
100
0
0 200
50 100 150
see Figure 3
mld199
T
(°C)
amb
[1]
- - 500 K/W
[1] Mounted on a PCB, vertical in still air.
3
10
R
th(j-a)
(K/W)
10
10
δ = 0.75
0.5
2
10
1
−1
−6
10
0.2
0.1
0.05
0.02
0.01
P
0
−5
10
−4
10
−3
10
−2
10
−1
10
110
t
p
Fig 3. Transient thermal impedance from junction to ambient as a function of pulse duration
mld250
t
p
δ =
T
T
10
t
2
tp (s)
3
10
BSS84_6 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 06 — 16 December 2008 4 of 11
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