NXP AN12943 Application Note
AN12943
Spurious interrupt on MagniV
Rev. 0 — July, 2020
by: NXP Semiconductors
Contents
1 Introduction
The S12 MagniV family of microcontrollers includes single-die solutions that
are designed to provide a complete system-in-package (SiP) built on proven
S12 technology. With the integration of High-Voltage (HV) analog features into
a standard automotive MCU, the S12 MagniV family simplifies system design
by helping to improve manufacturing efficiency and reduce bill of materials
costs.
The S12Z CPU has taken advantage of this reduced need for absolute object
code compatibility to focus on improved support for C code-size efficiency and overall performance. The most obvious change
has been to eliminate the paged memory model and 64-kilobyte CPU addressing limitation of the CPU12 in favor of a linear 16megabyte address space. The X and Y index registers, as well as the stack pointer (SP) and program counter (PC), were
expanded from 16 bits to 24 bits to match the width of the address bus. The next biggest change has been to replace the 8-bit
A and B accumulators (sometimes used as the 16-bit D accumulator), with a set of eight general purpose data registers (Di ). D0
and D1 are 8 bits, D2 through D5 are 16 bits, and D6 and D7 are 32 bits.
1 Introduction ........................................... 1
2 S12Z features........................................ 1
3 Exceptions of S12Z................................2
4 Exception processing flow..................... 2
5 Solution to avoid spurious interrupt....... 4
6 Summary............................................... 4
Application Note
As in previous generations of CPU12, the S12Z CPU has variable-length instructions ranging from a single byte to several bytes.
The longest instructions in the CPU12 were moves with two extended addressing mode operand addresses (6 bytes of object
code). Moves could have indexed addressing mode operands, but only indexed modes that did not require additional extension
bytes. The S12Z CPU allows complete flexibility in specifying the addresses for move instructions so if both operands use an
indexed postbyte plus three extension bytes, these instructions can take up to nine bytes of object code. The longest instructions
in the S12Z CPU are the most complex math instructions (DIV, MAC, and MOD) which are page 2 opcodes plus a math postbyte
plus two operand addresses which could each be an addressing mode postbyte plus 3 extension bytes (11 bytes total).
The CPU12 used postbytes for indexed addressing, transfer/exchange, and looping primitive instructions. The S12Z CPU
instruction set has expanded the use of postbytes to improve code-size efficiency. The indexed postbyte was re-worked into a
general operand (OPR) addressing system. This new addressing mode postbyte includes indexed addressing modes like the
CPU12 and extended addressing modes, a quick-immediate mode, and register-as-memory addressing mode.
In addition to this general OPR addressing postbyte, the S12Z instruction set uses postbytes for transfer/exchange, looping
primitives, math (MUL, DIV, MAC, and MOD), relative addressing, shifts, bit-field instructions, and push/pull.
2 S12Z features
The S12Z CPU is the latest generation of CPU in the CPU12 line. This high-speed 16-bit processor has an expanded programmers
model with 24-bit wide X, Y, SP, and PC registers and replaces the A, B, and D accumulators with a set of eight general purpose
registers Di . Improved addressing modes support efficient use of the 16-megabyte (24-bit) linear address space.
• 24-Bit Linear Address Space (16-megabytes)
• 24-Bit Index Registers (X and Y), Stack Pointer (SP), and Program Counter (PC)
• Eight General Purpose Data Registers (D0, D1 8-Bits; D2–D5 16-Bits; D6, D7 32-Bits)
• Separate Memory Access Controllers for Code and Data
• Variable-Length Instructions Including Single-Byte and Odd Number of Bytes
• Extensive Use of Instruction Postbytes to Optimize Code-Size Efficiency
NXP Semiconductors
Exceptions of S12Z
3 Exceptions of S12Z
Exceptions are events that require processing outside the normal flow of instruction execution. Central Processor Unit (CPU)
exceptions on the S12Z CPU include:
1. Reset
2. Software exceptions:
• Unimplemented page 1 opcode trap (SPARE)
• Unimplemented page 2 opcode trap (TRAP)
• Software interrupt instruction (SWI)
• System call interrupt instruction (SYS)
3. Machine exception
4. A non-maskable (X-bit) interrupt
5. Maskable (I-bit) interrupts
Each exception has an associated 24-bit vector, which points to the memory location where the routine that handles the exception
is located. The 24-bit exception vectors are taken from a vector table.
Figure 1. Example of exception vector map and priority
The S12Z CPU can handle up to 128 exception vectors, but the number actually used varies from device to device, and some
vectors are reserved for NXP use.
Exceptions can be classified into different categories, depending on the effect of the different ways to mask interrupts.
1. Reset.: This exception is not maskable.
2. Software exceptions: These include the unimplemented op-code traps, the SWI instruction and the SYS instruction.
Software exceptions are not maskable.
3. Machine exception: A machine exception cannot be masked. Sources for a machine exception are defined in the Memory
Map Control module (MMC). Please refer to the MMC chapter in the MCU ReferenceManual for details.
4. X-bit interrupt: The interrupt service requests from the XIRQ pin is handled as a X-bit interrupt. This exception can be
masked with the X-bit (X=1). The I-bit and the IPL-bits have no effect.
5. All remaining interrupt service requests can be masked with the I-bit (I=1) and are subject to priority filtering using the IPLbits.
4 Exception processing flow
The first cycle in the exception processing flow for all S12Z CPU exceptions is the same, regardless of the source of the exception.
Between the first and second cycles of execution, the CPU chooses one of four alternative paths. The first path is for reset, the
Spurious interrupt on MagniV, Rev. 0, July, 2020
Application Note 2 / 5
Loading...