NXP AN12868 Application Note
AN12868
Camera Interface in LPC55(S)xx
Rev. 1 — 10/2020
1 How to read this application note
This application note introduces a parallel interface for the camera solution
for LPC55(S)xx. It includes the introduction of camera interface, features and
API routines, and demo.
2 Target application
The camera interface can be used as important part of many camera usage
as below:
• Object detection
• Gesture recognition
• Color recognition
• QR code scanning, and so on
3 Introduction of camera interfaces
A typical camera interface supports at least one parallel interface, although
nowadays many camera interfaces begin to support the MIPI CSI interface.
The camera interface's parallel interface consists of the following lines:
• Data line (D[0:11]):
These are parallel data lines that carry pixel data. The data transmitted on
these lines change with every Pixel Clock (PCLK).
Application Note
Contents
1 How to read this application note.... 1
2 Target application............................1
3 Introduction of camera interfaces....1
4 Features of camera interface.......... 1
5 Function description........................ 2
5.1 Camera interface engine............. 2
5.2 Camera driver library................... 2
5.3 LCD display..................................2
5.4 System clock................................2
5.5 Clock source of camera............... 2
5.6 I2C interface................................. 2
5.7 Memory usage............................. 2
5.8 Other supported camera modules
.....................................................2
6 Pin description.................................3
6.1 Connection of interface................4
6.2 Requirement of interface............. 4
7 Library and API routine................... 4
7.1 Library..........................................4
7.2 API routine................................... 4
7.3 API routine description.................5
7.4 Code detail description................ 5
8 Demonstration.................................7
9 Revision history...............................8
A Purchasing LCD module used in this
demo............................................... 8
• Horizontal Sync (HSYNC)
This is a special signal that goes from the camera sensor. An HSYNC indicates that one line of the frame is transmitted.
• Vertical Sync (VSYNC)
This signal is transmitted after the entire frame is transferred. This signal is often a way to indicate that one entire frame
is transmitted.
• Pixel Clock (PCLK)
This is the pixel clock and it changes on every pixel.
The application note only focuses on Digital-Video-Port (DVP) interface which is parallel interface.
4 Features of camera interface
• Supported formats (8-bit): RGB565
• Maximum image transfer rate: 30 fps for QVGA(320 × 240). For small RAM parts, reduce the size of image and frame
rate.
NXP Semiconductors
Function description
• Camera module tested : OV7673
• Other camera modules can be supported as long as they provide the same signal timing.
5 Function description
5.1 Camera interface engine
There is a hidden co-processor in LPC55S69 which can handle the signals of camera.
It reads the data from camera and stores the data in the RAM which can then be accessed by ARM core. Before using the
co-processor, some configurations need to be made, which includes pin configuration, clock enable, processor enable, interrupt
enable and so on.
5.2 Camera driver library
The instructions of co-processor use the type of machine code. The code implements the function of camera interface protocol
and is released in lib. Some API routines are provided in this application. User can use API routines to initialize the engine and
configure the pins.
5.3 LCD display
The application note uses LCD to display the video stream from camera in real time. The high-speed SPI port is used for LCD
driving port. The max speed on the SPI bus is 50 Mbps, so it can display the 320 × 240 resolution LCD up to 30 fps.
5.4 System clock
The camera engine shares the system clock with Arm® core. To speed up the processing time, the system clock must be
configured to 150 MHz. For those below 150 MHz, such as, 96 MHz system clock part, reduce the frequency of pixel clock.
5.5 Clock source of camera
The camera needs a 50 MHz clock source which can be provided by CLKOUT signal from MCU.
5.6 I2C interface
The camera is configured through I2C interface which can be connected with I2C peripheral port in the MCU.
5.7 Memory usage
The 320 × 240 resolution picture requires 150 K bytes RAM space. The solution uses the space address from 0x20010000
to 0x20035800.
Additionally, the instruction codes of camera engine need be run in the RAM for high performance. This solution uses the space
address from 0x20040000 to 0x20043FFF to store camera engine code.
5.8 Other supported camera modules
Other camera modules can be supported as long as they provide the same signal timing.
1. The camera module need to be configured as RGB565 mode with the timing diagram, as shown in Figure 1.
Camera Interface in LPC55(S)xx, Rev. 1, 10/2020
Application Note 2 / 9
NXP Semiconductors
Pin description
Figure 1. Camera module configuration
2. The resolution should be configured as QVGA (320 × 240).
6 Pin description
Camera Interface in LPC55(S)xx, Rev. 1, 10/2020
Application Note 3 / 9
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