NXP 74ABT 125D-SMD Datasheet

74ABT125

Quad buffer; 3-state

Rev. 3 — 29 April 2008 Product data sheet

1. General description

The 74ABT125 high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.

The 74ABT125 device is a quad buffer that is ideal for driving bus lines. The device
features four Output Enables (1OE, 2OE, 3OE, 4OE), each controlling one of the 3-state
outputs.

2. Features

n Quad bus interface
n 3-state buffers
n Live insertion and extraction permitted
n Output capability: HIGH −32 mA; LOW +64 mA
n Power-up 3-state
n inputs are disabled during 3-state mode
n Latch-up protection exceeds 500 mA per JESD78 class II level A
n ESD protection:

u HBM JESD22-A114E exceeds 2000 V
u MM JESD22-A115-A exceeds 200 V

3. Ordering information

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74ABT125N −40 °C to +85 °C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74ABT125D −40 °C to +85 °C SO14 plastic small outline package; 14 leads;

body width 3.9 mm

74ABT125DB −40 °C to +85 °C SSOP14 plastic shrink small outline package; 14 leads;

body width 5.3 mm

74ABT125PW −40 °C to +85 °C TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

74ABT125BQ −40 °C to +85 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very

thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm

SOT108-1

SOT337-1

SOT402-1

SOT762-1

NXP Semiconductors

4. Functional diagram

74ABT125

Quad buffer; 3-state

2

1
5

4
9

10
12

13

1A 1Y

1OE
2A 2Y

2OE
3A 3Y

3OE
4A 4Y

4OE

mna228

3

2

6

8

11

1
5

4

9
10
12
13

EN1

1

mna229

3

6

8

nA

11

nOE

mna227

Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one buffer)

5. Pinning information

5.1 Pinning

74ABT125

1OE
1

GND

7

GND

CC

V
14

(1)

8
3Y

001aai028

74ABT125

1

1OE V

2

1A 4OE

3

1Y 4A

4

2OE 4Y

5

2A 3OE

6

2Y 3A

7

GND 3Y

001aai027

14
13
12
11
10

9
8

CC

terminal 1

index area

2 13

1A 4OE

3 12

1Y 4A

4 11

2OE 4Y

5 10

2A 3OE

6 9

2Y 3A

Transparent top view

nY

Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14 Fig 5. Pin configuration DHVQFN14

5.2 Pin description

Table 2. Pin description

Symbol Pin Description

OE to 4OE 1, 4, 10, 13 output enable input (active LOW)

1
1A to 4A 2, 5, 9, 12 data input
1Y to 4Y 3, 6, 8, 11 data output
GND 7 ground (0 V)
V

CC

74ABT125_3 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 3 — 29 April 2008 2 of 14

14 supply voltage

NXP Semiconductors

6. Functional description

74ABT125

Quad buffer; 3-state

Table 3. Function selection

[1]

Inputs Output
nOE nA nY

LLL
LHH
HXZ

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.

7. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

V

CC

V

I

V

O

I

IK

I

OK

I

O

T

j

T

stg

P

tot

supply voltage −0.5 +7.0 V
input voltage −1.2 +7.0 V
output voltage output in OFF-state or HIGH-state −0.5 +5.5 V
input clamping current VI < 0 V −18 - mA
output clamping current VO < 0 V −50 - mA
output current output in LOW-state - 128 mA
junction temperature
storage temperature −65 +150 °C
total power dissipation T

[1]

= −40 °C to +85 °C

amb

[2]

- 150 °C

[3]

- 500 mW

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction

temperatures which are detrimental to reliability.

[3] For SO14 packages: above 70 °C derate linearly with 8 mW/K.

For SSOP14 and TSSOP20 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 °C derate linearly with 4.5 mW/K.

8. Recommended operating conditions

Table 5. Operating conditions

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

V

CC

V

I

V

IH

V

IL

I

OH

I

OL

∆t/∆V input transition rise and fall rate - 10 ns/V
T

amb

74ABT125_3 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 3 — 29 April 2008 3 of 14

supply voltage 4.5 5.5 V
input voltage 0 V

CC

V
HIGH-level input voltage 2.0 - V
LOW-level Input voltage - 0.8 V
HIGH-level output current −32 - mA
LOW-level output current - 64 mA

ambient temperature in free air −40 +85 °C

NXP Semiconductors

74ABT125

Quad buffer; 3-state

9. Static characteristics

Table 6. Static characteristics

Symbol Parameter Conditions 25 °C −40 °C to +85 °C Unit

Min Typ Max Min Max

V

IK

V

OH

V

OL

I

I

I

OFF

I

O(pu/pd)

I

OZ

I

LO

I

O

I

CC

∆I

CC

C

I

C

O

input clamping voltage VCC = 4.5 V; IIK= −18 mA - −0.9 −1.2 - −1.2 V
HIGH-level output

voltage

LOW-level output
voltage

VI = VIL or V

IH

VCC = 4.5 V; IOH= −3 mA 2.5 2.9 - 2.5 - V

= 5.0 V; IOH= −3 mA 3.0 3.4 - 3.0 - V

V

CC

= 4.5 V; IOH= −32 mA 2.0 2.4 - 2.0 - V

V

CC

VCC = 4.5 V; IOL= 64 mA;
V

I=VIL

or V

IH

- 0.35 0.55 - 0.55 V

input leakage current VCC = 5.5 V; VI= GND or 5.5 V - ±0.01 ±1.0 - ±1.0 µA
power-off leakage

VCC = 0.0 V; VI or VO≤ 4.5 V - ±5.0 ±100 - ±100 µA

current
power-up/power-down

output current
OFF-state output

current

VCC = 2.1 V; VO= 0.5 V;
V

= GND or VCC; OE = don’t care

I

VCC = 5.5 V; VI = VIL or V

IH

VO = 2.7 V - 1.0 50 - 50 µA

= 0.5 V - −1.0 −50 - −50 µA

V

O

output leakage current HIGH-state; VO= 5.5 V;

V

= 5.5 V; VI= GND or V

CC

output current VCC = 5.5 V; VO = 2.5 V
supply current VCC = 5.5 V; VI = GND or V

CC

CC

[1]

- ±5.0 ±50 - ±50 µA

- 5.0 50 - 50 µA

[2]

−50 −100 −180 −50 −180 mA

outputs HIGH-state - 65 250 - 250 µA
outputs LOW-state - 12 15 - 30 mA
outputs disabled - 65 250 - 50 µA

additional supply
current

per control pin; VCC = 5.5 V;
one control input at 3.4 V, other
inputs at V

or GND

CC

[3]

outputs enabled - 0.5 1.5 - 1.5 mA
outputs disabled - 50 250 - 250 mA

one enable input at 3.4 V and other
inputs at V

or GND; outputs

CC

- 0.5 1.5 - 1.5 mA

disabled

input capacitance VI = 0 V or V

CC

output capacitance outputs disabled; VO= 0 V or V

CC

-4-- - pF

-7-- - pF

[1] This parameter is valid for any VCCbetween 0 V and 2.1 V, with a transition time of up to 10 ms. FromVCC= 2.1 V to VCC=5V± 10 %,

a transition time of up to 100 ms is permitted.
[2] Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
[3] This is the increase in supply current for each input at 3.4 V.

74ABT125_3 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 3 — 29 April 2008 4 of 14

NXP Semiconductors

74ABT125

Quad buffer; 3-state

10. Dynamic characteristics

Table 7. Dynamic characteristics

GND = 0 V. For test circuit, see Figure 8.

Symbol Parameter Conditions 25 °C; VCC= 5.0 V −40 °C to +85 °C;

V

= 5.0 V ± 0.5 V

CC

Min Typ Max Min Max

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

LOW to HIGH
propagation delay

HIGH to LOW
propagation delay

OFF-state to HIGH
propagation delay

OFF-state to LOW
propagation delay

HIGH to OFF-state
propagation delay

LOW to OFF-state
propagation delay

nA to nY, see Figure 6 1.0 2.8 4.1 1.0 4.6 ns

nA to nY; see Figure 6 1.0 3.1 4.6 1.0 4.9 ns

nOE to nY; see Figure 7 1.0 3.2 5.0 1.0 5.9 ns

nOE to nY; see Figure 7 1.0 4.2 6.2 1.0 6.8 ns

nOE to nY; see Figure 7 1.0 4.1 5.4 1.0 6.2 ns

nOE to nY; see Figure 7 1.5 2.8 5.0 1.5 5.5 ns

Unit

11. Waveforms

V

I

nA input

GND

V

OH

nY output

V

OL

Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.

Fig 6. Propagation delay input (nA) to output (nY)

V

M

t

PHL

V

M

t

PLH

mna230

74ABT125_3 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 3 — 29 April 2008 5 of 14