NXP 35FS4500, 35FS6500 Product short data sheet

35FS4500, 35FS6500: ASIL B

Grade 0 safety power system basis chip with CAN FD transceiver

Rev. 2 — 14 April 2021 Product short data sheet

1 General description

The 35FS4500/35FS6500 ASIL B SMARTMOS devices are a multi-output, power supply, integrated circuit, including CAN Flexible Data (FD) transceiver, dedicated to the automotive market.

Multiple switching and linear voltage regulators, including low-power mode (32 μA) are available with various wake-up capabilities. An advanced power management scheme is implemented to maintain high efficiency over a wide range of input voltages (down to

2.7 V) and output current ranges (up to 1.5 A).

The 35FS4500/35FS6500 ASIL B includes configurable fail-safe/fail silent safety behavior and features, with two fail-safe outputs, becoming a full part of a safety oriented system partitioning, to reach a high integrity safety level (up to ASIL B).

The built-in CAN FD interface fulfills the ISO 11898-2

(11)

and -5

(12)

standards.

High temperature capability up to TA = 150 °C and TJ = 175 °C, compliant with AECQ100 Grade 0 automotive qualification.

2 Features and benefits

• Battery voltage sensing and MUX output pin

• Highly flexible SMPS pre-regulator, allowing two topologies: non-inverting buck-boost

and standard buck

• Family of devices to supply MCU core from 1.0 V to 5.0 V, with SMPS (0.8 A or 1.5 A)

or LDO (0.5 A)

• Linear voltage regulator dedicated to auxiliary functions, or to sensor supply (V

tracker or independent), 5.0 V, or 3.3 V

• Linear voltage regulator dedicated to MCU Analog/Digital (A/D) reference voltage or

I/Os supply (V

• 3.3 V keep alive memory supply available in low-power mode

• Long duration timer, counting up to 6 months with 1.0 s resolution

• Multiple wake-up sources in low-power mode: CAN, IOs, LDT

• Five configurable I/Os

3 Applications

• TA up to 150 °C and TJ up to 175 °C

• Drive Train Electrification (BMS, Hybrid EV and HEV, Inverter, DC-DC, Alterno Starter)

• Drive Train - Chassis and Safety (Active Suspension, Steering, Safety Domain

Gateway)

• Power Train (EMS, TCU, Gear Box)

• ADAS (LDW, Radar, Sensor Fusion Safety area)

), 5.0 V, or 3.3 V

CCA

NXP Semiconductors

G

AT

E

_

L

S

V

P

R

E

S

W

_

CO

R

E

BO

O

T

_

C

O

R

E

V

CO

R

E

_

S

N

S

FB_COR E

COMP_CORE

FCRBM

VCCA_ E

VCCA_ B

VDDIO

VCCA

MUX_OUT

IO_5/VKA M

MOSI

MISO

SCLK

NCS

INTB

RSTB

TXD

RXD

IO_2

IO_3

BO

O

T

_

P

R

E

SW

_

P

R

E

2

SW

_

P

R

E

1

VS

UP

2

VS

UP

1

VSUP3

VSENSE

VAUX_E

VAUX_B

VAUX

SELECT

CAN-5 V

DEBUG

IO_0

IO_4

CANH

CANL

VPU-F S

+batter y

(KL30)

DEBUG

mode

ignition key

(KL15)

to switch

CAN BUS

fail-s afe

delay

fail-s afe

drive

V

AUX

V

PRE

V

DDIO

V

PRE

V

CORE

VDD

AD ref. voltage

ADC Input

Vstandby

SPI

NMI

Reset

CAN

MCU

V

CCA

V

DDIO

V

CORE

or

V

CCA

FS1B

FS0B

GNDA DGNDGND_COM

35FS65 00C

aaa-03 9989

Grade 0 safety power system basis chip with CAN FD transceiver

• On board charger

• Motor control

4 Simplified application diagrams

35FS4500, 35FS6500: ASIL B

Figure 1. 35FS6500C simplified application diagram - buck boost configuration - FS1B

Product short data sheet Rev. 2 — 14 April 2021

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NXP Semiconductors

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G

A

TE

_

L

S

V

P

R

E

S

W_

C

O

R

E

B

OO

T_

C

O

R

E

V

C

O

R

E

_

S

N

S

FB_CORE

COMP_CORE

FCRBM

VCCA_E

VCCA_B

VDDIO

VCCA

MUX_OUT

IO_5/VKAM

MOSI

MISO

SCLK

NCS

INTB

RSTB

TXD

RXD

IO_2

IO_3

B

OO

T_

P

R

E

S

W_

P

R

E

2

S

W_

P

R

E

1

V

S

U

P

2

V

S

U

P

1

VSUP3

VSENSE

VAUX_E

VAUX_B

VAUX

SELECT

CAN-5V

DEBUG

IO_0

IO_4

CANH

CANL

VPU-FS

+battery

(KL30)

DEBUG

mode

ignition key

(KL15)

to switch

CAN BUS

fail-safe

delay

fail-safe

drive

V

AUX

V

PRE

V

DDIO

V

PRE

V

CORE

VDD

AD ref. voltage

ADC Input

Vstandby

SPI

NMI

Reset

CAN

MCU

V

CCA

V

DDIO

V

CORE

or

V

CCA

FS1B

FS0B

GNDA DGNDGND_COM

35FS4500C

35FS4500, 35FS6500: ASIL B

Grade 0 safety power system basis chip with CAN FD transceiver

Figure 2. 35FS4500C simplified application diagram - buck boost configuration - FS1B

5 Ordering information

5.1 Part number definition

MC35FS c 5 x y z AE/R2

Table 1. Part number breakdown

Code Option Variable Description

4 series Linearc

6 series

Product short data sheet Rev. 2 — 14 April 2021

y

0 0.5 A or 0.8 Ax

1

5 None

6 FS1B

7 LDT

8

N Nonez

C

V

type

CORE

V

current

CORE

Functions

Physical interface

FS1B and LDT

DC-DC

1.5 A

CAN FD

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NXP Semiconductors

35FS4500, 35FS6500: ASIL B

Grade 0 safety power system basis chip with CAN FD transceiver

5.2 Part numbers list

Table 2. Orderable part variations

Part Number Temperature

MC35FS4505NAE 0 0 0.5 A Linear by SPI 0 B

MC35FS4505CAE 0 0 0.5 A Linear by SPI 1 B

MC35FS4506NAE 1 0 0.5 A Linear by SPI 0 B

MC35FS4506CAE 1 0 0.5 A Linear by SPI 1 B

MC35FS4507NAE 0 1 0.5 A Linear by SPI 0 B

MC35FS4507CAE 0 1 0.5 A Linear by SPI 1 B

MC35FS4508NAE 1 1 0.5 A Linear by SPI 0 B

MC35FS4508CAE 1 1 0.5 A Linear by SPI 1 B

MC35FS6505NAE 0 0 0.8 A DC-DC by SPI 0 B

MC35FS6505CAE 0 0 0.8 A DC-DC by SPI 1 B

MC35FS6506NAE 1 0 0.8 A DC-DC by SPI 0 B

MC35FS6506CAE 1 0 0.8 A DC-DC by SPI 1 B

MC35FS6507NAE 0 1 0.8 A DC-DC by SPI 0 B

MC35FS6507CAE 0 1 0.8 A DC-DC by SPI 1 B

MC35FS6508NAE 1 1 0.8 A DC-DC by SPI 0 B

MC35FS6508CAE 1 1 0.8 A DC-DC by SPI 1 B

MC35FS6515NAE 0 0 1.5 A DC-DC by SPI 0 B

MC35FS6515CAE 0 0 1.5 A DC-DC by SPI 1 B

MC35FS6516NAE 1 0 1.5 A DC-DC by SPI 0 B

MC35FS6516CAE 1 0 1.5 A DC-DC by SPI 1 B

MC35FS6517NAE 0 1 1.5 A DC-DC by SPI 0 B

MC35FS6517CAE 0 1 1.5 A DC-DC by SPI 1 B

MC35FS6518NAE 1 1 1.5 A DC-DC by SPI 0 B

MC35FS6518CAE

(TA)

–40 °C to

150 °C

Package FS1B LDT VCORE VCORE

type

48-pin LQFP exposed pad

1 1 1.5 A DC-DC by SPI 1 B

VKAM On CANFDASIL Notes

[1]

[1] To order parts in tape and reel, add the R2 suffix to the part number.

Product short data sheet Rev. 2 — 14 April 2021

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NXP Semiconductors

aaa-037810

VSUP3

VSUP1

VSUP2

SW_PRE1

SW_PRE2

BOOT_PRE

GATE_LS

VPRE

DGND

Vpre

select

debug

MIFO_FS

Vsup3

(1)

Vsup3

Vsup3Vpre

Vpre

Vsup3

Vsup_mon

Vsense_mon

CAN diag

Vpre

Vsense

Vref

(2.5 V)

SW_CORE

FB_CORE

VCORE_SNS

BOOT_CORE

COMP_CORE

VCCA_E

VCCA_B

VCCA

GNDA

MUX_OUT

DEBUG

INTB

NCS

SCLK

MOSI

MISO

VDDIO

VSENSE

RXD

TXD

RSTB

FS0B

FS1B

VPU_FS

VAUX_E

VAUX_B

VAUX

CAN-5V

SELECT

IO_0

IO_2

IO_3

IO_4

IO_5/VKAM

VKAM

FCRBM

CANH

CANL

GND_COM

Vpre SMPS

TSD

Vaux LINEAR REGULATOR

TSD

Vcore SMPS

Vcca LINEAR REGULATOR

ANALOG

REFERENCE #1

POWER

MANAGEMENT

STATE

MACHINE

LONG

DURATION

TIMER

TSD

CHARGE

PUMP

V2p5d

MAIN

V2p5d

FS

OSC

MAIN

VKAM

SPI

MAIN

MUX

INTERFACE

Vcan

LINEAR REGULATOR

CAN-5 V

FB_core

Vaux Vcca

Die

Temp

I/Os

INTERFACE

(1)

SPI

FS

OSC

FS

ANALOG REFERENCE #2

FS

CAN FLEXIBLE DATA INTERFACE

(1)

fail safe logic and supply

part number dependent

(1)

VOLTAGE REGULATOR SUPERVISOR

(OVER AND

UNDERVOLTAGE)

FAIL SAFE

MACHINE

FS1B DELAY AND DRIVER

5

6 Block diagram

35FS4500, 35FS6500: ASIL B

Grade 0 safety power system basis chip with CAN FD transceiver

Figure 3. 35FS4500/35FS6500 with CAN simplified internal block diagram

Product short data sheet Rev. 2 — 14 April 2021

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NXP Semiconductors

VSUP1 BOOT_CORE

VSUP2 SW_CORE

VSENSE VCORE _SNS

VSUP3 COMP_CORE

FS1B FB_CORE

GND_C OM SELECT

CAN_ 5V VDDIO

CANH INTB

CANL NCS

IO_4 SCLK

IO_5/ VK AM MOSI

IO_0 MISO

FCRBM

S

W

_

P

R

E

1

FS0B

S

W

_

P

R

E

2

DE

BUG

B

O

T

_

P

R

E

AGND

DG

N

D

MUX _OUT

GA

T

E

_

L

S

IO_2

V

C

A

IO_3

V

C

A

_

B

TXD

V

C

A

_

E

RXD

VA

U

X

_

E

VP

U_FS

VA

U

X

_

B

n.c

.

RSTB

VA

U

X

VP

R

E

aaa- 03773 4

1

2

3

4

5

6

7

8

9

10

11

12

36

35

34

33

32

31

30

29

28

27

26

25

131415161718192021

22

23

48

4

7

464544

43

4

241

403938

3

724

VSUP1 BOOT_CORE

VSUP2 SW_CORE

VSENSE VCORE _SNS

VSUP3 COMP_CORE

n.c. FB_CORE

GND_C OM SELECT

CAN_ 5V VDDIO

n.c INTB

n.c NCS

IO_4 SCLK

IO_5/ VK AM MOSI

IO_0 MISO

FCRBM

S

W

_

P

R

E

1

FS0B

S

W

_

P

R

E

2

DE

BUG

B

O

T

_

P

R

E

AGND

DG

N

D

MUX _OUT

GA

T

E

_

L

S

IO_2

V

C

A

IO_3

V

C

A

_

B

n.c.

V

C

A

_

E

n.c

.

VA

U

X

_

E

n.c

.

VA

U

X

_

B

n.c

.

RSTB

VA

U

X

VP

R

E

aaa- 03773 6

1

2

3

4

5

6

7

8

9

10

11

12

36

35

34

33

32

31

30

29

28

27

26

25

131415161718192021

22

23

48

4

7

464544

43

4

241

403938

3

724

7 Pinning information

7.1 Pinning information

35FS4500, 35FS6500: ASIL B

Grade 0 safety power system basis chip with CAN FD transceiver

Figure 4. 35FS6500 pinout with CAN and FS1B

Figure 5. 35FS6500 pinout without CAN

Product short data sheet Rev. 2 — 14 April 2021

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NXP Semiconductors

VSUP1 n.c.

VSUP2 VCORE

VSENSE VCORE _SNS

VSUP3 n.c.

FS1B FB_CORE

GND_C OM SELECT

CAN_ 5V VDDIO

CANH INTB

CANL NCS

IO_4 SCLK

IO_5/ VK AM MOSI

IO_0 MISO

FCRBM

S

W

_

P

R

E

1

FS0B

S

W

_

P

R

E

2

DE

BUG

B

O

T

_

P

R

E

AGND

DG

N

D

GA

T

E

_

L

S

IO_2

V

C

A

IO_3

V

C

A

_

B

TXD

V

C

A

_

E

RXD

VA

U

X

_

E

VP

U_FS VA

U

X

_

B

n.c.

RSTB

VA

U

X

VP

R

E

aaa- 037737

1

2

3

4

5

6

7

8

9

10

11

12

36

35

34

33

32

31

30

29

28

27

26

25

131415161718192021

22

23

48

4

7

464544

43

4

241

403938

3

724

35FS4500, 35FS6500: ASIL B

Grade 0 safety power system basis chip with CAN FD transceiver

Figure 6. 35FS4500 pinout with CAN and FS1B

Product short data sheet Rev. 2 — 14 April 2021

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NXP Semiconductors

35FS4500, 35FS6500: ASIL B

Grade 0 safety power system basis chip with CAN FD transceiver

7.2 Pin description

A functional description of each pin can be found in the full data sheet.

Table 3. 35FS4500/35FS6500 pin definition

Pin number

1 VSUP1 A_IN Power supply of the device. An external reverse battery protection diode in series is

2 VSUP2 A_IN Second power supply. Protected by the external reverse battery protection diode

3 VSENSE A_IN Sensing of the battery voltage. Must be connected prior to the reverse battery

4 VSUP3 A_IN Third power supply dedicated to the device supply. Protected by the external

5 FS1B D_OUT Second output of the safety block (active low). The pin is asserted low at start-up

6 GND_COM GROUND Dedicated ground for physical layers

7 CAN_5V A_OUT Output voltage for the embedded CAN FD interface

8 CANH A_IN/OUT CAN output high. If CAN function is not used, this pin must be left open.

9 CANL A_IN/OUT CAN output low. If CAN function is not used, this pin must be left open.

10 IO_4 D_IN

11 IO_5/VKAM A_IN

12 IO_0 A_IN

13 FCRBM A_IN Feedback core resistor bridge monitoring: For safety purposes, this pin is used to

14 FS0B D_OUT First output of the safety block (active low). The pin is asserted low at start-up and

Pin name Type Definition

mandatory

used for VSUP1. VSUP1 and VSUP2 must be connected together externally.

protection diode.

reverse battery protection diode used for VSUP1. Must be connected between the reverse protection diode and the input PI filter.

and when a fault condition is detected, with a configurable delay or duration versus FS0B output terminal. Open drain structure.

Can be used as digital input (load dump proof) with wake-up capability or as an

A_OUT

D_IN A_OUT

D_IN

output gate driver Digital input: Pin status can be read through the SPI. Can be used to monitor error

signals from another IC for safety purposes (when used with IO_5).

Wake-up capability: Can be selectable to wake-up on edges or levels. Output gate driver: Can drive a logic level low-side NMOS transistor. Controlled by

the SPI.

Can be used as digital input with wake-up capability or as an analog output providing keep alive memory supply in low-power mode.

Analog input: Pin status can be read through the MUX output terminal Digital input: Pin status can be read through the SPI. Can be used to monitor error

signals from another IC for safety purposes (when used with IO_4).

Wake-up capability: Can be selectable to wake-up on edges or levels. Supply output: Provide keep alive memory supply in low-power mode

Can be used as analog or digital input (load dump proof) with wake-up capability (selectable)

Analog input: Pin status can be read through the MUX output terminal Digital input: Pin status can be read through the SPI. Wake-up capability: Can be selectable to wake-up on edges or levels.

monitor the middle point of a redundant resistor bridge connected on V parallel to the one used to set the V connected directly to FB_CORE.

when a fault condition is detected. Open drain structure.

voltage). If not used, this pin must be

CORE

(in

Product short data sheet Rev. 2 — 14 April 2021

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