NSC NS486SXF-25 Datasheet

TL/EE12514

NS486SXF Optimized 32-Bit 486-Class Controller

with On-Chip Peripherals for Embedded Systems

ADVANCE INFORMATION

February 1997

NS486TMSXF Optimized 32-Bit 486-Class Controller
with On-Chip Peripherals for Embedded Systems

General Description

The NS486SXF is a highly integrated embedded system
controller incorporating an Intel486

TM

-class 32-bit proces­sor, all of the necessary System Service Elements, and a
set of peripheral I/O controllers tailored for embedded con­trol systems. It is ideally suited for a wide variety of applica­tions running in a segmented protect-mode environment.

Key Features

Y

100% compatible with VxWorksÉ, VRTXÉ, QNXÉNeu­trino, pSOS

a

TM

, and other popular real-time executives

and operating system kernels

Y

Intel486 instruction set compatible (protected mode
only) with optimized performance

Y

CPU includes a 1 Kbyte Instruction Cache

Y

Operation at 25 MHz with 5V supply

Y

Low cost 160-pin PQFP package

Y

Industry standard interrupt controller, timers, real time
clock, UART with IrDA v1.0 (Infrared Data Association)
port

Y

Intel 82365 compatible PCMCIA interface

Y

Protected WATCHDOGTMtimer

Y

Optimized DRAM Controller (supports two banks, up to
8 Mbytes each)

Y

Up to nine versatile, programmable chip selects

Y

Glueless interface to ISA peripherals

Y

Arbitration support for auxiliary processor

Y

Four external DMA channels (max. transfer rate of 25
MByte/sec

@

25 MHz) support many transfer modes

Y

High performance IEEE 1284 (ECP) Bidirectional
Parallel Port

Y

MICROWIRETM/Access.bus synchronous serial
interfaces

Y

LCD Controller for an up to 4 grey scale supertwist
Liquid Crystal Displays up to 480 X 320

Y

Reconfigurable I/O: Up to 29 I/O pins can be used as
general purpose bidirectional I/O lines

Y

Flexible, programmable, multilevel power saving modes
maximize power savings

NS486SXF Single-Chip Embedded Controller

TL/EE/12514– 1

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
NS486

TM

, WATCHDOGTMand MICROWIRETMare trademarks of National Semiconductor Corporation.

Intel486

TM

is a trademark of Intel Corporation.

QNX

É

is a registered trademark of QNX Software Systems, Inc.

VRTX

É

is a registered trademark of Microtec Research, Inc.

VxWorks

É

is a registered trademark of Wind River Systems, Inc.

pSOS

a

TM

is a trademark of Integrated Systems Inc.

PowerPack

É

is a registered trademark of Microtek International.

C

1996 National Semiconductor Corporation RRD-B30M27/Printed in U. S. A.

http://www.national.com

Table of Contents

1.0 SYSTEM OVERVIEW

1.1 NS486SXF System Overview

1.2 32-bit Processor Core

1.3 System Service Elements

1.3.1 DRAM Controller

1.3.2 DMA Controller

1.3.3 Programmable Interval Timer

1.3.4 WATCHDOG Timer

1.3.5 Interrupt Controller

1.3.6 Real Time Clock/Calendar

1.3.7 Power Management Features

1.4 NS486SXF System Bus

1.5 Other On-board Peripherals

1.5.1 Reconfigurable I/O Lines

1.5.2 IEEE 1284 Bidirectional Port

1.5.3 PCMCIA Interface

1.5.4 MICROWIRE/Access.bus Interface

1.5.5 UART Serial Port

1.5.6 LCD Controller

1.6 ICE Support

1.7 Other Issues

2.0 PIN DESCRIPTION TABLES

3.0 DEVICE SPECIFICATIONS

3.1 DC Electrical Specifications 5V

g

5%

3.1.1 Recommended Operating Conditions

3.1.2 Absolute Maximum Ratings (Notes 2 and 3)

3.1.3 Capacitance: T

A

e

25§C, fe1 MHz

3.1.4 DC Characteristics

3.2 General AC Specifications

3.2.1 Power Ramp Times

3.2.2 PWRGOOD and Power Rampdown Timing

3.3 AC Switching Specifications

3.3.1 DRAM Interface Timing Specification

3.3.2 ISA-like Bus Cycles Timing Specification

3.3.3 Ready Feedback Timing Specifications

3.3.4 OSCX1 AC Specification

3.3.5 Peripheral Timing Specifications

3.4 Physical Description

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List of Figures

FIGURE 1-1. NS486SXF Internal Resource to Pins Map

FIGURE 1-2. NS486SXF Internal Busses

FIGURE 2-1. NS486SXF Package Pinout Diagram

FIGURE 3-1. Switching Characteristic Measurement Waveforms

FIGURE 3-2. More Switching Specifications

FIGURE 3-3. Power Supply Rise and Fall

FIGURE 3-4. PWGOOD in relation to V

DD

FIGURE 3-5. DRAM Timing Diagram

FIGURE 3-6. ISA-like Bus Timing Diagram

FIGURE 3-7. Ready Feedback Timing Diagram

FIGURE 3-8. TTL Clock Input Timing Diagram

FIGURE 3-9. DMA Controller Read Timing Diagram

FIGURE 3-10. DMA Controller Write Timing Diagram

FIGURE 3-11. PIC Timing Diagram

FIGURE 3-12. Memory Read Timing

FIGURE 3-13. Memory Write Timing Diagram

FIGURE 3-14. I/O Read Timing

FIGURE 3-15. I/O Write Timing Diagram

FIGURE 3-16. Access.bus Timing Diagram

FIGURE 3-17. UART Baud Rate and Infrared Clocks

FIGURE 3-18. UART IRQ Timing

FIGURE 3-19. UART Modem Control Timing

FIGURE 3-20. LCD Controller Timing Diagram

FIGURE 3-21. Testmode Timing Diagram

FIGURE 3-22. Plastic Package Specifications

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List of Tables

TABLE 2-1. Bus Interface Unit Pins

TABLE 2-2. DMA Control Pins

TABLE 2-3. DRAM Control Pins

TABLE 2-4. Power Pins

TABLE 2-5. Reset Logic Pins

TABLE 2-6. Auxiliary Processor Interface Pins

TABLE 2-7. Test Pins

TABLE 2-8. Interrupt Control Pins

TABLE 2-9. Real Time Clock Pins

TABLE 2-10. LCD Interface Pins

TABLE 2-11. Oscillator Pins

TABLE 2-12. HP-SIR/UART Pins

TABLE 2-13. PCMCIA pins

TABLE 2-14. IEEE-1284 Port (ECP Mode)

TABLE 2-15. Timer Pins

TABLE 2-16. 3-Wire Serial I/O Pins

TABLE 2-17. General Purpose Chip Select Pins

TABLE 2-18. Summary of Reconfigurable I/O Pins

TABLE 3-1. V

DD

Rise and Fall Times

TABLE 3-2. VDDRampdown vs PWRGOOD

TABLE 3-3. 4 Cycle Page Miss Preliminary Specifications

TABLE 3-4. 3 Cycle Miss Preliminary Specifications

TABLE 3-5. No Command Delay ISA-like Bus Specifications

TABLE 3-6. One Programmed Command Delay ISA-like Bus Specifications

TABLE 3-7. Ready Signal Timing Specifications

TABLE 3-8. TTL Clock Input Specification

TABLE 3-9. DMA Controller Specifications

TABLE 3-10. PIC Timing Specifications

TABLE 3-11. Parallel Port Compatibility Mode Handshake Timing Values

TABLE 3-12. Parallel Port IEEE 1284 Mode Handshake Timing Values

TABLE 3-13. PCMCIA Memory Read Timing Specifications

TABLE 3-14. Memory Write Timing

TABLE 3-15. PCMCIA I/O Read Specifications

TABLE 3-16. PCMCIA I/O Write Specifications

TABLE 3-17. Access.Bus Timing Specifications

TABLE 3-18. LCD Controller Timing Specifications

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1.0 System Overview

1.1 NS486SXF SYSTEM OVERVIEW

The NS486SXF is a highly integrated embedded system
controller. It includes an Intel486-class 32-bit processor, all
resources required for the System Service Elements of a
Real-Time Executive, and a generous set of peripherals.
This ‘‘system-on-a-chip’’ is ideal for implementing a wide
variety of embedded applications. These include (but are
not limited to) fax machines, multifunction peripherals (fax,
scanners, printers) mobile companions (both organizer and
communicator), television set-top boxes, and telephones
(mobile and desktop).

The 32-bit processor core executes all of the Intel486 in­structions with a similar number of clocks per instruction. An
on-board 1 kbyte instruction cache provides for efficient ex­ecution from ROM. Intel486 debug features are supported.
The processor has been optimized for operating system
kernels such as VRTX, VxWorks, pSOS

a

and QNX. These
environments only need the ‘486 protected mode operation
(no real mode or virtual 8086 support), flat or linear memory
addressing (no virtual memory paging), and floating point
execution in software only (no co-processor interface).

In fact, the NS486SXF includes all of the System Service
Elements required by a typical kernel, including an efficient
DRAM controller that supports page-mode DRAMs for data

cache-like performance; a six-channel DMA controller with
two channels supporting data transfers from on-chip periph­erals (the IEEE 1284 ECP or Extended Capabilities Port,
and the LCD controller), and four channels supporting exter­nal devices such as scanners, and print engines; three timer
channels (including one configured as a protected WATCH­DOG Timer); two programmable 8259 interrupt controllers
provide 15 on-chip interrupt sources; an industry standard
real time clock and calendar (RTC) with battery backup; and
support for comprehensive power management schemes.

In addition, the NS486SXF also incorporates the key I/O
peripherals required for implementing a wide variety of em­bedded applications: an IEEE 1284 Bidirectional Parallel
Port that includes both Host and Slave modes, an Intel
82365-compatible PCMCIA controller for one card slot, an
industry standard high-performance NS16550-compatible
UART with HP-SIR and IrDA v1.0 infrared option, an LCD
panel interface with DMA supported refresh for many of the
standard resolutions, an 8254 timer, and a general purpose
2- or 3-wire synchronous serial interface for easy interface
to low-cost EEPROMs and other serial peripherals. System
expansion is supported with nine programmable Chip Select
(CS) signals and a generic ISA-type bus interface for exter­nal devices and memory.

TL/EE/12514– 2

FIGURE 1-1. NS486SXF Internal Resource to Pins Map

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1.0 System Overview (Continued)

Certain I/O lines not being used by disabled peripherals can
be reconfigured for use as general purpose bidirectional I/O
lines (up to 29 pins). This gives the designer maximum flexi­bility in designing various systems using the NS486SXF de­vice. It is expected that an NS486SXF system will minimally
include the NS486SXF system controller with on-board
processor and I/O devices, boot ROM, and working RAM
memory. Many applications will not require any additional
I/O support.

Finally, the NS486SXF implements a very flexible power
management scheme that permits selective control of indi­vidual I/O subsystems, with varying levels of power con­sumption.

NS486SXF provides a cost-effective hardware platform for
the design and implementation of a wide range of office
automation and communication systems. With its powerful
embedded ‘486-class processor, comprehensive set of on­chip peripheral controllers, flexible power management
structure and reconfigurable I/O lines, NS486SXF makes
possible a variety of end-user systems based on the same
hardware. Because of its optimized design and on-board
resources, a very cost effective system can be achieved.

1.2 32-BIT PROCESSOR CORE

The NS486SXF processor core is an implementation of the
protected mode ‘486 instruction set architecture, optimized
using a RISC-like design philosophy for embedded applica­tions. Using this approach, the most frequently used instruc­tions are optimized, and on an average execute in a lower
number of clock cycles than a ‘486.

The NS486SXF features a three stage pipeline, efficient in­struction prefetching mechanism, and single cycle instruc­tion decoding for most instructions. Additionally, a 1 kbyte
instruction cache and single cycle DRAM access provide
higher memory performance than a larger unified cache im­plementation.

The NS486SXF processor provides the same programming
model and register set as the standard ‘486 except that real
mode, virtual memory, and floating point support have been
eliminated. These features have little or no impact in em­bedded applications and save significant silicon real estate.
At reset, unlike the standard ‘486, the NS486SXF starts up
in protected mode instead of real mode. All ‘486 instructions
appropriate to protected mode and our hardware configura­tion are supported, including debug instructions.

The NS486SXF is initially available to run 25 MHz at 5V.
The processor clock is obtained by dividing the crystal fre­quency by two. For example, a 25 MHz NS486SXF runs with
a 50 MHz crystal oscillator as the master clock.

As a result of our innovative design, the NS486SXF
achieves performance equivalent to a standard ‘486 with
less circuitry. This translates into reduced power consump­tion and a lower overall system cost. It also makes the
NS486SXF ideal for ‘‘green’’ systems and battery operated
systems.

1.3 SYSTEM SERVICE ELEMENTS

The NS486SXF controller provides the basic hardware re­sources required for the O/S-defined System Service Ele­ments. These include a DRAM controller, a DMA controller,
programmable interval timer, a protected WATCHDOG tim­er, a programmable interrupt controller, a real-time clock
and calendar, and comprehensive power management fea­tures.

1.3.1 DRAM Controller

The NS486SXF DRAM controller supports one or two ad­justable-sized banks of dynamic RAM using a 16-bit data
path. Support is provided for byte parity (if desired), requir­ing the DRAM banks to be 18 bits wide when parity is en­abled. Banks can be up to 8 Mbytes in size. The DRAM
controller supports page mode read and write operations
and can also support both byte and word accesses. All ac­cess control signals for read, write and parity checking are
generated as well as an automatic and programmable CAS­before-RAS refresh. If self-refresh DRAMs are used, refresh
can be disabled, saving power.

NS486SXF provides flexible support for use of a number of
different DRAM configurations, using popular DRAM devic­es. Access is optimized for fast page mode DRAMs, and
they will provide the highest performance with contiguous
data. When accessing data bytes or words in the same
DRAM page, the data access is in one cycle. This perform­ance provides fast data access times without the overhead
of a separate data cache. Page sizes can be 512, 1024,
2048 or 4096 bytes. Flexibility for DRAM timing is provided
through programming of the DRAM controller registers: 3 or
4 cycle page miss accesses and extended CAS cycles can
be selected.

Memory bank 0 starts at address 0h; memory bank 1 can
start at any address in the 128 Mbyte address map that is a
multiple of its size.

1.3.2 DMA Controller

The NS486SXF Direct Memory Access (DMA) controller is a
high speed 16-bit controller that improves system perform­ance by off-loading from the processor the task of manag­ing data transfers to and from memory and external devices.
Data transfers are done independently from the processor
at a maximum data rate of 2 bytes per 2 clock cycles. (A 25
MHz clock yields a 25 megabyte per second transfer rate.)

There are six independent DMA channels. Requestor and
target addresses have a maximum addressable memory
range of 64 Mbytes. Three standard transfer modes, single,
block and demand, are provided giving the designer a wide
range of DMA options. A special transfer type, cascade­master, allows an external master to access the NS486SXF
ISA-like bus. Normal transfers can be from memory to mem­ory, memory to I/O and I/O to memory. DMA transfers are
controlled by DMA control registers in the NS486SXF con­trol register I/O map.

1.3.3 Programmable Interval Timer

The NS486SXF programmable interval timer is compatible
with the Intel 8254 programmable interval timer and con­tains three identical timers (CH0 –CH2). CH0 and CH1 can
be used to generate accurate timing delays under software
control. CH2 may be configured to provide a WATCHDOG
timer function.

1.3.4 WATCHDOG Timer

The NS486SXF WATCHDOG timer, CH2, is a protected
16-bit timer that can be used to prevent system ‘‘lockups or
hangups.’’ It uses a 1 kHz clock generated by the on-chip
real-time clock circuit. If the WATCHDOG timer is enabled
and times out, a reset or interrupt will be generated allowing
graceful recovery from an unexpected system lockup.

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1.0 System Overview (Continued)

1.3.5 Interrupt Controller

The NS486SXF interrupt controller consists of two cascad­ed programmable interrupt controllers that are compatible
with the Intel 8259A Programmable Interrupt Controller.
They provide a total of 15 (out of 16) programmable inter­rupts. Three interrupts are reserved for a real time clock-tick
interrupt, a real time clock interrupt request, and a cascade
interrupt channel. The remaining 13 interrupts can be used
by internal or external sources. Additional external interrupt
controllers can be cascaded as well.

1.3.6 Real Time Clock/Calendar

The NS486SXF Real Time Clock/Calendar is a low power
clock that provides a time-of-day clock and 100-year calen­dar with alarm features and battery operation. Time is kept
in BCD or binary format. It includes 50 bytes of general pur­pose CMOS RAM and 3 maskable interrupt sources. It is
compatible with the DS1287 and MC146818 RTC/Calendar
devices, except for the general purpose memory size.

1.3.7 Power Management Features

The NS486SXF power management structure includes a
number of power saving mechanisms that can be combined
to achieve comprehensive power savings under a variety of
system conditions. First of all, the core processor power
consumption can be controlled by varying the processor/
system clock frequency. The internal CPU clock can be di­vided by 4, 8, 16, 32 or 64. In addition, in idle mode, the
internal processor clock will be disabled. Finally, if an exter­nal crystal oscillator circuit is being used, it can be disabled.
For maximum power savings, all internal clocks can be dis­abled (except for the real-time clock oscillator).

The clocks of the on-board peripherals can be individually
or globally controlled. By setting bits in the power manage­ment control registers, the internal clocks to the DMA con-

troller, the ECP port, the three-wire interface, the timer, the
LCD controller, the DRAM controller, the PCMCIA controller
and the UART can be disabled.

In addition to these internal clocks, the external SYSCLK
can be disabled via a bit in the power management control
registers.

Using various combinations of these power saving controls
with the NS486SXF controller will result in excellent pro­grammable power management for any application.

1.4 NS486SXF SYSTEM BUS

The NS486SXF system bus provides the interface to off­chip peripherals and memory. It offers an ISA-compatible
interface and is therefore capable of directly interfacing to
many ISA peripheral control devices. The interface is ac­complished through the Bus Interface Unit (BIU). The BIU
generates all of the access signals for both internal and
external peripherals and memory. Depending upon whether
the access is to internal peripherals, external peripherals or
external memory, the BIU generates the timing and control
signals to access those resources. The BIU is designed to
support a glueless interface to many ISA-type peripherals.

For debug purposes, the NS486SXF can be set to generate
external bus cycles at the same time as an internal peripher­al access takes place. This gives logic analyzers or other
debug tools the ability to track and capture internal peripher­al accesses.

Access to internal peripherals is accomplished in three CPU
T-states (clock cycles). The fastest access to off-chip I/O is
also three T-states. When accessing off-chip memory and
I/O, wait state generation is accomplished through a combi­nation of NS486SXF chip select logic and off-chip peripher­al feedback signals.

TL/EE/12514– 3

FIGURE 1-2. NS486SXF Internal Busses

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1.0 System Overview (Continued)

When the CPU is in idle mode, the BIU is designed to mimic
the CPU during DMA interchanges between memory and
peripherals. By responding to DRQs and generating DACK,
and HOLDA signals as required, the BIU eliminates the
need to reactivate the CPU during such transfers as screen
updates from memory to the LCD controller. This gives the
designer added flexibility in conserving power while main­taining basic system functions.

1.5 OTHER ON-BOARD PERIPHERALS

In addition to those peripherals and system control ele­ments needed for System Service Elements, the NS486SXF
also includes a number of I/O controllers and resources
that make implementing a complete embedded system pos­sible with just a single-chip NS486SXF controller. These in­clude an IEEE 1284 Extended Capabilities Port, a serial
UART port, a LCD controller, a PCMCIA interface and a
MICROWIRE or Access.bus synchronous serial bus inter­face. In addition, unused I/O controllers free up their I/O
pins for general purpose use.

1.5.1 Reconfigurable I/O Lines

The NS486SXF supports reconfigurable I/O. For example, if
the UART, ECP Parallel Port, LCD or PCMCIA functions are
not being used, the I/O pins associated with them can be
reconfigured as general purpose bidirectional I/O pins. Up
to 29 pins can be reconfigured for this purpose. This capa­bility makes the NS486SXF extremely versatile and ideal for
supporting different end product configurations with a single

NS486SXF device.

1.5.2 IEEE 1284 Bidirectional Port

The NS486SXF parallel port is a multifunction 8-bit parallel
port that is compatible with the IEEE 1284 bidirectional par­allel port standard. The operation of the parallel port is set
by the content of the NS486SXF parallel port I/O control
registers. The port can operate in one of two modes: a stan­dard parallel port mode (PC compatible), or a full Extended
Capabilities Port (ECP) mode. The NS486SXF ECP port can
support both Host and Slave ECP mode. In slave mode, the
NS486SXF becomes a versatile microprocessor for parallel
I/O peripheral devices.

1.5.3 PCMCIA Interface

The NS486SXF PCMCIA interface supports the direct con­nection of a single PCMCIA 2.0 IC card. Exchange Card
Architecture (ExCA release 1.50) compatibility and eXecute
In Place (XIP) capability is also provided.

Accessing the PCMCIA interface switches the external bus
automatically into the PCMCIA mode and permits Memory
Window Mapping and Address Offset to be handled inside
the NS486SXF device. Power management and ‘‘hot’’ card
insertion/removal options can be implemented using exter­nal buffering, if required.

1.5.4 MICROWIRE/Access.bus Interface

The NS486SXF MICROWIRE/Access.bus interface pro­vides for full support of either the three-wire MICROWIRE or
the two-wire Access.bus serial interfaces. MICROWIRE has
an alternate clock phasing option that supports the SPI bus
protocol as well. These industry standard interfaces permit
easy interfacing to a wide range of low-cost specialty mem­ories and I/O devices. These include EEPROMs, SRAMs,
timers, clock chips, A/D converters, D/A converters, and
peripheral device drivers.

1.5.5 UART Serial Port

The NS486SXF UART provides complete NS16550 (PC
standard) serial communications port compatibility including
the performance enhancing 16-byte deep FIFO. It performs
serial-to-parallel conversion from external devices to the

NS486SXF and parallel-to-serial conversion from the
NS486SXF to external peripherals. Full modem control can

be supported.

A serial IrDA v1.0 and HP-SIR (infrared) mode is also sup­ported, making possible low-cost wireless communications
between an NS486SXF-based system and other wireless
infrared systems.

1.5.6 LCD Controller

The NS486SXF LCD controller is capable of controlling a
variety of monochrome supertwist LCD configurations in­cluding 320x240, 320x200 and 480x320 black and white or
grayscale graphics LCD modules equipped with self-con­tained screen drivers. It uses a video frame buffer in system
DRAM with either a 1- or 2-bit per pixel grayscale. A 60 Hz
to 90 Hz frame refresh rate is supported. Special controls
permit the fine tuning of display characteristics to precisely
optimize visual display quality.

1.6 ICE SUPPORT

National Semiconductor has worked closely with Microtek
International to provide hardware in-circuit emulator support
for the NS486SXF. The Microtek product (PowerPack

É

EA­NS486) uses a special bondout version of the NS486SXF to
deliver a full-featured hardware emulator that is capable of
tracing on chip activity, including peripheral interrupt and
I/O activity. The emulator runs at full speed, and supports
overlay memory and multiple triggers.

1.7 OTHER ISSUES

NS486SXF provides a comprehensive set of on-board pe-

ripherals. Also, it is designed to easily interface to external
peripherals. In addition to this ISA-like bus which supports
ISA-compatible peripherals, the NS486SXF provides an in­terface to an external master with a shared memory space.
The external master or auxiliary processor interface allows
low cost interfacing to shared external memory belonging to
other external masters (including another NS486SXF con­troller).

To program the resources of the NS486SXF, a set of inter­nal control registers exists. These registers provide precise
control over all internal resources and the setup of external
NS486SXF control signals. It is the designer’s responsibility
to ensure the proper initialization of the registers in this I/O
map.

In addition, the NS486SXF core processor itself requires
several descriptor tables and initialization parameters that
must be set by user-written start-up software.

The NS486SXF is designed from the ground up for optimum
price/performance in embedded systems. This makes the
NS486SXF the logical choice as the base hardware plat­form for executing an embedded operating system kernel
such as those available from Microtec International, Wind
River, ISI, QNX, and many others. Any Operating System or
Real-Time Executive that will operate in a segmented or flat
memory model protect mode environment is a suitable com­plement to the NS486SXF.

Also, there are many third party tool sets that will allow an
executable application to be built to run directly on the tar­get hardware without an O/S environment.

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2.0 Pin Description Tables

TL/EE/12514– 4

FIGURE 2-1. NS486SXF Package Pinout Diagram

The NS486SXF single chip controller is provided in a com­pact 160-pin, industry standard JEDEC PQFP package. The
following tables detail the Symbol, Type, and Description of
each pin. The tables divide the pins into functional groups
as follows: Bus Interface Unit Pins, DMA Control Pins,
DRAM Control Pins, Power Pins, Reset Logic Pins, Auxiliary
Processor Interface Pins, Test Pins, Interrupt Control Pins,
Real Time Clock Pins, LCD Interface Pins, Oscillator Pins,
UART/IrDA Pins, PCMCIA Pins, IEEE-1284 Port (ECP

Mode) Pins, Timer Pins, 3-Wire Serial I/O Pins, General Pur­pose Chip Select Pins, and Reconfigurable I/O Pins. Twen­ty-nine I/O pins are multipurpose. In their standard modes,
they perform specific I/O controller functions. When those
particular I/O functions are not required in the system, how­ever, those pins can be reprogrammed to become general
purpose, bidirectional I/O lines.

Note: In the above figure and in the following tables, all active low signals

are shown with an overbar.

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2.0 Pin Description Tables (Continued)

TABLE 2-1. Bus Interface Unit Pins

Symbol Pins Type Function

SA[25:0]130, 132, O System Address bus. These output-only signals carry the latched address for the current access.

DRAM accesses multiplex the row and column addresses for the DRAMs on the SA[12:1]pins.

133, 134,

During Interrupt Acknowledge cycles, the internal master interrupt controller’s cascade line

135, 136,

signals, CAS[2:0], are driven onto SA[25:23], respectively. SA[0]is sampled at the end of reset to

137, 138,

determine if the part will run normally or enter ICE TRI-STATE mode.

139, 140,
141, 142,
143, 145,
146, 148,
149, 150,
151, 152,
153, 155,
156, 158,
159, 160

SD[15:0]2, 3, 5, 6, I/O System Data bus: This bi-directional data bus provides the data path for all memory and I/O

accesses. During transfers with 8-bit devices, the upper data byte is not used (SD[15:8]).

8, 9, 10,

11, 13,
15, 16,
18, 19,

20, 21, 22

SBHE 129 O Byte High Enable. This active-low signal indicates that the high byte (odd address byte) is being

transferred. External 16-bit devices should use this signal to help them determine that a data byte
is to be transferred on the upper byte of the System Data bus (SD[15:8]). 8-bit devices should
ignore this signal. SBHE

is sampled at the end of power good reset to determine if the boot ROM

is 8- or 16-bit wide.

IOR 124 O IO Read command. This active-low signal instructs an I/O device to place data onto the system

data bus.

IOW 125 O IO Write command. This active-low signal indicates to an I/O device that a write operation is in

process on the system bus.

MEMR 126 O MEMory Read command. This active-low signal instructs a memory mapped device to place data

onto the system data bus.

MEMW 127 O MEMory Write command. This active-low signal indicates to a memory mapped device that a write

operation is in process on the system bus.

CS16 122 I/O Chip Select 16-bit. This active-low feedback signal indicates that the device being accessed is a

16-bit device. This signal should be driven by external devices with an open collector driver. If a
chip select is programmed to force 16-bit accesses, this signal will be asserted (low) during the
access.

RDY 123 I ReaDY. An external device may drive this signal inactive low to insert wait states and extend the

external bus cycle. This signal should be driven with an open collector or be TRI-STATE driven.

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2.0 Pin Description Tables (Continued)

TABLE 2-2. DMA Control Pins

Symbol Pins Type Function

DRQ[4], DRQ[3], 34, 32, I DMA ReQuest. A DRQn signal requests the internal DMA Controller to transfer data

between the Requesting Device and memory.

DRQ[2], DRQ[0]36, 38

DACK[4], 35, 33, O DMA ACKnowledge: When the CPU has relinquished control of the bus to a requesting DMA

channel, the appropriate active-low DACK

n signal acknowledges the winning DRQn.

DACK[3

]

, 37, 39

DACK[2

]

,

DACK[0

]

TC/EOP 40 I/O Terminal Count/End Of Process: This signal may operate either as a terminal count output

or an active-low End of Process input. As TC, an active-high pulse occurs on this signal when
the terminal count for any DMA channel has been reached. As EOP

, an external device may

terminate the DMA transfer by driving this signal active-low.

TABLE 2-3. DRAM Control Pins

Symbol Pins Type Function

RAS

[

1:0]30, 31 O Row Address Strobe. On the falling edge of these active-low signals, Bank 1 and Bank 0

respectively, should latch in the row address off of SA[12:1]. If only one bank of DRAMs are
supported, RAS0

will support that bank and RAS1 will be unused.

CASH

[

1:0]25, 26 O Column Address Strobe (High Byte). These active-low signals indicate when the column access is

being made to the high byte of DRAM Bank 1 and DRAM Bank 0 respectively. If only one bank of
DRAMs are supported, CASH0

will support the high byte of that bank and CASH1 will be unused.

CASL

[

1:0]28, 29 O Column Address Strobe (Low Byte). These active-low signals indicate when the column access is

being made to the low byte of DRAM Bank 1 and DRAM Bank 0, respectively. If only one bank of
DRAMs are supported, CASL0

will support the low byte of that bank and CASL1 will be unused.

WE 23 O Write Enable. Active low signal for writing the data into the DRAM bank.

DPH, DPL 1, 12 I/O DRAM Data Parity. DRAM data parity may be enabled or disabled; if disabled these two pins will be

unused. Otherwise, for DRAM writes the NS486SXF’s DRAM Controller will generate odd parity and
drive the odd parity onto these two pins. For DRAM reads the NS486SXF’s DRAM Controller will
read the values driven on these two pins and check it for odd parity in association with the
appropriate data byte.

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2.0 Pin Description Tables (Continued)

TABLE 2-4. Power Pins

Symbol Pins Type Function

V

DD

7, 17, 27, I

a

5V power to core and I/O.

47, 63,

87, 101,

131, 147,

157

V

SS

4, 14, 24, I Ground to core and I/O.

44, 61,
84, 98,

128, 144,

154

TABLE 2-5. Reset Logic Pins

Symbol Pins Type Function

RESET 119 O RESET system output driver: This active high signal resets or initializes system peripheral logic during

power up or during a low line voltage outage.

RESET 120 O Inverse of RESET for peripherals requiring active low reset.

PWGOOD 60 I PoWer GOOD. This active-high (Schmitt Trigger) input will cause a hardware reset to the NS486SXF

whenever this input goes low. This pin will typically be driven by the power supply and PWGOOD will
remain low until the power supply determines that stable and valid voltage levels have been achieved.

TABLE 2-6. Auxiliary Processor Interface Pins

Symbol Pins Type Function

EREQ/CS6/RTS 102 O This pin has three programmable options controlled by the Modem Signal Control Register

(refer to the UART section):

1. External bus REQuest (active-low) to an auxiliary processor.

2. Chip Select 6 (active-low) pin.

3. Request To Send. When low, this signal informs the MODEM or data set that the UART is
ready to exchange data. The RTS output signal can be set to an active low by programming
bit 2 (RTS) of the MODEM Control Register. A Master Reset operation sets this signal to its
inactive (high) state. Loop mode operation holds this signal in its inactive state.

EACK/CS7/DSR 103 I/O This pin has three possible programmable options controlled by the Modem Signal Control

Register (refer to the UART section):

I1.External bus ACKnowledge (active-low) from an auxiliary processor.

O2.Chip Select 7 (active-low) pin.

I3.Data Set Ready. When low, it indicates that the MODEM or data set is ready to link with the

UART. The DSR

signal is a MODEM status input whose condition can be tested by the CPU
reading bit 5 (DSR) of the MODEM Status Register. Bit 5 is the complement of the DSR
signal. Bit 1 (DDSR) of the MODEM Status Register indicates whether the DSR input has
changed state since the previous reading of the MODEM Status Register.

Note: Whenever the DSR bit of the MODEM Status Register changes state, an interrupt is generated if the MODEM

Status Interrupt is enabled.

DRV/CS8/DTR 104 O This pin has three possible programmable options controlled by the Modem Signal Control

Register (refer to the UART section):

1. DSP shared memory DRiVe control signal.

2. Chip Select 8 (active-low) pin.

3. Data Terminal Ready. When low, this signal informs the MODEM or data set that the UART
is ready to establish a communications link. The DTR

output signal can be set to an active
low by programming bit 0 (DTR) of the MODEM Control Register to a high level. A Master
Reset operation sets this signal to its inactive (high) state. Loop mode operation holds this
signal in its inactive state.

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2.0 Pin Description Tables (Continued)

TABLE 2-7. Test Pins

Symbol Pins Type Function

TEST 66 I/O Reserved for testing and development system support.

TABLE 2-8. Interrupt Control Pins

Symbol Pins Type Function

NMI 105 I Non-Maskable Interrupt. This active-high signal will generate a non-maskable interrupt to the CPU

when it is active high. Normally this signal is used to indicate a serious system error.

INTA 106 O INTerrupt Acknowledge. During each interrupt acknowledge cycle this signal will strobe low; it

should be used by external cascaded interrupt controllers.

IRQ[5:0]107, 108, I Interrupt ReQuests. These inputs are either rising edge or low-level sensitive interrupt requests,

depending on the configuration of the internal interrupt controllers. These interrupt requests may

109, 110,

also be programmed to support externally cascaded interrupt controller(s). The IRQ pins are also

111, 112

used to select a particular test in test mode. If the PCMCIA controller is enabled, IRQ[5]becomes
the IREQ

signal.

TABLE 2-9. Real Time Clock Pins

Symbol Pins Type Function

RTCX1 62 I Real Time Clock crystal oscillator input: 32 kHz crystal.

RTCX2 64 O Real Time Clock crystal oscillator output: 32 kHz crystal.

V

bat

65 I Externalabattery input for real time clock.

TABLE 2-10. LCD Interface Pins

Symbol Pins Type Function

LCD[3:0]51, 52, O Data Output Word to LCD,1eWhite, 0eBlue/black.

53, 54

CL2 50 O Word CLock to LCD.

CL1 49 O Row CLock to LCD.

CLF 48 O Frame CLock to LCD.

TABLE 2-11. Oscillator Pins

Symbol Pins Type Function

SYSCLK 121 O SYStem CLocK. This clock output pin will either be driven with a signal half the frequency of the OSCX1

input clock frequency or the CPU’s clock frequency, which is determined in the Power Management
Control Register 1. The source selection for this signal is determined by bit 1 of the Power Management
Control Register 3.

OSCX1 45 I OSCillator Crystal 1 input. This pin should either be driven by a TTL oscillator or be connected to an

external crystal circuit. This signal is the fundamental clock source for all clocked elements in the
NS486SXF, except the Real-Time Clock, which has its own crystal pins.

OSCX2 46 O OSCillator Crystal 2 output. This is the output side of the NS486SXF on-chip circuitry provided to

support an external crystal circuit. If a TTL oscillator drives OSCX1, this pin should be a no connect.

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2.0 Pin Description Tables (Continued)

TABLE 2-12. HP-SIR/UART Pins

Symbol Pins Type Function

Tx 57 O UART Transmit data. In HP-SIR mode this pin is the UART output encoded for the serial infrared link.

Otherwise it is the transmit output of the 16550 UART.

Rx 58 I UART Receive data. In HP-SIR mode this pin is routed through the serial infrared decoder. Otherwise, it

is the receive input to the 16550.

UCLK 59 O Uart CLocK. Output of programmable rate UART/MODEM clock. Typically used for the Infrared

Modulator.

TABLE 2-13. PCMCIA Pins

Symbol Pins Type Function

CDÐRST 68 O CarDReSeT. This active high signal resets the PCMCIA card during a soft-reset.

IOIS16/WP 67 I IO port IS 16 bits/Write Protect: When a PCMCIA card is configured as an IO card, this signal

is asserted to indicate the currently addressed IO port is 16 bits wide. When a PCMCIA card is
configured as a memory card, an active high signal indicates the card is currently write
protected.

BVD2/SPKR 74 I Battery Voltage Detect bit 2/ SPeaKeR output. When a PCMCIA card is configured as a

memory card, this input along with BVD[1]will provide status information about the card’s on­board battery condition. When a PCMCIA card is configured as an IO card, this pin will act as
the audio output of the card to the system.

BVD1/STSCNG 73 I Battery Voltage Detect bit 1/ STatuSChaNGe output. When a PCMCIA card is configured as a

memory card, this input along with BVD[2]will provide status information about the card’s on­board battery state. When a PCMCIA card is configured as an I/O card, the status change
signal indicates one or more of the memory status signals (BVD[2:1], WP, RDY or BSY

) has

changed states.

VCCÐSEL 69 O PCMCIA VCCSELect. When this signal is low, the VCCpower to the PCMCIA card should be

enabled.

VPPÐSEL1, 70, 71 O PCMCIA VPPSELect 1 and 2. These signals indicate the voltage with which the VPPpower to

the PCMCIA card should be driven.

V

PP

ÐSEL2

GPI 72 I General Purpose Input. This signal is a general purpose input signal used with a PCMCIA card

to indicate a valid V

PP

state, a pending card eject/insertion, or as an interrupt source.

CD2, CD1 76, 75 I Card Detect. Both signals are low when the PCMCIA card is correctly inserted.

DIR 77 O DIRection. Used to control the direction of the data line buffers to the PCMCIA interface.

ENABLE 78 O ENABLE PCMCIA. Enables the buffer drivers to the PCMCIA interface. Low true signal.

REG 79 O REG. PCMCIA card support.

Note: If PCMCIA is enabled, Chip Selects 1 and 2 become Card Enable 1 and 2. See Table 2-17, ‘‘General Purpose Chip Select Pins’’. Also, IRQ[5]becomes the
PCMCIA IREQ

signal.

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