The LPC662 CMOS Dual operational amplifier is ideal for
operation from a single supply. It features a wide range of
operating voltage from +5V to +15V, rail-to-rail output swing
in addition to an input common-mode range that includes
ground. Performance limitations that have plagued CMOS
amplifiers in the past are not a problem with this design.
Input V
(into 100 kΩ and5kΩ) are all equal to or better than widely
accepted bipolar equivalents, while the power supply
requirement is typically less than 0.5 mW.
This chip is built with National’s advanced Double-Poly
Silicon-Gate CMOS process.
See the LPC660 datasheet for a Quad CMOS operational
amplifier and LPC661 for a single CMOS operational
amplifier with these same features.
, drift, and broadband noise as well as voltage gain
OS
Applications
n High-impedance buffer
n Precision current-to-voltage converter
n Long-term integrator
n High-impedance preamplifier
n Active filter
n Sample-and-Hold circuit
n Peak detector
Features
n Rail-to-rail output swing
n Micropower operation (
n Specified for 100 kΩ and5kΩloads
n High voltage gain120 dB
n Low input offset voltage3 mV
n Low offset voltage drift1.3 µV/˚C
n Ultra low input bias current2 fA
n Input common-mode includes GND
n Operating range from +5V to +15V
n Low distortion0.01% at 1 kHz
n Slew rate0.11 V/µs
n Full military temperature range available
(C = 100 pF, R = 1.5 kΩ)1000V
Power Dissipation(Note 2)
Current at Input Pin
Current at Output Pin
±
Supply Voltage
(Note 11)
(Note 1)
±
5mA
±
18 mA
Current at Power Supply Pin35 mA
+
Voltage at Input/Output Pin(V
) + 0.3V, (V−) −0.3V
Operating Ratings (Note 3)
Temperature Range
LPC662AMJ/883−55˚C ≤ T
LPC662AM−55˚C ≤ T
LPC662AI−40˚C ≤ T
LPC662I−40˚C ≤ T
Supply Range4.75V to 15.5V
Power Dissipation(Note 9)
Thermal Resistance (θ
) (Note 10)
JA
8-Pin Ceramic DIP100˚C/W
8-Pin Molded DIP101˚C/W
8-Pin SO165˚C/W
8-Pin Side Brazed Ceramic DIP100˚C/W
≤ +125˚C
J
≤ +125˚C
J
≤ +85˚C
J
≤ +85˚C
J
DC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ= 25˚C. Boldface limits apply at the temperature extremes. V+= 5V, V
= 0V, VCM= 1.5V, VO= 2.5V and R
Input Offset Voltage1.3µV/˚C
Average Drift
Input Bias Current0.00220pA
Input Offset Current0.00120pA
Input Resistance
Common Mode0V ≤ V
Rejection RatioV
+
= 15V686861min
Positive Power Supply5V ≤ V
Rejection RatioV
O
Negative Power Supply0V ≤ V
Rejection Ratio828373min
Input Common-ModeV
+
= 5V and 15V−0.4−0.1−0.1−0.1V
Voltage RangeFor CMRR ≥ 50 dB000max
Large SignalR
= 100 kΩ (Note 5)1000400400300V/mV
L
Voltage GainSourcing250300200min
Sinking50018018090V/mV
R
=5kΩ(Note 5)1000200200100V/mV
L
Sourcing15016080min
Sinking25010010050V/mV
>
1M unless otherwise specified.
L
LPC662AMLPC662AILPC662I
Limit(Note 4)(Note 4)
(Notes 4, 8)
3.53.36.3max
10044max
10022max
>
1Tera Ω
≤ 12.0V83707063dB
CM
+
≤ 15V83707063dB
= 2.5V686861min
−
≤ −10V94848474dB
+
V
− 1.9V+− 2.3V+− 2.3V+− 2.3V
+
V
− 2.6V+− 2.5V+− 2.5min
7012070min
356040min
−
www.national.com2
DC Electrical Characteristics (Continued)
Unless otherwise specified, all limits guaranteed for TJ= 25˚C. Boldface limits apply at the temperature extremes. V+= 5V, V
= 0V, VCM= 1.5V, VO= 2.5V and R
Gain-Bandwidth Product0.35MHz
Phase Margin50Deg
Gain Margin17dB
Amp-to-Amp Isolation(Note 7)130dB
Input Referred Voltage NoiseF = 1 kHz42
Input Referred Current NoiseF = 1 kHz0.0002
Total Harmonic DistortionF = 1 kHz, AV= −10, V+= 15V0.01%
R
Note 1: Applies to both single supply and split supply operation. Continuous short circuit operation at elevated ambient temperature and/or multiple Op Amp shorts
can result in exceeding the maximum allowed junction temperature of 150˚C. Output currents in excess of
Note 2: The maximum power dissipation is a function of T
−TA)/θJA.
Note 3: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The
guaranteed specifications apply only for the test conditions listed.
Note 4: Limits are guaranteed by testing or correlation.
Note 5: V
Note 6: V
Note 7: Input referred. V
Note 8: A military RETS electrical test specification is available on request. At the time of printing, the LPC662AMJ/883 RETS specification complied fully with the
boldface limits in this column. The LPC662AMJ/883 may also be procured to a Standard Military Drawing specification.
Note 9: For operating at elevated temperatures the device must be derated based on the thermal resistance θ
Note 10: All numbers apply for packages soldered directly into a PC board.
Note 11: Do not connect output to V
+
= 15V, VCM= 7.5V and RLconnected to 7.5V. For Sourcing tests, 7.5V ≤ VO≤ 11.5V. For Sinking tests, 2.5V ≤ VO≤ 7.5V.
+
= 15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of the positive and negative slew rates.
+
= 15V and RL= 100 kΩ connected to V+/2. Each amp excited in turn with 1 kHz to produce VO=13VPP.
+
when V+is greater than 13V or reliability may be adversely affected.
>
1M unless otherwise specified.
L
= 100 kΩ,VO=8V
L
J(max)
LPC662AMLPC662AI LPC662I
Limit(Note 4)(Note 4)
(Notes 4, 8)
0.040.050.03min
PP
±
30 mA over long term may adversely affect reliability.
, θJA, and TA. The maximum allowable power dissipation of any ambient temperature is PD=(T