NSC CLC949AJQ, CLC949ACQ, CLC949PCASM Datasheet

SFDR (dBc)

SNR (dB), SFDR (dBc)

Power Dissipation vs. Conversion Rate

200

150

100

Power (mW)

0 5 10 15

Sample Rate (MSPS)

Features

■

Very low/programmable power

0.07W @ 5MSPS

0.22W @ 20MSPS

0.40W @ 30MSPS

■

Single supply operation (+5V)

■

0.5 LSB differential linearity error

■

Wide dynamic range

72dBc spurious-free dynamic range 68dB signal-to-noise ratio

■

No missing codes

Applications

■

CCD imaging

■

IR imaging

■

FLIR processing

■

Medical imaging

■

High definition video

■

Instrumentation

■

Radar processing

■

Digital communications

General Description

The Comlinear CLC949 is a 12-bit analog-to-digital converter subsystem including 12-bit quantizer, sample-and-hold amplifier, and internal reference. The CLC949 has been optimized for low power operation with high dynamic range. The CLC949 has a unique feature which allows the user to adjust internal bias levels in the converter which results in a trade-off between power dissipation and maximum conversion rate. With bias set for 220mW power dissipation the converter operates at 20MSPS. Under these conditions, dynamic performance with a 9.9MHz analog input is typically 68dB SNR and 72dBc SFDR. When bias is set for only 65mW power dissipation the converter maintains excellent performance at 5MSPS. With a 2.4MHz analog input signal the SNR is 70dB and SFDR is 78dBc. This excellent dynamic performance in the frequency domain without high power requirements make the part a strong performer for communications and radar applications. The low input noise of the CLC949, its 0.5LSB differential linearity error specification, fast settling, and low power dissipation also lead to excellent performance in imaging systems. All parts are thoroughly tested to insure that guaranteed specifications are met.

The CLC949 incorporates an input sample-and-hold amplifier followed by a quantizer which uses a pipelined architecture to minimize comparator count and the associated power dissipation penalty. An on-board voltage reference is provided. Analog input signals, conversion clock, and a single supply are all that are required for CLC949 operation.

The CLC949 exhibits very stable performance over the commercial and industrial temperature ranges. Most parameters shift very little as the ambient temperature changes from -40°C to 85°C. An exception to this rule is the dynamic performance of the converter. As the temperature is increased, the distortion increases, especially at higher input frequencies. This can be seen in the plot on page 3. For input frequencies below 7MHz, there is relatively little variation in distortion as the temperature is changed, but at higher input frequencies, it is apparent that the performance degrades as the temperature is increased.

Note that the reason for this degradation is the reduced ability of the CLC949 to handle high slew rates at high temperatures. In applications such as CCD imaging systems, where the slew rate at the A/D sampling instant is very low, this degradation will not be nearly so pronounced.

For applications requiring high temperature operation and very low distortion with high frequency input signals, use of an external sample-and-hold amplifier may enhance performance by reducing the slew rates that the CLC949 sees during its sampling period (just after the falling edge of CLK).

The CLC949 is fabricated in a 0.9µm CMOS technology. The CLC949ACQ is specified over the commercial temperature range of 0°C to +70°C and the CLC949AJQ is specified over the indus- trial range of -40°C to +85°C. Both are packaged in a 44-pin Plastic Leaded Chip Carrier (PLCC)

Comlinear CLC949 Very Low-Power, 12-Bit, 20MSPS Monolithic A/D Convertter

August 1996

Comlinear CLC949

Very Low-Power, 12-Bit, 20MSPS Monolithic Converter

Printed in the U.S.A.

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PARAMETERS CONDITIONS TYP

MIN/MAX RATINGS

UNITS SYMBOL

Case Temperature +25˚C 0 to 70˚C -40 to 85˚C

DYNAMIC CHARACTERISTICS

overvoltage recovery V

= 1.5FS 15 25 25 25 ns OR effective aperture delay 3.0 6.2 6.2 6.2 ns TA aperture jitter 7.0 15 15 15 ps(rms) AJ slew rate 400 V/µSSR settling time 12 ns ST

NOISE and DISTORTION (20MSPS)

Signal-to-Noise Ratio (no harmonics)

4.985MHz; FS 68 66 66 66 dB SNR2

9.663MHz; FS 68 66 66 66 dB SNR3

Spurious-Free Dynamic Range

4.985MHz; FS -1dB 72 dBc SFDR2

9.663MHz; FS -1dB 72 63 58 55 dBc SFDR3

Intermodulation Distortion

= 5.58MHz @ FS -7dB; f2 = 5.70MHz @ FS -7dB -70 dBc IMD 3dB bandwidth (full power) 100 MHz BW

NOISE and DISTORTION (5MSPS, low bias)

Signal-to-Noise Ratio (no harmonics)

2.4MHz; FS 70 68 68 67 dB SNR1

Spurious-Free Dynamic Range

2.4MHz; FS -1dB 78 66 66 64 dBc SFDR1

NOISE and DISTORTION (25.6MSPS, high bias)

Signal-to-Noise Ratio (no harmonics)

9.894MHz; FS 67 63 63 63 dB SNR4

Spurious-Free Dynamic Range

9.894MHz; FS-1dB 67 59 53 48 dBc SFDR4

DC ACCURACY and PERFORMANCE

differential non-linearity dc; FS 0.5 1.0 1.0 1.0 LSB DNL integral non-linearity dc; FS 1.2 3.5 3.5 3.5 LSB INL common mode rejection ratio dc 60 dB CMRR missing codes 0 0 0 0 codes MC mid-scale offset 5.0 25 25 25 mV VIO

temperature coefficient 15 µV/°C DVIO gain error 1.0 5.0 5.0 5.0 %FS GE power supply rejection

dda

dc 55 dB PSRA

ddd

dc 50 dB PSRD

VOLTAGE REFERENCE CHARACTERISTICS

positive reference voltage (internal) 3.25 3.24-3.26 3.24-3.26 3.24-3.26 V VREFP negative reference voltage (internal) 1.25 1.24-1.26 1.24-1.26 1.24-1.26 V VREFN differential reference voltage (Vrefp - Vrefn) 2.0 1.98-2.02 1.98-2.02 1.98-2.02 V VDIFF

ANALOG INPUT PERFORMANCE

common mode range 2 - 3 V VCM differential range ± 2 V VDM

analog input bias current ±0.1 ±1.0 ±1.0 ±1.0 µA IBN analog input capacitance 5.0 10 10 10 pF CIN

DIGITALINPUTS

CMOS input voltage logic LOW 1 1 1 V VIL

logic HIGH 4.0 4.0 4.0 V VIH

CMOS input current logic LOW ±0.1 ±1.0 ±1.0 ±1.0 µA IIL

logic HIGH ±0.1 ±1.0 ±1.0 ±1.0 µA IIH

DIGITALOUTPUTS

CMOS output voltage logic LOW 0.25 0.5 0.5 0.5 V VOL

logic HIGH 4.8 4.5 4.5 4.5 V VOH

TIMING

maximum conversion rate 30 30 30 30 MSPS CR minimum conversion rate 10 10 10 10 KSPS CRM data hold time 7.0 4.5 4.5 4.5 ns THLD pipeline delay 6.5 6.5 6.5 6.5 clocks

POWER REQUIREMENTS

supply current (+V

) 44 60 60 60 mA IDD power dissipation 20MSPS 220 300 300 300 mW PDM power dissipation (low bias) 5MSPS 65 mW PDL power dissipation (high bias) 30MSPS 400 mW PDH

Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters.

CLC949 Electrical Characteristics

(+VDD= +5V, Medium Bias (200µA): unless specified)

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CLC949 Typical Performance Characteristics

(+VDD= + 5V, Med Bias, Fs= 20MSPS: unless specified)

Output Spectrum 1MHz

Output Level (dBFS)

Frequency (MHz)

-40



-120

-80

-20

-60

-100

Output Spectrum 9MHz

Output Level (dBFS)

Frequency (MHz)

-40



-120

-80

-20

-60

-100

Output Spectrum 15MHz

Output Level (dBFS)

Frequency (MHz)

-40



-120

-80

-20

-60

-100

SNR & SFDR vs. Input Amplitude 1MHz

SNR (dB) & SFDR (dBc)

Input Amplitude (dBFS)

-50

-30

-10

SNR

SFDR

-40 -20 0

SNR & SFDR vs. Input Amplitude 5MHz

SNR (dB) & SFDR (dBc)

Input Amplitude (dBFS)

-50

-30

-10



SNR

SFDR

-40 -20 0

SNR & SFDR vs. Input Amplitude 9MHz

SNR (dB) & SFDR (dBc)

Input Amplitude (dBFS)

-50

-30

-10



SNR

SFDR

-40 -20 0

SNR & SFDR vs. Input Frequency

SNR (dB), SFDR (dBc)

Input Frequency (MHz)

100k

10M

100M

FS = 20MHz

SFDR (dBc)

SNR (dB)

SNR vs. Sample Rate vs. Bias

SNR (dB)

Sample Rate (MSPS)

0.1

1.0



100

Low Bias

High Bias

Medium Bias

Fin = 5MHz

SFDR vs. Sample Rate vs. Bias

SFDR (dBc)

Sample Rate (MSPS)

0.1

1.0



100

Low Bias

Medium Bias

High Bias

Fin = 5MHz

Two Tone Intermodulation Distortion

Output Level (dBFS)

Frequency (MHz)

-40



-120

-80

-20

-60

-100

Integral Non-Linearity

INL (LSBs)

Output Code

2.5

1.5

1000

2000

-2.5

0.5

3000 4000

-0.5

-1

-1.5

-2

Differential Non-Linearity

DNL (LSBs)

Output Code

1.5

0.5

1000

2000



-1.5

-0.5

3000 4000

-1

Pulse Settling Response

ADC Output Code

Time (ns)

4000

100

150

1000

2000

200

3000

SFDR vs. Input Frequency

40°C

80°C

60°C

0°C

20°C

-20°C

SFDR (dBc)

Input Frequency (MHz)

100

I/O Timing (Convert CLK & Bit Skew)

Time (ns)

400

300



100

200

812

Output Data

Convert

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Recommended Operating Conditions Absolute Maximum Ratings*

supply voltage (V

) +5V ±5% differential voltage between any two GND’s <10mV analog input voltage range (full scale) 1.25 – 3.25V digital input voltage range 0 to V

operating temperature range 0°C to 70°C clock pulse-width high (C

pwh

) >25ns

supply voltage (V

) -0.5V to +7V differential voltage between any two GND’s 200mV analog input voltage range -0.5V to +V

digital input voltage range -0.5V to +V

output short circuit duration (one pin to gnd) infinite junction temperature +175°C storage temperature range -65°C to +150°C lead solder duration (+300°C) 10 sec

*NOTE: Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure to maximum ratings for extended periods may affect device reliability.

Pinout & Pin Description and Usage

References (V

REFN

, V

REFP

, V

REFNO

, V

REFPO

, V

REFNC

REFPC

, V

REFMO

)

To use the internal references, connect V

REFPO

to V

REFP

and V

REFNO

to V

REFN

. The nominal value for V

REFPO

3.25V and for V

REFNO

is 1.25V. V

REFPC

and V

REFNC

are internal reference points which should be bypassed to GND with a 0.1µF capacitor. V

REFMO

is an output voltage that is equal to the mid point of the reference range and can be used to apply the appropriate offset to the analog inputs. For a more detailed discussion on references, see the paragraph on references in the applications section of this datasheet.

Analog Input (V

INP

, V

INN

)

The analog input to the CLC949 is a differential signal applied to V

INP

and V

INN

. For more detail on driving the inputs, see the paragraphs in the applications section of this datasheet.

Power Supplies and Grounds (V

DDA

, V

DDD

, GNDA, GNDD)

The power and ground pins of the CLC949 are split into those that supply the analog portions of the integrated circuit (V

DDA

, GNDA) and the digital portions of the chip

DDD

, GNDD). If your system uses separate power and ground planes, then performance can be improved by making use of the appropriate pins. In many systems, the power pins will all be tied together and the GND pins

will all be tied together. For more detailed discussion, please refer to the paragraph on power and grounds in the applications section of the databook.

Clock (CLK)

The CLK accepts a CMOS clock input. Samples are taken on the falling edges of the CLK and data emerges 6 1/2 clock cycles later, on to the rising edge of the CLK.

Output Data (D1-D12, MSBINV, OE\)

The data emerges from the CLC949 as CMOS level digital data on D1(MSB) through D12(LSB). The outputs can be put into a high impedance state by bringing OE\ high. There is an internal pulldown

resistor so that if this input is left open, the output data is enabled. MSBINV will invert the MSB of the output data. With MSBINV in the high state, the output data is two’s complement, when low, the output data format is offset binary. An internal pulldown resistor makes the output default to offset binary if MSBINV is left open.

Bias Control (BCO, BC1, BIASC)

The DC bias current of the CLC949 is controlled by three pins: BCO, BC1, and BIASC. BC0 and BC1 are digital CMOS inputs and set the bias current in accordance with the truth table below:

BC0 BC1 Bias Current PD@10MSPS

0 0 Default: Med Bias (200µA) 200mW 1 0 Analog Mode Variable 0 1 High Bias (400µA) 350mW 1 1 Low Bias (50µA) 75mW

In the analog mode, the user provides a bias current through the BIASC pin of the CLC949. As the bias current is increased, the power dissipation of the CLC949 is increased and the part becomes capable of increased conversion rates.

No connection - leave these pins open.

44-Pin PLCC

TOP VIEW

123456 44 43 42 41 40

DDDVDDDVDDD

CLK

BC1

DDAVDDAVDDAVREFNO

REFPO

2322

212019

24 25

26 27 28

GNDDGND

MSBINV

OE\

D1(MSB)

GND

13 14 15 16 17

BIASC

GND

INP

INN

GND

REFNC

REFPC

REFN

REFP

REFMO

33 32 31 30 29

D8 D7 D6 D5 D4 D3

D10

D11

D12(LSB)

BCO

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