NSC ADC10221CIVT Datasheet

January 2000

ADC10221
10-Bit, 15 MSPS, 98 mW A/D Converter with Internal
Sample and Hold

ADC10221 10-Bit, 15 MSPS, 98 mW A/D Converter with Internal Sample and Hold

General Description

The ADC10221 is the first in a family of low power, high per­formance CMOS analog-to-digital converters. It can digitize
signals to 10 bits resolution at sampling rates up to 20 MSPS
(15 MSPS guaranteed) while consuming a typical 98 mW
from a single 5V supply. Reference force and sense pins al­low the user to connect an external reference buffer amplifier
to ensure optimal accuracy. The ADC10221 is guaranteed to
have no missing codes over the full operating temperature
range. The unique two stage architecture achieves 9.2 Effec­tive Bits with a 10MHz input signal and a 20MHz clock fre­quency. Output formatting is straight binary coding.

To ease interfacing to 3V systems, the digital I/O power pins
of the ADC10221 can be tied to a 3V power source, making
the outputs 3V compatible. When not converting, power con­sumption can be reduced by pulling the PD (Power Down)
pin high, placing the converter into a low power standby
state, where it typically consumes less than 4 mW. The
ADC10221’s speed, resolution and single supply operation
make it well suited for a variety of applications in video, im­aging, communications, multimedia and high speed data ac­quisition. Low power, single supply operation ideally suit the
ADC10221 for high speed portable applications, and its
speed and resolution are ideal for charge coupled device
(CCD) input systems.

The ADC10221 comes in a space saving 32-pin TQFP and
operates over the industrial (−40˚C ≤ T
ture range.

≤ +85˚C) tempera-

A

Features

n Internal Sample-and-Hold
n Single +5V Operation
n Low Power Standby Mode
n Guaranteed No Missing Codes
n TTL/CMOS or 3V Logic Input/Output Compatible

Key Specifications

n Resolution 10 Bits
n Conversion Rate 20 MSPS (typ)

15 MSPS (min)

n ENOB 10 MHz Input,

20 MHz Clock 9.2 Bits (typ)

n DNL 0.35 LSB (typ)
n Power Consumption 98 mW (typ)
n Low Power Standby Mode

<

4 mW (typ)

Applications

n Digital Video
n Document Scanners
n Medical Imaging
n Electro-Optics
n Plain Paper Copiers
n CCD Imaging

Connection Diagram

DS101038-1

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© 2000 National Semiconductor Corporation DS101038 www.national.com

Ordering Information

ADC10221

Block Diagram

Commercial

(−40˚C ≤ T

ADC10221CIVT TQFP

≤ +85˚C)

A

NS Package

DS101038-2

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Pin Descriptions and Equivalent Circuits

ADC10221

Pin
No.

Symbol Equivalent Circuit Description

Analog I/O

30 V

31 V

32 V

2V

1V

IN

REF

REF

REF

REF−

+

+

−

9 CLK

Analog Input signal to be converted. Conversion
range is V

REF

+

StoV

REF

−

S.

Analog input that goes to the high side of the

F

S

reference ladder of the ADC. This voltage should

+

force V

S to be in the range of 2.3V to 4.0V.

REF

Analog output used to sense the voltage at the top
of the ADC reference ladder.

Analog input that goes to the low side of the

F

S

reference ladder of the ADC. This voltage should
force V

S to be in the range of 1.3V to 3.0V.

REF−

Analog output used to sense the voltage at the
bottom of the ADC reference ladder.

Converter digital clock input. VINis sampled on the
falling edge of CLK input.

8PD

26 OE

14

thru

19

and

D0 -D9

22

thru

25

3, 7,

28

5, 10 V

V

A

D

Power Down input. When this pin is high, the
converter is in the Power Down mode and the data
output pins are in a high impedance state.

Output Enable pin. When this pin and the PD pin
are low, the output data pins are active. When this
pin or the PD pin is high, the output data pins are in
a high impedance state.

Digital Output pins providing the 10 bit conversion
results. D0 is the LSB, D9 is the MSB. Valid data is
present just after the falling edge of the CLK input.

Positive analog supply pins. These pins should be
connected to a clean, quiet voltage source of +5V.

and VDshould have a common supply and be

V

A

separately bypassed with 10µF to 50µF capacitors
in parallel with 0.1µF capacitors.

Positive digital supply pins. These pins should be
connected to a clean, quiet voltage source of +5V.

and VDshould have a common supply and be

V

A

separately bypassed with 10µF to 50µF capacitors
in parallel with 0.1µF capacitors.

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Pin Descriptions and Equivalent Circuits (Continued)

ADC10221

Pin

No.

Analog I/O

12, 21 V

4, 27,

29

6, 11 DGND

13, 20 DGND I/O The ground return of the digital output drivers.

Symbol Equivalent Circuit Description

Positive supply pins for the digital output drivers.

I/O

D

AGND

These pins should be connected to a clean, quiet
voltage source of +3V to +5V and be separately
bypassed with 10µF capacitors.

The ground return for the analog supply. AGND and
DGND should be connected together close to the
ADC10221 package.

The ground return for the digital supply. AGND and
DGND should be connected together close to the
ADC10221 pacjage.

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ADC10221

Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required,

Soldering Temp., Infrared, 10 sec. (Note 6) 300˚C
Storage Temperature −65˚C to +150˚C

please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Positive Supply Voltage (V=V
Voltage on Any I/O Pin −0.3V to (V

=

) 6.5V

V

A

D

or VD) +0.3V)

A

Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Package Dissipation at T

=

25˚C See (Note 4)

A

ESD Susceptibility (Note 5)

Human Body Model 1500V

±

25mA

±

50mA

Operating Ratings(Notes 1, 2)

Operating Temperature −40˚C ≤ T
V

Supply Voltage +4.5V to +5.5V

A,VD

V

I/O Supply Voltage +2.7V to 5.5V

D

V

Voltage Range 1.3V to (VA-1.0V)

IN

V

+ Voltage Range 2.3V to (VA-1.0V)

REF

V

− Voltage Range 1.3V to 3.0V

REF

PD, CLK, OE Voltage

−0.3V to + 5.5V

≤ +85˚C

A

Machine Model 200V

Converter Electrical Characteristics

The following specifications apply for V

=

C

20pF, f

L

CLK

=

15 MHz, R

=

S

=

+5.0V

A

25Ω. Boldface limits apply for T

Symbol Parameter Conditions

Static Converter Characteristics

INL Integral Non-Linearity
DNL Differential-Non Linearity

Resolution with No Missing
Codes

Zero Scale Offset Error −6 mV(max)
Full-Scale Error −6 mV(max)

Dynamic Converter Characteristics

=

f

IN

ENOB Effective Number of Bits

S/(N+D)

Signal-to-Noise Plus
Distortion Ratio

SNR Signal-to-Noise Ratio

THD Total Harmonic Distortion

SFDR

Spurious Free Dynamic
Range

DG Differential Gain Error f
DP Differential Phase Error f

Overrange Output Code V
Underrange Output Code V

=

f

IN

=

f

IN

=

f

IN

=

f

IN

=

f

IN

=

f

IN

=

f

IN

=

f

IN

=

f

IN

=

f

IN

=

f

IN

=

f

IN

=

f

IN

=

f

IN

=

IN

=

IN

>

IN

<

IN

BW Full Power Bandwidth 150 MHz
PSRR

Power Supply Rejection
Ratio

Change in Full Scale with 4.5V to

5.5V Supply Change

Reference and Analog Input Characteristics

V

IN

C

IN

I

IN

Analog Input Range
Analog VINInput

Capacitance
Input Leakage Current 10 µA

DC,VD

=

5.0V

DC,VD

=

A

I/O=5.0VDC,V

to T

T

MIN

MAX

+=+3.5VDC,V

REF

: all other limits T

Typical

(Note 8)

±

0.45

±

0.35

1.0 MHz

4.43 MHz
10 MHz, f

CLK

=

20 MHz

1.0 MHz

4.43 MHz
10 MHz, f

CLK

=

20 MHz

1.0 MHz

4.43 MHz
10 MHz, f

CLK

=

20 MHz

1.0 MHz

4.43 MHz
10 MHz, f

CLK

=

20 MHz

1.0 MHz

4.43 MHz
10 MHz, f

4.43 MHz, f

4.43 MHz, f
V

REF

V

REF

=

20 MHz

CLK

=

17.72 MHz 0.5

CLK

=

17.72 MHz 0.5 deg

CLK

+ 1023

− 0

9.5

9.5

9.2
59

59
57

60
60
58

−71

−70

−66
74

72
68

56 dB

5pF

−=+1.5VDC,

REF

=

25˚C(Note 7)

A

Limits

(Note 9)

±

1.0 LSB(max)

±

0.85 LSB(max)

Units

10 Bits

9.0

56

58

−59

Bits(min)

dB(min)

dB(min)

dB(min)

60

1.3

4.0

V(min)

V(max)

Bits

Bits

dB

dB
dB

dB
dB

dB
dB

dB
dB

%

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