NSC ADC10064CIWM, ADC10062CIWM, ADC10061CIWM Datasheet
June 1999
ADC10061/ADC10062/ADC10064
10-Bit 600 ns A/D Converter with Input Multiplexer and
Sample/Hold
ADC10061/ADC10062/ADC10064 10-Bit 600 ns A/D Converter with Input Multiplexer and
Sample/Hold
General Description
Using an innovative, patented multistep*conversion technique, the 10-bit ADC10061, ADC10062, and ADC10064
CMOS analog-to-digital converters offer sub-microsecond
conversion times yet dissipate a maximum of only 235 mW.
The ADC10061, ADC10062, and ADC10064 perform a
10-bit conversion in two lower-resolution “flashes”, thus
yielding a fast A/D without the cost, power dissipation, and
other problems associated with true flash approaches. The
ADC10061 is pin-compatible with the ADC1061 but much
faster, thus providing a convenient upgrade path for the
ADC1061.
The analog input voltageto the ADC10061, ADC10062, and
ADC10064 is sampled and held by an internal sampling circuit. Input signals at frequencies from dc to over 200 kHz
can therefore be digitized accurately without the need for an
external sample-and-hold circuit.
The ADC10062 and ADC10064 include a “speed-up” pin.
Connecting an external resistor between this pin and ground
reduces the typical conversion time to as little as 350 ns with
only a small increase in linearity error.
For ease of interface to microprocessors, the ADC10061,
ADC10062, and ADC10064 have been designed to appear
as a memory location or I/O port without the need for external interface logic.
*
U.S. Patent Number 4918449
Simplified Block Diagram
Features
n Built-in sample-and-hold
n Single +5V supply
n 1, 2, or 4-input multiplexer options
n No external clock required
n Speed adjust pin for faster conversions (ADC10062
and ADC10064). See ADC10662/4 for high speed
guaranteed performance.
Key Specifications
n Conversion time to 10 bits 600 ns typical,
n 900 ns max over temperature
n Sampling Rate 800 kHz
n Low power dissipation 235 mW (max)
n Total unadjusted error
n No missing codes over temperature
±
1.0 LSB (max)
Applications
n Digital signal processor front ends
n Instrumentation
n Disk drives
n Mobile telecommunications
*
ADC10061 Only
**
ADC10062 and ADC10064 Only
***
ADC10064 Only
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS011020 www.national.com
DS011020-1
Ordering Information
Industrial (−40˚C ≤ TA≤ +85˚C) Package
Connection Diagrams
Top View
ADC10061CIWM M20B Small Outline
ADC10062CIWM M24B Small Outline
ADC10064CIWM M28B Small Outline
DS011020-11
DS011020-12
Top View
Top View
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DS011020-13
Pin Descriptions
DVCC,AVCCThese are the digital and analog positive sup-
INT
S/H This is the Sample/Hold control input. When
RD
CS
S0, S1 On the multiple-input devices (ADC10062 and
V
REF−
V
REF+
ply voltage inputs. They should always be connected to the same voltage source, but are
brought out separately to allow for separate
bypass capacitors. Each supply pin should be
bypassed with a 0.1 µF ceramic capacitor in
parallel with a 10 µF tantalum capacitor to
ground.
This is the active low interrupt output. INT
goes low at the end of each conversion, and
returns to a high state following the rising edge
of RD.
this pin is forced low (and CS is low), it causes
the analog input signal to be sampled and initiates a new conversion.
This is the active low Read control input.
When this RD and CS are low, any data
present in the output registers will be placed
on the data bus.
This is the active low Chip Select control input.
When low, this pin enables the RD and S/H
pins.
ADC10064), these pins select the analog input
that will be connected to the A/D during the
conversion. The input is selected based on the
state of S0 and S1 when S/H makes its
High-to-Low transition (See the Timing Diagrams). The ADC10064 includes both S0 and
S1. The ADC10062 includes just S0, and the
ADC10061 includes neither.
,
These are the reference voltage inputs. They
may be placed at any voltage between GND
and V
, but V
CC
V
. An input voltage equal to V
REF−
duces an output code of 0, and an input voltage equal to (V
put code of 1023.
must be greater than
REF+
− 1 LSB) produces an out-
REF+
REF−
pro-
V
,
IN,VIN0
V
IN1,VIN2
V
IN3
These are the analog input pins. The
ADC10061 has one input (V
,
has two inputs (V
ADC10064 has four inputs (V
and V
). The impedance of the source
IN3
should be less than 500Ω for best accuracy
and V
IN0
), the ADC10062
IN
), and the
IN1
IN0,VIN1,VIN2
and conversion speed. For accurate conversions, no input pin (even one that is not selected) should be driven more than 50 mV
GND, AGND,
DGND
above V
These are the power supply ground pins. The
ADC10061 has a single ground pin (GND),
or 50 mV below ground.
CC
and the ADC10062 and ADC10064 have
separate analog and digital ground pins
(AGND and DGND) for separate bypassing of
the analog and digital supplies. The ground
pins should be connected to a stable,
noise-free system ground. For the devices
with two ground pins, both pins should be returned to the same potential.
DB0–DB9 These are the TRI-STATE
®
output pins.
SPEED ADJ (ADC10062 and ADC10064 only). This pin is
normally left unconnected, but by connecting a
resistor between this pin and ground, the conversion time can be reduced. See the Typical
Performance Curves and the table of Electrical Characteristics.
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Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
+
=
Supply Voltage (V
Voltage at Any Input or Output −0.3V to V
Input Current at Any Pin (Note 3) 5 mA
Package Input Current (Note 3) 20 mA
Power Dissipation (Note 4) 875 mW
ESD Susceptability (Note 5) 2000V
Soldering Information (Note 6)
Vapor Phase (60 Sec)
Infrared (15 Sec)
AV
=
) −0.3V to +6V
DV
CC
CC
+
+ 0.3V
215˚C
220˚C
Storage Temperature Range −65˚C to +150˚C
Junction Temperature 150˚C
Operating Ratings (Notes 1, 2)
Temperature Range T
ADC10061CIWM,
ADC10062CIWM,
ADC10064CIWM −40˚C ≤ T
Supply Voltage Range 4.5V to 5.5V
MIN
≤ TA≤ T
≤ +85˚C
A
MAX
Converter Characteristics
The following specifications apply for V
otherwise specified. Boldface limits apply for T
+
=
+5V, V
A
REF(+)
=
=
+5V, V
REF(−)
=
T
to T
T
J
Min
Max
Symbol Parameter Conditions
Resolution 10 Bits
Integral Linearity Error R
=
18 kΩ
SA
Offset Error
Full-Scale Error
Total Unadjusted Error All Suffixes, R
=
SA
Missing Codes 0 (max)
+
=
Power Supply Sensitivity V
THD Total Harmonic Distortion f
SNR Signal-to-Noise Ratio f
Effective Number of Bits f
R
R
V
V
V
V
V
V
REF
REF
REF(+)
REF(−)
REF(+)
REF(−)
IN
IN
Reference Resistance 650 400 Ω (min)
Reference Resistance 650 900 Ω (max)
V
Input Voltage V++ 0.05 V (max)
REF(+)
V
Input Voltage GND − 0.05 V (min)
REF(−)
V
Input Voltage V
REF(+)
V
Input Voltage V
REF(−)
Input Voltage V++ 0.05 V (max)
Input Voltage GND − 0.05 V (min)
OFF Channel Input Leakage Current
ON Channel Input Leakage Current
±
5V
+
=
±
5V
V
=
10 kHz, 4.85 V
IN
=
f
160 kHz, 4.85 V
IN
=
10 kHz, 4.85 V
IN
=
f
160 kHz, 4.85 V
IN
=
10 kHz, 4.85 V
IN
=
f
160 kHz, 4.85 V
IN
+
CS=V
,V
CS=V+,V
5%,V
10%,V
=
IN
=
IN
REF
REF
+
V
+
V
=
GND, and Speed Adjust pin unconnected unless
; all other limits T
18 kΩ
=
4.5V
=
4.5V
P-P
P-P
P-P
P-P
P-P
P-P
=
A
Typical
(Note 7)
±
0.5
±
0.5
±
1/16
0.06
0.08
61
60
9.6
9.4
0.01
±
1
=
T
+25˚C.
J
Limit
(Note 8)
±
1.0/±1.5 LSB (max)
±
1 LSB (max)
±
1 LSB (max)
±
1.5/±2.0 LSB (max)
3
±
⁄
8
REF(−)
REF(+)
3
−3
Units
(Limit)
LSB
LSB (max)
%
%
dB
dB
Bits
Bits
V (min)
V (max)
µA (max)
µA (max)
DC Electrical Characteristics
The following specifications apply for V
wise specified. Boldface limits apply for T
+
=
+5V, V
=
5V V
REF(+)
=
=
T
A
T
J
MIN
to T
REF(−)
MAX
Symbol Parameter Conditions
+
V
IN(1)
V
IN(0)
I
IN(1)
I
IN(0)
V
OUT(1)
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Logical “1” Input Voltage V
Logical “0” Input Voltage V
Logical “1” Input Current V
Logical “0” Input Current V
Logical “1” Output Voltage V
=
5.5V 2.0 V (min)
+
=
4.5V 0.8 V (max)
=
5V 0.005 3.0 µA (max)
IN(1)
0V −0.005 −3.0 µA (max)
IN(0)
+
=
4.5V, I
+
=
4.5V, I
V
OUT
OUT
=
=
=
GND, and Speed Adjust pin unconnected unless other-
; all other limits T
−360 µA
−10 µA
=
=
T
+25˚C.
A
J
Typical
(Note 7)
Limit
(Note 8)
2.4
4.25
Units
(Limit)
V (min)
V (min)
DC Electrical Characteristics (Continued)
+
The following specifications apply for V
wise specified. Boldface limits apply for T
=
+5V, V
=
A
Symbol Parameter Conditions
V
I
OUT
DI
AI
OUT(0)
CC
CC
Logical “0” Output Voltage V
TRI-STATE®Output Current V
DVCCSupply Current CS=S/H=RD=0, R
AVCCSupply Current CS=S/H=RD=0, R
=
5V V
REF(+)
=
T
T
J
+
=
4.5V, I
=
OUT
=
V
OUT
MIN
5V
0V
REF(−)
to T
; all other limits T
MAX
=
1.6 mA 0.4 V (max)
OUT
CS=S/H=RD=0, R
CS=S/H=RD=0, R
=
GND, and Speed Adjust pin unconnected unless other-
=
∞
SA
=
18 kΩ
SA
=
∞
SA
=
18 kΩ
SA
=
=
T
+25˚C.
A
J
Typical
(Note 7)
0.1
−0.1
1.0
1.0
30
30
Limit
(Note 8)
50
−50
2
45
Units
(Limit)
µA (max)
µA (max)
mA (max)
mA (max)
mA (max)
mA (max)
AC Electrical Characteristics
The following specifications apply for V
nected unless otherwise specified. Boldface limits apply for T
Symbol Parameter Conditions
t
CONV
t
CRD
t
ACC1
t
ACC2
t
SH
t
1H,t0H
t
INTH
t
P
t
MS
t
MH
C
VIN
C
OUT
C
IN
Note 1: Absolute Maximum Ratingsindicatelimitsbeyondwhich damage to the device may occur.Operating Ratings indicate conditions for which the device is functional. These ratings do not guarantee specific performance limits, however. For guaranteed specifications and test conditions, see the Electrical Characteristics. The
guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed
test conditons.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (V
to 5 mA or less. The 20 mA package input current limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
allowable power dissipation at any temperature is P
the maximum derated power dissipation will be reached only during fault conditions. For these devices, T
tables below:
Mode 1 Conversion Time from
Rising Edge of S/H to Falling Edge
of INT
Mode 2 Conversion Time R
Access Time (Delay from Falling
Edge of RD to Output Valid)
Access Time (Delay from Falling
Edge of RD to Output Valid)
Minimum Sample Time (
TRI-STATE Control (Delay from
Rising Edge of RD to High-Z State)
Delay from Rising Edge of RD to
Rising Edge of INT
Delay from End of Conversion to
Next Conversion
Multiplexer Control Setup Time 10 75 ns (max)
Multiplexer Hold Time 10 40 ns (max)
Analog Input Capacitance 35 pF (max)
Logic Output Capacitance 5 pF (max)
Logic Input Capacitance 5 pF (max)
) at any pin exceeds the power supply rails (V
IN
+
=
D
+5V, t
=
(T
=
t
r
f
R
SA
R
SA
SA
Mode 2, R
Mode 1; C
Mode 2; C
Figure 1
R
L
C
L
=
20 ns, V
=
∞
=
18k
=
∞
); (Note 8) 250 ns (max)
=
1k, C
=
100 pF
SA
L
L
L
A
=
=
REF(+)
=
T
=
100 pF
100 pF
=
10 pF
J
18k
=
5V, V
=
T
MIN
REF(−)
to T
MAX
(Note 7)
=
GND, and Speed Adjust pin uncon-
; all other limits T
Typical
600
=
A
Limit
(Note 8)
750/900
375
850
1400 ns(max)
530
30 60 ns (max)
900 t
+50 ns (max)
CRD
30 60 ns (max)
25 50 ns (max)
50 ns (max)
<
IN
)/θJAor the number given in the Absolute Maximum Ratings, whichever is lower. In most cases,
JMAX−TA
GND or V
>
V+) the absolute value of current at that pin should be limited
IN
, θJAand the ambient temperature, TA. The maximum
JMAX
for a board-mounted device can be found from the
JMAX
=
T
+25˚C.
J
Units
(Limit)
ns(max)
ns
ns
Device θJA(˚C/W)
ADC10061CIWM 54
ADC10062CIWM 48
ADC10064CIWM 44
Note 5: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 6: See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in a current National Semicon-
ductor Linear Data Book for other methods of soldering surface mount devices.
Note 7: Typicals are at +25˚C and represent must likely parametric norm.
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