NSC ADC1005CCJ-1, ADC1005BCJ-1, ADC1005BCJ Datasheet

ADC1005
10-Bit µP Compatible A/D Converter

ADC1005 10-Bit µP Compatible A/D Converter

June 1999

General Description

The ADC1005 is a CMOS 10-bit successive approximation
A/D converter.The 20-pin ADC1005 outputs 10-bit data in a
two-byte format for interface with 8-bit microprocessors.

The ADC1005 has differential inputs to permit rejection of
common-mode signals, allow the analog input range to be
offset, and also to permit the conversion of signals not re­ferred to ground. In addition, the reference voltage can be
adjusted, allowing smaller voltage spans to be measured
with 10-bit resolution.

Connection Diagram

ADC 1005 (for an 8–bit data bus)

Dual-In-Line Package

Features

n Easy interface to all microprocessors
n Differential analog voltage inputs
n Operates ratiometrically or with 5 V

or analog span adjusted voltage reference

n 0V to 5V analog input voltage range with single 5V

supply

n On-chip clock generator
n TLL/MOS input/output compatible
n 0.3" standard width 20-pin DIP

voltage reference

DC

Key Specifications

n Resolution 10 bits
n Linearity Error
n Conversion Time 50 µs

1

±

⁄2LSB and±1 LSB

DS005261-1

Top View

Ordering Information

Part Number Package Temperature Linearity

Outline Range Error

ADC1005BCJ-1 J20A 0˚C to +70˚C
ADC1005BCJ J20A −40˚C to +85˚C
ADC1005CCJ-1 J20A 0˚C to +70˚C
ADC1005CCJ J20A −40˚C to +85˚C

TRI-STATE®is a registered trademark of National Semiconductor Corporation.

© 1999 National Semiconductor Corporation DS005261 www.national.com

1

±

±

⁄2LSB

1 LSB

Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage (V
Logic Control Inputs −0.3V to +15V
Voltage at Other Inputs and Outputs −0.3V to V
Input Current Per Pin
Input Current Per Package
Storage Temperature Range −65˚C to +150˚C
Package Dissipation at T
Lead Temperature

(Soldering, 10 seconds)

) 6.5V

CC

CC

±

=

25˚C 875 mW

A

+0.3V

±

5mA

20 mA

Dual-In-Line Package (Ceramic) 300˚C
Surface Mount Package

Vapor Phase (60 seconds) 215˚C
Infrared (15 seconds) 220˚C

ESD Susceptibility (Note 8) 800V

Operating Ratings (Notes 1, 2)

Supply Voltage (V
Temperature Range T

ADC1005BCJ, ADC1005CCJ −40˚C≤TA≤+85˚C
ADC1005BCJ-1, ADC1005CCJ-1

) 4.5V to 6.0V

CC

MN≤TA≤TMAX

Electrical Characteristics

The following specifications apply for V

from T

MIN

to T

MAX

; All other limits T

=

5V, V

CC

=

=

T

A

j

Parameter Conditions ADC1005BCJ ADC1005BCJ-1, Limit

Converter Characteristics

Linearity Error (Note 3)
ADC1005BCJ
ADC1005BCJ-1
ADC1005CCJ
ADC1005CCJ-1, CCV
Zero Error
ADC1005BCJ
ADC1005BCJ-1
ADC1005CCJ
ADC1005CCJ-1, CCV
Fullscale Error
ADC1005BCJ
ADC1005BCJ-1
ADC1005CCJ
ADC1005CCJ-1, CCV
Reference MIN 4.8 2.2 4.8 2.4 2.2 kΩ
Input MAX 4.8 8.3 4.8 7.6 8.3 kΩ
Resistance
Common-Mode MIN V
Input (Note 4) MAX V

(+) or VIN(−) GND−0.05 GND−0.05 GND−0.05 V

IN

DC Common-Mode Over

Common-Mode

Error Input Range

=

±

Power Supply Sensitivity V

CC

V

REF

5V

=

DC

4.75V

%

5

25˚C.

REF

=

5V, f

=

1.8 MHz unless otherwise specified. Boldface limits apply

CLK

ADC1005CCJ ADC1005CCJ-1

Typ Tested Design Typ Tested Design

(Note 5) Limit Limit (Note 5) Limit Limit

(Note 6) (Note 7) (Note 6) (Note 7)

±

0.5 LSB

±

0.5

±

1 LSB

±

1

±

0.5 LSB

±

0.5

±

1 LSB

±

1

±

0.5 LSB

±

0.5

±

1 LSB

±

1

+0.05 VCC+0.05 VCC+0.05 V

CC

1

±

⁄

8

1

±

⁄

8

1

±

⁄

4

1

±

⁄

4

1

±

⁄

8

1

±

⁄

8

1

±

⁄

4

1

±

⁄

4

±

0.5 LSB

±

1 LSB

±

0.5 LSB

±

1 LSB

±

0.5 LSB

±

1 LSB

1

±

⁄

4

1

±

⁄

4

Units

LSB

LSB

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Electrical Characteristics (Continued)

The following specifications apply for V

from T

MIN

to T

MAX

; All other limits T

=

5V, V

CC

=

=

T

A

j

Parameter Conditions ADC1005BCJ ADC1005BCJ-1, Limit

DC Characteristics

Logical “1” Input V

V

IN(1)

Voltage MIN (except CLK
V

, Logical “0” Input V

IN(0)

Voltage MAX (Except CLK
I

, Logical “1” Input V

IN

=

5.25V 2.0 2.0 2.0 V

CC

=

CC

=

5.0V 0.005 1 0.005 1 1 µA

IN

)

IN

4.75V 0.8 0.8 0.8 V
)

IN

Current MAX
I

, Logical “0” Input V

IN

=

0V −0.005 −1 −0.005 −1 −1 µA

IN

Current MAX
V

, Minimum CLK

T+(MIN)

IN

Positive going Threshold 3.1 2.7 3.1 2.7 2.7 V
Voltage
V

, Maximum CLK

T(MAX)

IN

Positive going Threshold 3.1 3.5 3.1 3.5 3.5 V
Voltage
V

, Minimum CLK

T−(MIN)

IN

Negative going Threshold 1.8 1.5 1.8 1.5 1.5 V
Voltage
V

, Maximum CLK

T−(MAX)

IN

Negative going Threshold 1.8 2.1 1.8 2.1 2.1 V
Voltage
V

, Minimum CLK

H(MIN)

Hysteresis (V
V

, Maximum CLK

H(MAX)

Hysteresis (V
V

, Logical “1” V

OUT(1)

Output Voltage MIN I

V

, Logical “0” V

OUT(0)

Output Voltage MAX I
I

, TRI-STATE Output V

OUT

Current MAX V
I

, Output Source V

SOURCE

T+-VT−

T+-VT−

IN

)

IN

)

=

4.75V

CC

=

−360 µA 2.4 2.8 2.4 V

OUT

=

I

−10 µA 4.5 4.6 4.5 V

OUT

=

4.75V 0.4 0.34 0.4 V

CC

=

1.6 mA

OUT

=

0V −0.01 −3 −0.01 −0.3 −3 µA

OUT

=

5V 0.01 3 0.01 0.3 3 µA

OUT

=

0V −14 −6.5 −14 −7.5 −6.5 mA

OUT

Current MIN
I

, Output Sink V

SINK

=

5V 16 8.0 16 9.0 8.0 mA

OUT

Current MIN
I

, Supply Current MAX f

CC

=

1.8 MHz 1.5 3 1.5 2.5 3 mA

CLK

CS=“1”

25˚C.

REF

=

5V, f

=

1.8 MHz unless otherwise specified. Boldface limits apply

CLK

ADC1005CCJ ADC1005CCJ-1

Typ Tested Design Typ Tested Design

(Note 5) Limit Limit (Note 5) Limit Limit

(Note 6) (Note 7) (Note 6) (Note 7)

1.3 0.6 1.3 0.6 0.6 V

1.3 2.0 1.3 2.0 2.0 V

Units

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AC Electrical Characteristics

The following specifications apply for V

its apply from T

MIN

to T

MAX

; All other limits T

=

5V, V

CC

Parameter Conditions (Note 5) Limit Limit Units

, Clock Frequency MIN 0.2 0.2 MHz

f

CLK

MAX 2.6 2.6 MHz

Clock Duty Cycle MIN 40 40

MAX 60 60

t

, Conversion Time MIN 80 80 1/f

C

MAX 90 90 1/f
MIN f
MAX f

t

, Minimum WR Pulse

W(WR)L

Width

, Access Time (Delay from

t

ACC

falling edge of RD to Output
Data Valid)

t

, TRI-STATE Control

1H,t0H

(Delay from Rising Edge of RD
to Hi-Z State)

t

, Delay from Falling

WI,tRI

Edge of WR or RD to Reset of

=

1.8 MHz 45 45 µs

CLK

=

1.8 MHz 50 50 µs

CLK

CS=0

CS=0

=

C

100 pF, R

L

=

=

10k, C

R

L

L

=

L

=

2k, C

100 pF 145 230 230 ns

L

R

INTR

, INTR to 1st Read Set-up

t

IRS

Time
C

, Capacitance of Logic

IN

Inputs

, Capacitance of Logic

C

OUT

Outputs

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.

Note 2: All voltages are measured with respect to ground.
Note 3: Linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line which passes through the end points of the transfer

characteristic.
Note 4: For V

voltages one diode drop below ground or one diode drop greater thanV
can cause this input diode to conduct, especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias
of either diode. This means that as long as the analog V
absolute 0 V

Note 5: Typicals are at 25˚C and represent most likely parametric norm.
Note 6: Tested and guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 7: Guaranteed, but not 100%production tested. These limits are not used to calculate outgoing quality levels.
Note 8: Human body model, 100 pF discharged through a 1.5 kΩ resistor.

DC

the digital output code will be 00 0000 0000. Two on-chip diodes are tied to each analog input which will forward conduct for analog input

IN(−)≥VIN(+)

to5VDCinput voltage range will therefore require a minimum supply voltage of 4.950 VDCover temperature variations, initial tolerance and loading.

IN

=

REF

=

=

T

25˚C.

A

j

5V,V

REF

=

= 20 ns unless otherwise specified. Boldface lim-

5V, t

r=tf

Typ Tested Design Limit

(Note 6) (Note 7)

100 150 150 ns

170 300 300 ns

=

2k

L

10 pF 125 200 ns

300 450 450 ns

400 550 550 ns

5 7.5 pF

5 7.5 pF

supply.Becareful,duringtestingatlowVCClevels (4.5V), as high level analog inputs (5V)

CC

does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an

%
%

CLK
CLK

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