NSC 5962-8865101RA, 5962-88651012A Datasheet
54FCT533
Octal Transparent Latch with TRI-STATE
®
Outputs
General Description
The FCT533 consists of eight latches with TRI-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is low,thedatasatisfying the input timing requirements is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state.
Features
n Eight latches in a single package
n TTL input and output level compatible
n CMOS power consumption
n TRI-STATE outputs drive bus lines or buffer memory
address registers
n Output sink capability of 32mA, source capability of 12
mA
n Inverted version of the FCT373
n Standard Microcircuit Drawing (SMD) 5962-8865101
Logic Symbols
Pin
Names
Description
D
0–D7
Data Inputs
LE Latch Enable Input
OE
Output Enable Input
O
0–O7
TRI-STATE Latch
Outputs
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
FACT
™
is a trademark of Fairchild Semiconductor Corporation.
DS100969-1
IEEE/IEC
DS100969-2
September 1998
54FCT533 Octal Transparent Latch with TRI-STATE Outputs
© 1998 National Semiconductor Corporation DS100969 www.national.com
Connection Diagrams
Functional Description
The FCT533 contains eight D-type latches with TRI-STATE
standard outputs. When the Latch Enable (LE) input is
HIGH, data on the D
n
inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will
change state each time its D input changes. When LE is
LOW, the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE standard outputs are controlled
by the Output Enable (OE) input. When OE is LOW,the standard outputs are in the 2-state mode. When OE is HIGH, the
standard outputs are in the high impedance mode but this
does not interfere with entering new data into the latches.
Truth Table
Inputs Outputs
LE OE
D
n
O
n
XHX Z
HLL H
HLH L
LLX O
0
H
=
HIGH Voltage Level
L=LOW Voltage Level
Z=High Impedance
X=Immaterial
O
0
=
Previous O
0
before HIGH to Low transition of Latch Enable
Logic Diagram
Pin Assignment
for DIP and Flatpak
DS100969-3
Pin Assignment
for LCC
DS100969-4
DS100969-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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