NSC 5962-8855001SA, 5962-8855001RA, 5962-88550012A Datasheet

TL/F/9511

54F/74F273 Octal D Flip-Flop

May 1995

54F/74F273
Octal D Flip-Flop

General Description

The ’F273 has eight edge-triggered D-type flip-flops with in­dividual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR

) inputs load and reset

(clear) all flip-flops simultaneously.

The register is fully edge-triggered. The state of each D in­put, one setup time before the LOW-to-HIGH clock tran­sition, is transferred to the corresponding flip-flop’s Q out­put.

All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR

input. The
device is useful for applications where the true output only is
required and the Clock and Master Reset are common to all
storage elements.

Features

Y

Ideal buffer for MOS microprocessor or memory

Y

Eight edge-triggered D flip-flops

Y

Buffered common clock

Y

Buffered, asynchronous Master Reset

Y

See ’F377 for clock enable version

Y

See ’F373 for transparent latch version

Y

See ’F374 for TRI-STATEÉversion

Y

Guaranteed 4000V minimum ESD protection

Commercial Military

Package

Package Description

Number

74F273PC N20A 20-Lead (0.300×Wide) Molded Dual-In-Line

54F273DM (Note 2) J20A 20-Lead Ceramic Dual-In-Line

74F273SC (Note 1) M20B 20-Lead (0.300×Wide) Molded Small Outline, JEDEC

74F273SJ (Note 1) M20D 20-Lead (0.300×Wide) Molded Small Outline, EIAJ

54F273FM (Note 2) W20A 20-Lead Cerpack

54F273LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C

Note 1: Devices also available in 13×reel. Use suffixeSCX and SJX.

Note 2: Military grade device with environmental and burn-in processing. Use suffix

e

DMQB, FMQB and LMQB.

Logic Symbols

TL/F/9511– 3

IEEE/IEC

TL/F/9511– 5

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

C

1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.

Connection Diagrams

Pin Assignment for

DIP, SOIC and Flatpak

TL/F/9511– 1

Pin Assignment

for LCC

TL/F/9511– 2

Unit Loading/Fan Out

54F/74F

Pin Names Description

U.L. Input I

IH/IIL

HIGH/LOW Output IOH/I

OL

D0–D

7

Data Inputs 1.0/1.0 20 mA/b0.6 mA

MR

Master Reset (Active LOW) 1.0/1.0 20 mA/b0.6 mA

CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 mA/

b

0.6 mA

Q0–Q

7

Data Outputs 50/33.3

b

1 mA/20 mA

Mode Select-Function Table

Operating Mode

Inputs Output

MR CP D

n

Q

n

Reset (Clear) L X X L

Load ‘1’ H L hH

Load ‘0’ H L lL

H

e

HIGH Voltage Level steady state

h

e

HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock
transition

L

e

LOW Voltage Level steady state

I

e

LOW Voltage Level one setup time prior to the LOW-to-HIGH clock
transition
X

e

Immaterial

L

e

LOW-to-HIGH clock transition

Logic Diagram

TL/F/9511– 4

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

2

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Storage Temperature

b

65§Ctoa150§C

Ambient Temperature under Bias

b

55§Ctoa125§C

Junction Temperature under Bias

b

55§Ctoa175§C

Plastic

b

55§Ctoa150§C

V

CC

Pin Potential to

Ground Pin

b

0.5V toa7.0V

Input Voltage (Note 2)

b

0.5V toa7.0V

Input Current (Note 2)

b

30 mA toa5.0 mA

Voltage Applied to Output

in HIGH State (with V

CC

e

0V)

Standard Output

b

0.5V to V

CC

TRI-STATE Output

b

0.5V toa5.5V

Current Applied to Output

in LOW State (Max) twice the rated I

OL

(mA)

ESD Last Passing Voltage (min) 4000V

Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.

Note 2: Either voltage limit or current limit is sufficient to protect inputs.

Recommended Operating
Conditions

Free Air Ambient Temperature

Military

b

55§Ctoa125§C

Commercial 0

§

Ctoa70§C

Supply Voltage

Military

a

4.5V toa5.5V

Commercial

a

4.5V toa5.5V

DC Electrical Characteristics

Symbol Parameter

54F/74F

Units V

CC

Conditions

Min Typ Max

V

IH

Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

V

IL

Input LOW Voltage 0.8 V Recognized as a LOW Signal

V

CD

Input Clamp Diode Voltage

b

1.2 V Min I

IN

eb

18 mA

V

OH

Output HIGH Mil 2.5 I

OH

eb

1mA

Voltage 10% V

CC

2.5 V Min

5% V

CC

2.7

V

OL

Output LOW Mil 0.5 I

OL

e

20 mA

Voltage 10% V

CC

0.5 V Min

5% V

CC

0.5

I

IH

Input HIGH 54F 20.0

mA Max

V

IN

e

2.7V

Current 74F 5.0

I

BVI

Input HIGH Current 54F 100

mA Max

V

IN

e

7.0V

Breakdown Test 74F 7.0

I

CEX

Output HIGH 54F 250

mA Max

V

OUT

e

V

CC

Leakage Current 74F 50

V

ID

Input Leakage

74F 4.75 V 0.0

I

ID

e

1.9 mA

Test All other pins grounded

I

OD

Output Leakage

74F 3.75 mA 0.0

V

IOD

e

150 mV

Circuit Current All other pins grounded

I

IL

Input LOW Current

b

0.6 mA Max V

IN

e

0.5V

I

OS

Output Short-Circuit Current

b

60

b

150 mA Max V

OUT

e

0V

I

CCH

Power Supply Current 44

mA Max

CPeL

I

CCL

56 D

n

eMRe

HIGH

3