NSC 5962-8671002JA, 5962-86710023A, 54F181SDMQB Datasheet
TL/F/9491
54F/74F181 4-Bit Arithmetic Logic Unit
August 1995
54F/74F181
4-Bit Arithmetic Logic Unit
General Description
The ’F181 is a 4-bit Arithmetic logic Unit (ALU) which can
perform all the possible 16 logic operations on two variables
and a variety of arithmetic operations. It is 40% faster than
the Schottky ALU and only consumes 30% as much power.
Features
Y
Full lookahead for high-speed arithmetic operation on
long words
Y
Guaranteed 4000V minimum ESD protection
Commercial Military
Package
Package Description
Number
74F181PC N24A 24-Lead (0.600×Wide) Molded Dual-In-Line
74F181SPC N24C 24-Lead (0.300×Wide) Molded Dual-In-Line
54F181DM (Note 2) J24A 24-Lead Ceramic Dual-In-Line
54F181SDM (Note 2) J24F 24-Lead (0.300×) Ceramic Dual-In-Line
74F181SC (Note 1) M24B 24-Lead (0.300×) Molded Small Outline, JEDEC
54F181FM (Note 2) W24C 24-Lead Cerpack
54F181LM (Note 2) E28A 24-Lead Ceramic Leadless Chip Carrier,Type C
Note 1: Devices also available in 13×reel. Use suffixeSCX.
Note 2: Military grade device with environmental and burn-in processing. Use suffix
e
DMQB, FMQB and LMQB.
Connection Diagrams
Pin Assignment
for DIP, SOIC and Flatpak
TL/F/9491– 1
Pin Assignment
for LCC
TL/F/9491– 2
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
Logic Symbols
Active-HIGH Operands
TL/F/9491– 3
Active-LOW Operands
TL/F/9491– 4
IEEE/IEC
TL/F/9491– 10
Unit Loading/Fan Out
54F/74F
Pin Names Description
U.L. Input I
IH/IIL
HIGH/LOW Output IOH/I
OL
A0–A
3
A Operand Inputs (Active LOW) 1.0/3.0 20 mA/b1.8 mA
B
0–B3
B Operand Inputs (Active LOW) 1.0/3.0 20 mA/b1.8 mA
S
0–S3
Function Select Inputs 1.0/4.0 20 mA/b2.4 mA
M Mode Control Input 1.0/1.0 20 mA/b0.6 mA
C
n
Carry Input 1.0/5.0 20 mA/b3.0 mA
F0–F
3
Function Outputs (Active LOW) 50/33.3b1 mA/20 mA
A
e
B Comparator Output OC*/33.3 */20 mA
G
Carry Generate Output (Active LOW) 50/33.3b1 mA/20 mA
P
Carry Propagate Output (Active LOW) 50/33.3b1 mA/20 mA
C
na4
Carry Output 50/33.3b1 mA/20 mA
*OC-Open Collector
Functional Description
The ’F181 is a 4-bit high-speed parallel Arithmetic Logic
Unit (ALU). Controlled by the four Function Select inputs
(S
0–S3
) and the Mode Control input (M), it can perform all
the 16 possible logic operations or 16 different arithmetic
operations on Active HIGH or Active LOW operands. The
Function Table lists these operations.
When the Mode Control input (M) is HIGH, all internal carries are inhibited and the device performs logic operations
on the individual bits as listed. When the Mode Control input
is LOW, the carries are enabled and the device performs
arithmetic operations on the two 4-bit words. The device
incorporates full internal carry lookahead and provides for
either ripple carry between devices using the C
na4
output,
or for carry lookahead between packages using the signals
P
(Carry Propagate) and G (Carry Generate). In the Add
mode, P
indicates that F is 15 or more, while G indicates
that F
is 16 or more. In the Subtract mode P indicates that F
is zero or less, while G indicates that F is less than zero. P
and G are not affected by carry in. When speed requirements are not stringent, the ’F181 can be used in a simple
Ripple Carry mode by connecting the Carry output (C
n
a
4)
signal to the Carry input (C
n
) of the next unit. For high speed
operation the device is used in conjunction with a carry lookahead circuit. One carry lookahead package is required for
each group of four ’F181 devices. Carry lookahead can be
provided at various levels and offers high speed capability
over extremely long word lengths.
The A
e
B output from the device goes HIGH when all four F
outputs are HIGH and can be used to indicate logic equivalence over four bits when the unit is in the Subtract mode.
The A
e
B output is open collector and can be wired AND
with other A
e
B outputs to give a comparison for more than
four bits. The A
e
B signal can also be used with the C
na4
signal to indicate AlB and AkB.
The Function Table lists the arithmetic operations that are
performed without a carry in. An incoming carry adds a one
to each operation. Thus, select code LHHL generates A
minus B minus 1 (2s complement notation) without a carry
in and generates A minus B when a carry is applied. Because subtraction is actually performed by complementary
addition (1s complement), a carry out means borrow
; thus a
carry is generated when there is no underflow and no carry
is generated when there is underflow. As indicated, this device can be used with either active LOW inputs producing
active LOW outputs or with active HIGH inputs producing
active HIGH outputs. For either case the table lists the operations that are performed to the operands labeled inside the
logic symbol.
2
’F181 Operation Table
Logic Arithmetic Arithmetic
S
0S1S2S3
(MeH) (MeL, C
0
e
Inactive) (MeL, C
0
e
Active)
LLLL A A minus 1 A
HLL L A
#
B A
#
B minus 1 A#B
LHLL A
a
BA
#
Bminus 1 A#B
H H L L Logic ‘‘1’’ minus 1 (2s comp.) Zero
LLHL A
a
B A plus (AaB) A plus (AaB) plus 1
HLHL B
A
#
B plus (AaB)A
#
B plus (AaB) plus 1
LHHL AZB A minus B minus 1 A minus B
HHHL A
a
B A
a
B A
a
Bplus 1
LLLH A
#
B A plus (AaB) A plus (AaB plus 1
HLLH A
Z
B A plus B A plus B plus 1
LHLH B A
#
Bplus (AaB) A#B plus (AaB) plus 1
HHL H A
a
BA
a
BA
a
B plus 1
L L H H Logic ‘‘0’’ A plus A (2
c
A) A plus A (2cA) plus 1
HLHH A
#
B A plus A#B A plus A#B plus 1
LHHH A
#
B A plus A#B A plus A#B plus 1
H H H H A A A plus 1
LLLL A A A plus 1
HLL L A
a
B A
a
BA
a
B plus 1
LHLL A
#
BA
a
B A
a
Bplus 1
H H L L Logic ‘‘0’’ minus 1 (2s comp.) Zero
LLHL A
#
B A plus (A#B) A plus A#B plus 1
HLHL B
A
#
Bplus (AaB) A#B plus (AaB) plus 1
LHHL A
Z
B A minus B minus 1 A minus B
HHHL A
#
B A
#
Bminus 1 A#B
LLLH A
a
B A plus A#B A plus A#B plus 1
HLLH A
Z
B A plus B A plus B plus 1
LHLH B A
#
B plus (AaB)A
#
B plus (AaB) plus 1
HHL H A
#
BA
#
B minus 1 A#B
L L H H Logic ‘‘1’’ A plus A (2
c
A) A plus A (2cA) plus 1
HLHH A
a
B A plus (AaB) A plus (AaB) plus 1
LHHH A
a
B A plus (AaB) A plus (AaB) plus 1
H H H H A A minus 1 A
LLLL A A minus 1 A
HLL L A
a
BA
#
Bminus 1 A#B
LHLL A
#
B A
#
B minus 1 A#B
H H L L Logic ‘‘1’’ minus 1 (2s comp.) Zero
LLHL A
#
B A plus (AaB) A plus (AaB) plus 1
HLHL B A
#
Bplus (AaB) A#B plus (AaB) plus 1
LHHL A
Z
B A plus B A plus B plus 1
HHHL A
a
BA
a
BA
a
B plus 1
LLLH A
a
B A plus (AaB) A plus (AaB) plus 1
HLLH AZB A minus B minus 1 A minus B
LHLH B
A
#
B plus (AaB)A
#
B plus (AaB) plus 1
HHL H A
a
B A
a
B A
a
Bplus 1
L L H H Logic ‘‘0’’ A plus A (2
c
A) A plus A (2cA) plus 1
HLHH A
#
B A plus A#B A plus A#B plus 1
LHHH A
#
B A plus A#B A plus A#B plus 1
H H H H A A A plus 1
LLLL A A A plus 1
HLL L A
#
BA
a
B A
a
Bplus 1
LHLL A
a
B A
a
BA
a
B plus 1
H H L L Logic ‘‘0’’ minus 1 (2s comp.) Zero
LLHL A
a
B A plus A#B A plus A#B plus 1
HLHL B A
#
B plus (AaB)A
#
Bplus (AaB) plus 1
LHHL A
Z
B A plus B A plus B plus 1
HHHL A
#
BA
#
B minus 1 A#B
LLLH A
#
B A plus A#B A plus A#B plus 1
HLLH A
Z
B A minus B minus 1 A minus B
LHLH B
A
#
Bplus (AaB) A#B plus (AaB) plus 1
HHL H A
#
B A
#
Bminus 1 A#B
L L H H Logic ‘‘1’’ A plus A (2cA) A plus A (2cA) plus 1
HLHH A
a
B A plus (AaB) A plus (AaB) plus 1
LHHH A
a
B A plus (AaB) A plus (AaB) plus 1
H H H H A A minus 1 A
a. All Input Data Inverted
b. All Input Data True
c. A Input Data Inverted;
B Input Data True
d. A Input Data True;
B Input Date Inverted
3
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