NSC 5962-8607201FA, 5962-8607201EA, 5962-86072012A Datasheet
TL/F/9488
54F/74F169 4-Stage Synchronous Bidirectional Counter
November 1994
54F/74F169
4-Stage Synchronous Bidirectional Counter
General Description
The ’F169 is a fully synchronous 4-stage up/down counter.
The ’F169 is a modulo-16 binary counter. Features a preset
capability for programmable operation, carry lookahead for
easy cascading and a U/D
input to control the direction of
counting. All state changes, whether in counting or parallel
loading, are initiated by the LOW-to-HIGH transition of the
clock.
Features
Y
Asynchronous counting and loading
Y
Built-in lookahead carry capability
Y
Presettable for programmable operation
Commercial Military
Package
Package Description
Number
74F169PC N16E 16-Lead (0.300×Wide) Molded Dual-In-Line
54F169DM (Note 2) J16A 16-Lead Ceramic Dual-In-Line
74F169SC (Note 1) M16A 16-Lead (0.150×Wide) Molded Small Outline, JEDEC
74F169SJ (Note 1) M16D 16-Lead (0.300×Wide) Molded Small Outline, EIAJ
Note 1: Devices also available in 13×reel. Use suffixeSCX and SJX.
Note 2: Military grade device with environmental and burn-in processing. Use suffix
e
DMQB.
Logic Symbols
TL/F/9488– 3
IEEE/IEC
’F169
TL/F/9488– 9
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.
Connection Diagrams
Pin Assignment for
DIP, SOIC and Flatpak
TL/F/9488– 1
Pin Assignment
for LCC
TL/F/9488– 2
Unit Loading/Fan Out
54F/74F
Pin Names Description
U.L. Input I
IH/IIL
HIGH/LOW Output IOH/I
OL
CEP Count Enable Parallel Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA
CET
Count Enable Trickle Input (Active LOW) 1.0/2.0 20 mA/b1.2 mA
CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 mA/
b
0.6 mA
P0–P
3
Parallel Data Inputs 1.0/1.0 20 mA/b0.6 mA
PE
Parallel Enable Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA
U/D Up-Down Count Control Input 1.0/1.0 20 mA/b0.6 mA
Q
0–Q3
Flip-Flop Outputs 50/33.3
b
1 mA/20 mA
TC
Terminal Count Output (Active LOW) 50/33.3
b
1 mA/20 mA
Functional Description
The ’F169 uses edge-triggered J-K type flip-flops and has
no constraints on changing the control or data input signals
in either state of the clock. The only requirement is that the
various inputs attain the desired state at least a setup time
before the rising edge of the clock and remain valid for the
recommended hold time thereafter. The parallel load operation takes precedence over other operations, as indicated in
the Mode Select Table. When PE
is LOW, the data on the
P
0–P3
inputs enters the flip-flops on the next rising edge of
the clock. In order for counting to occur, both CEP
and CET
must be LOW and PE must be HIGH; the U/D input then
determines the direction of counting. The Terminal Count
(TC
) output is normally HIGH and goes LOW, provided that
CET
is LOW, when a counter reaches zero in the Count
Down mode or reaches 15 for the ’F169 in the Count Up
mode. The TC
output state is not a function of the Count
Enable Parallel (CEP
) input level. Since the TC signal is derived by decoding the flip-flop states, there exists the possibility of decoding spikes on TC
. For this reason the use of
TC
as a clock signal is not recommended (see logic equa-
tions below).
1) Count Enable
e
CEP#CET#PE
2) Up: (’F169): TCeQ
0
#
Q
1
#
Q
2
#
Q
3
#
(Up)#CET
3) Down: TCeQ
0
#
Q
1
#
Q
2
#
Q
3
#
(Down)#CET
2
Logic Diagram
’F169
TL/F/9488– 5
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Mode Select Table
PE CEP CET U/D
Action on Rising
Clock Edge
HeHIGH Voltage Level
L X X X Load (P
n
x
Qn)
LeLOW Voltage Level
H L L H Count Up (Increment)
XeImmaterial
H L L L Count Down (Decrement)
H H X X No Change (Hold)
H X H X No Change (Hold)
State Diagram
’F169
TL/F/9488– 7
3
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