NSC 54F676SDMQB, 54F676FMQB, 54F676DMQB Datasheet

TL/F/9588

54F/74F676 16-Bit Serial/Parallel-In, Serial-Out Shift Register

December 1994

54F/74F676
16-Bit Serial/Parallel-In, Serial-Out Shift Register

General Description

The ’F676 contains 16 flip-flops with provision for synchro­nous parallel or serial entry and serial output. When the
Mode (M) input is HIGH, information present on the parallel
data (P

0–P15

) inputs is entered on the falling edge of the

Clock Pulse (CP

) input signal. When M is LOW, data is shift­ed out of the most significant bit position while information
present on the Serial (SI) input shifts into the least signifi­cant bit position. A HIGH signal on the Chip Select (CS

)

input prevents both parallel and serial operations.

Features

Y

16-bit parallel-to-serial conversion

Y

16-bit serial-in, serial-out

Y

Chip select control

Y

Slim 24 lead 300 mil package

Commercial Military

Package

Package Description

Number

74F676PC N24A 24-Lead (0.600×Wide) Molded Dual-In-Line

74F676SPC N24C 24-Lead (0.300×Wide) Molded Dual-In-Line

54F676DM (Note 2) J24A 24-Lead (0.600×Wide) Ceramic Dual-In-Line

54F676SDM (Note 2) J24F 24-Lead (0.300×Wide) Ceramic Dual-In-Line

74F676SC (Note 1) M24B 24-Lead (0.300×Wide) Molded Small Outline, JEDEC

54F676FM (Note 2) W24C 24-Lead Cerpack

54F676LM (Note 2) E28A 24-Lead Ceramic Leadless Chip Carrier, Type C

Note 1: Devices also available in 13×reel. Use suffixeSCX.

Note 2: Military grade device with environmental and burn-in processing. Use suffix

e

DMQB, FMQB and LMQB.

Connection Diagrams

Pin Assignment

for DIP, SOIC and Flatpak

TL/F/9588– 2

Pin Assignment

for LCC

TL/F/9588– 3

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

C

1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Logic Symbols

TL/F/9588– 1

IEEE/IEC

TL/F/9588– 4

Unit Loading/Fan Out

54F/74F

Pin Names Description

U.L. Input I

IH/IIL

HIGH/LOW Output IOH/I

OL

P0–P

15

Parallel Data Inputs 1.0/1.0 20 mA/b0.6 mA

CS

Chip Select Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA

CP

Clock Pulse Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA

M Mode Select Input 1.0/1.0 20 mA/

b

0.6 mA
SI Serial Data Input 1.0/1.0 20 mA/b0.6 mA
SO Serial Output 50/33.3

b

1 mA/20 mA

Functional Description

The 16-bit shift register operates in one of three modes, as
indicated in the Shift Register Operations Table.

HOLDÐa HIGH signal on the Chip Select (CS

) input pre-

vents clocking, and data is stored in the sixteen registers.

Shift/Serial LoadÐdata present on the SI pin shifts into
the register on the falling edge of CP

. Data enters the Q

0

position and shifts toward Q15on successive clocks, finally
appearing on the SO pin.

Parallel LoadÐdata present on P

0–P15

are entered into

the register on the falling edge of CP

. The SO output repre-

sents the Q

15

register output.

To prevent false clocking, CP must be LOW during a LOW­to-HIGH transition of CS

.

Shift Register Operations Table

Control Input

Operating Mode

CS MCP

H X X Hold
LLKShift/Serial Load
LHKParallel Load

HeHIGH Voltage Level
L

e

LOW Voltage Level

X

e

Immaterial

K

e

HIGH-to-LOW Transition

Block Diagram

TL/F/9588– 5

2

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Storage Temperature

b

65§Ctoa150§C

Ambient Temperature under Bias

b

55§Ctoa125§C

Junction Temperature under Bias

b

55§Ctoa175§C

Plastic

b

55§Ctoa150§C

V

CC

Pin Potential to

Ground Pin

b

0.5V toa7.0V

Input Voltage (Note 2)

b

0.5V toa7.0V

Input Current (Note 2)

b

30 mA toa5.0 mA

Voltage Applied to Output

in HIGH State (with V

CC

e

0V)

Standard Output

b

0.5V to V

CC

TRI-STATEÉOutput

b

0.5V toa5.5V

Current Applied to Output

in LOW State (Max) twice the rated I

OL

(mA)

Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.

Note 2: Either voltage limit or current limit is sufficient to protect inputs.

Recommended Operating
Conditions

Free Air Ambient Temperature

Military

b

55§Ctoa125§C

Commercial 0

§

Ctoa70§C

Supply Voltage

Military

a

4.5V toa5.5V

Commercial

a

4.5V toa5.5V

DC Electrical Characteristics

Symbol Parameter

54F/74F

Units V

CC

Conditions

Min Typ Max

V

IH

Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

V

IL

Input LOW Voltage 0.8 V Recognized as a LOW Signal

V

CD

Input Clamp Diode Voltage

b

1.2 V Min I

IN

eb

18 mA

V

OH

Output HIGH 54F 10% V

CC

2.5 I

OH

eb

1mA

Voltage 74F 10% V

CC

2.5 V Min I

OH

eb

1mA

74F 5% V

CC

2.7 I

OH

eb

1mA

V

OL

Output LOW 54F 10% V

CC

0.5
V Min

I

OL

e

20 mA

Voltage 74F 10% V

CC

0.5 I

OL

e

20 mA

I

IH

Input HIGH 54F 20.0

mA Max

V

IN

e

2.7V

Current 74F 5.0

I

BVI

Input HIGH Current 54F 100

mA Max

V

IN

e

7.0V

Breakdown Test 74F 7.0

I

CEX

Output HIGH 54F 250

mA Max

V

OUT

e

V

CC

Leakage Current 74F 50

V

ID

Input Leakage

74F 4.75 V 0.0

I

ID

e

1.9 mA,

Test All Other Pins Grounded

I

OD

Output Leakage

74F 3.75 mA 0.0

V

IOD

e

150 mV,

Circuit Current All Other Pins Grounded

I

IL

Input LOW Current

b

0.6 mA Max V

IN

e

0.5V

I

OS

Output Short-Circuit Current

b

60

b

150 mA Max V

OUT

e

0V

I

CC

Power Supply Current 72 mA Max

3