NSC 54F544SDMQB, 54F544LMQB Datasheet
54F/74F544
Octal Registered Transceiver
54F/74F544 Octal Registered Transceiver
December 1994
General Description
The ’F544 octal transceiver contains two sets of D-type
latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are
provided for each register to permit independent control of
inputting and outputting in either direction of data flow. The
A outputs are guaranteed to sink 24 mA (20 mA Mil) while
the B outputs are rated for 64 mA (48 mA Mil). The ’F544
Features
Y
8-bit octal transceiver
Y
Back-to-back registers for storage
Y
Separate controls for data flow in each direction
Y
A outputs sink 24 mA (20 mA Mil), B outputs sink
64 mA (48 mA Mil)
Y
300 mil slim PDIP
inverts data in both directions.
Commercial Military
Package
Number
Package Description
74F544SPC N24C 24-Lead (0.300×Wide) Molded Dual-In-Line
54F544DM (Note 2) J24A 24-Lead Ceramic Dual-In-Line
54F544SDM (Note 2) J24F 24-Lead (0.300×Wide) Ceramic Dual-In-Line
74F544SC (Note 1) M24B 24-Lead (0.300×Wide) Molded Small Outline, JEDEC
74F544MSA (Note 1) MSA24 24-Lead Molded Shrink Small Outline, EIAJ, Type II
54F544FM (Note 2) W24C 24-Lead Cerpack
54F544LM (Note 2) E28A 24-Lead Ceramic Leadless Chip Carrier, Type C
Note 1: Devices also available in 13×reel. Use suffixeSCX and MSAX.
Note 2: Military grade device with environmental and burn-in processing. Use suffix
e
DMQB, FMQB and LMQB
Logic Symbols
IEEE/IEC
TL/F/9555– 2
TL/F/9555– 1
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.
TL/F/9555
Connection Diagrams
Pin Assignment for
DIP, SOIC and Flatpak
TL/F/9555– 3
Unit Loading/Fan Out
54F/74F
Pin Names Description
OEAB A-to-B Output Enable Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA
OEBA
CEAB
B-to-A Output Enable Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA
A-to-B Enable Input (Active LOW) 1.0/2.0 20 mA/b1.2 mA
CEBA B-to-A Enable Input (Active LOW) 1.0/2.0 20 m A/b1.2 mA
LEAB
A-to-B Latch Enable Input (Active LOW) 1.0/1.0 20 m A/b0.6 mA
LEBA B-to-A Latch Enable Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA
A
B
0–A7
0–B7
A-to-B Data Inputs or 3.5/1.083 70 mA/b650 mA
B-to-A TRI-STATE Outputs 150/40(33.3)
B-to-A Data Inputs or 3.5/1.083 70 mA/b650 mA
A-to-B TRI-STATE Outputs 600/106.6(80)
U.L. Input I
HIGH/LOW Output IOH/I
b
3 mA/24 mA (20 mA)
b
12 mA/64 mA (48 mA)
IH/IIL
Pin Assignment
for LCC
TL/F/9555– 4
OL
Functional Description
The ’F544 contains two sets of eight D-type latches, with
separate input and output controls for each set. For data
flow from A to B, for example, the A-to-B Enable (CEAB
input must be LOW in order to enter data from A
take data from B
Table. With CEAB
Enable (LEAB
, as indicated in the Data I/O Control
0–B7
LOW, a LOW signal on the A-to-B Latch
) input makes the A-to-B latches transparent;
a subsequent LOW-to-HIGH transition of the LEAB
puts the A latches in the storage mode and their outputs no
longer change with the A inputs. With CEAB
LOW, the TRI-STATE
B output buffers are active and re-
É
flect the data present at the output of the A latches. Control
of data flow from B to A is similar, but using the CEBA
LEBA
and OEBA inputs.
0–A7
signal
and OEAB both
Data I/O Control Table
)
or
Inputs
CEAB LEAB OEAB
Latch Status Output Buffers
H X X Latched High Z
X H X Latched Ð
L L X Transparent Ð
X X H Ð High Z
L X L Ð Driving
HeHIGH Voltage Level
e
L
,
LOW Voltage Level
e
X
Immaterial
A-to-B data flow shown; B-to-A flow control is the same,
except using CEBA
, LEBA and OEBA
2
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
TL/F/9555– 5
3
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