NSC 54F413MW8, 54F413DMQB Datasheet
TL/F/9541
54F/74F413 64 x 4 First-In First-Out Buffer Memory with Parallel I/O
January 1995
54F/74F413
64 x 4 First-In First-Out Buffer Memory with Parallel I/O
General Description
The ’F413 is an expandable fall-through type high-speed
First-In First-Out (FIFO) buffer memory organized as 64
words by four bits. The 4-bit input and output registers record and transmit, respectively, asynchronous data in parallel
form. Control pins on the input and output allow for handshaking and expansion. The 4-bit wide, 62-bit deep fallthrough stack has self-contained control logic.
Features
Y
Separate input and output clocks
Y
Parallel input and output
Y
Expandable without external logic
Y
15 MHz data rate
Y
Supply current 160 mA max
Y
Available in SOIC, (300 mil only)
Commercial Military
Package
Package Description
Number
74F413PC N16E 16-Lead (0.300×Wide) Molded Dual-In-Line
54F413DM (Note 1) J16A 16-Lead Ceramic Dual-In-Line
Note 1: Military grade device with environmental and burn-in processing. Use suffixeDMQB.
Logic Symbol
TL/F/9541– 1
Connection Diagram
Pin Assignment
for DIP
TL/F/9541– 2
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
Unit Loading/Fan Out
54F/74F
Pin Names Description
U.L. Input I
IH/IIL
HIGH/LOW Output IOH/I
OL
D0–D
3
Data Inputs 1.0/0.667 20 mA/b0.4 mA
O
0–O3
Data Outputs 50/13.3
b
1 mA/8 mA
IR Input Ready 1.0/0.667 20 mA/
b
0.4 mA
SI Shift In 1.0/0.667 20 mA/b0.4 mA
SO Shift Out 1.0/0.667 20 mA/
b
0.4 mA
OR Output Ready 1.0/0.667 20 mA/b0.4 mA
MR
Master Reset 1.0/0.667 20 mA/b0.4 mA
Functional Description
Data InputÐData is entered into the FIFO on D0–D3in-
puts. To enter data the Input Ready (IR) should be HIGH,
indicating that the first location is ready to accept data. Data
then present at the four data inputs is entered into the first
location when the Shift In (SI) is brought HIGH. An SI HIGH
signal causes the IR to go LOW. Data remains at the first
location until SI is brought LOW. When SI is brought LOW
and the FIFO is not full, IR will go HIGH, indicating that more
room is available. Simultaneously, data will propagate to the
second location and continue shifting until it reaches the
output stage or a full location. If the memory is full, IR will
remain LOW.
Data TransferÐOnce data is entered into the second cell,
the transfer of any full cell to the adjacent (downstream)
empty cell is automatic, activated by an on-chip control.
Thus data will stack up at the end of the device while empty
locations will ‘‘bubble’’ to the front. The t
PT
parameter defines the time required for the first data to travel from input
to the output of a previously empty device.
Data OutputÐData is read from the O
0–O3
outputs. When
data is shifted to the output stage, Output Ready (OR) goes
HIGH, indicating the presence of valid data. When the OR is
HIGH, data may be shifted out by bringing the Shift Out (SO)
HIGH. A HIGH signal at SO causes the OR to go LOW. Valid
data is maintained while the SO is HIGH. When SO is
brought LOW, the upstream data, provided that stage has
valid data, is shifted to the output stage. When new valid
data is shifted to the output stage, OR goes HIGH. If the
FIFO is emptied, OR stays LOW, and O
0–O3
remains as
before, i.e., data does not change if FIFO is empty.
Input Ready and Output Ready may also be used as
status signals indicating that the FIFO is completely full (Input Ready stays LOW for at least t
PT
) or completely empty
(Output Ready stays LOW for at least t
PT
).
Block Diagram
TL/F/9541– 4
2
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