NSC 54F410DMQB Datasheet

TL/F/9538

54F/74F410 Register StackÐ16 x 4 RAM TRI-STATE Output Register

August 1995

54F/74F410 Register StackÐ16x4RAM
TRI-STATE

É

Output Register

General Description

The ’F410 is a register-oriented high-speed 64-bit Read/
Write Memory organized as 16-words by 4-bits. An edge­triggered 4-bit output register allows new input data to be
written while previous data is held. TRI-STATE outputs are
provided for maximum versatility. The ’F410 is fully compati­ble with all TTL families.

Features

Y

Edge-triggered output register

Y

Typical access time of 35 ns

Y

TRI-STATE outputs

Y

Optimized for register stack operation

Y

18-pin package

Y

9410 replacement

Commercial Military

Package

Package Description

Number

74F410PC N18A 18-Lead (0.300×Wide) Molded Dual-In-Line

54F410DM (Note 1) J18A 18-Lead Ceramic Dual-In-Line

74F410SC M20B 20-Lead (0.300×Wide) Molded Small Outline, JEDEC

54F410LM W20A 20-Lead Cerpak

Note 1: Military grade device with environmental and burn-in processing. Use suffixeDMQB, LMQB

Logic Symbol

TL/F/9538– 3

Connection Diagrams

Pin Assignment

for DIP and SOIC

TL/F/9538– 1

Pin Assignment

for LCC

TL/F/9538– 2

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

C

1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Unit Loading/Fan Out

54F/74F

Pin Names Description

U.L. Input I

IH/IIL

HIGH/LOW Output IOH/I

OL

A0–A

3

Address Inputs 1.0/1.0 20 mA/b0.6 mA

D

0–D3

Data Inputs 1.0/1.0 20 mA/b0.6 mA

CS

Chip Select Input (Active LOW) 1.0/2.0 20 mA/b1.2 mA
OE Output Enable Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA
WE

Write Enable Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA
CP Clock Input (Outputs Change on

LOW-to-HIGH Transition) 1.0/2.0 20 mA/

b

1.2 mA

Q

0–Q3

TRI-STATE Outputs 150/40 (33.3)b3 mA/24 mA (20 mA)

Functional Description

Write OperationÐWhen the three control inputs, Write En-

able (WE

), Chip Select (CS), and Clock (CP), are LOW the

information on the data inputs (D

0–D3

) is written into the

memory location selected by the address inputs (A

0–A3

). If

the input data changes while WE

,CS, and CP are LOW, the
contents of the selected memory location follow these
changes, provided setup and hold time criteria are met.

Read OperationÐWhenever CS

is LOW and CP goes from
LOW-to-HIGH, the contents of the memory location select­ed by the address inputs (A

0–A3

) are edge-triggered into

the Output Register.

The (OE

) input controls the output buffers. When OE is

HIGH the four outputs (Q

0–Q3

) are in a high impedance or

OFF state; when OE

is LOW, the outputs are determined by

the state of the Output Register.

Block Diagram

TL/F/9538– 4

2

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Storage Temperature

b

65§Ctoa150§C

Ambient Temperature under Bias

b

55§Ctoa125§C

Junction Temperature under Bias

b

55§Ctoa175§C

Plastic

b

55§Ctoa150§C

V

CC

Pin Potential to

Ground Pin

b

0.5V toa7.0V

Input Voltage (Note 2)

b

0.5V toa7.0V

Input Current (Note 2)

b

30 mA toa5.0 mA

Voltage Applied to Output

in HIGH State (with V

CC

e

0V)

Standard Output

b

0.5V to V

CC

TRI-STATE Output

b

0.5V toa5.5V

Current Applied to Output

in LOW State (Max) twice the rated I

OL

(mA)

Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.

Note 2: Either voltage limit or current limit is sufficient to protect inputs.

Recommended Operating
Conditions

Free Air Ambient Temperature

Military

b

55§Ctoa125§C

Commercial 0

§

Ctoa70§C

Supply Voltage

Military

a

4.5V toa5.5V

Commercial

a

4.5V toa5.5V

DC Electrical Characteristics

Symbol Parameter

54F/74F

Units V

CC

Conditions

Min Typ Max

V

IH

Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

V

IL

Input LOW Voltage 0.8 V Recognized as a LOW Signal

V

CD

Input Clamp Diode Voltage

b

1.2 V Min I

IN

eb

18 mA

V

OH

Output HIGH 54F 10% V

CC

2.5 I

OH

eb

1mA

Voltage 54F 10% V

CC

2.4 I

OH

eb

3mA

74F 10% V

CC

2.5 V Min I

OH

eb

1mA

74F 10% V

CC

2.4 I

OH

eb

3mA

74F 5% V

CC

2.7 I

OH

eb

3mA

V

OL

Output LOW 54F 10% V

CC

0.5
V Min

I

OL

e

20 mA

Voltage 74F 10% V

CC

0.5 I

OL

e

24 mA

I

IH

Input HIGH 54F 20.0

mA Max V

IN

e

2.7V

Current 74F 5.0

I

BVI

Input HIGH Current 54F 100

mA Max V

IN

e

7.0V

Breakdown Test 74F 7.0

I

CEX

Output HIGH 54F 250

mA Max V

OUT

e

V

CC

Leakage Current 74F 50

V

ID

Input Leakage

74F 4.75 V 0.0

I

ID

e

1.9 mA

Test All Other Pins Grounded

I

OD

Output Leakage

74F 3.75 mA 0.0

V

IOD

e

150 mV

Circuit Current All Other Pins Grounded

I

IL

Input LOW Current

b

0.6
mA Max

V

IN

e

0.5V (An,Dn,OE,WE)

b

1.2 V

IN

e

0.5V (CS, CP)

I

OZH

Output Leakage Current 50 mA Max V

OUT

e

2.7V

I

OZL

Output Leakage Current

b

50 mA Max V

OUT

e

0.5V

I

OS

Output Short-Circuit Current

b

60

b

150 mA Max V

OUT

e

0V

I

ZZ

Bus Drainage Test 500 mA 0.0V V

OUT

e

5.25V

3