TL/F/9527
54F/74F379 Quad Parallel Register with Enable
August 1995
54F/74F379
Quad Parallel Register with Enable
General Description
The ’F379 is a 4-bit register with buffered common Enable.
This device is similar to the ’F175 but features the common
Enable rather than common Master Reset.
Features
Y
Edge triggered D-type inputs
Y
Buffered positive edge-triggered clock
Y
Buffered common enable input
Y
True and complement outputs
Y
Guaranteed 4000V minimum ESD protection
Commercial Military
Package
Package Description
Number
74F379PC N16E 16-Lead (0.300×Wide) Molded Dual-In-Line
54F379DM (QB) J16A 16-Lead Ceramic Dual-In-Line
74F379SC (Note 1) M16A 16-Lead (0.300×Wide) Molded Small Outline, JEDEC
74F379SJ (Note 1) M16D 16-Lead (0.300×Wide) Molded Small Outline, EIAJ
54F379FM (QB) W16A 16-Lead Cerpack
54F379LM (QB) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C
Note 1: Devices also available in 13×reel. Use suffixeSCX and SJX.
Logic Symbols
IEEE/IEC
TL/F/9527– 5
Connection Diagrams
Pin Assignment
DIP, SOIC and Flatpak
TL/F/9527– 1
Pin Assignment
for LCC
TL/F/9527– 2
TL/F/9527– 3
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.
Unit Loading/Fan Out
54F/74F
Pin Names Description
U.L. Input I
IH/IIL
HIGH/LOW Output IOH/I
OL
E Enable Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA
D
0–D3
Data Inputs 1.0/1.0 20 mA/b0.6 mA
CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 mA/
b
0.6 mA
Q0–Q3Flip-Flop Outputs 50/33.3b1 mA/20 mA
Q
0–Q3
Complement Outputs 50/33.3b1 mA/20 mA
Functional Description
The ’F379 consists of four edge-triggered D-Type flip-flops
with individual D inputs and Q and Q
outputs. The Clock
(CP) and Enable (E
) inputs are common to all flip-flops.
When the E
is input HIGH, the register will retain the present
data independent of the CP input. The D
n
and E inputs can
change when the clock is in either state, provided that the
recommended setup and hold times are observed.
Truth Table
Inputs Outputs
E CP D
n
Q
n
Q
n
H L XNCNC
LLHH L
LLLLH
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
L
e
LOW-to-HIGH Transition
NC
e
No Change
Logic Diagram
TL/F/9527– 4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature
b
65§Ctoa150§C
Ambient Temperature under Bias
b
55§Ctoa125§C
Junction Temperature under Bias
b
55§Ctoa175§C
Plastic
b
55§Ctoa150§C
V
CC
Pin Potential to
Ground Pin
b
0.5V toa7.0V
Input Voltage (Note 2)
b
0.5V toa7.0V
Input Current (Note 2)
b
30 mA toa5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
e
0V)
Standard Output
b
0.5V to V
CC
TRI-STATEÉOutput
b
0.5V toa5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
(mA)
ESD Last Passing Voltge (Min) 4000V
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
b
55§Ctoa125§C
Commercial 0
§
Ctoa70§C
Supply Voltage
Military
a
4.5V toa5.5V
Commercial
a
4.5V toa5.5V
DC Electrical Characteristics
Symbol Parameter
54F/74F
Units V
CC
Conditions
Min Typ Max
V
IH
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage
b
1.2 V Min I
IN
eb
18 mA
V
OH
Output HIGH 54F 10% V
CC
2.5 I
OH
eb
1mA
Voltage 74F 10% V
CC
2.5 V Min I
OH
eb
1mA
74F 5% V
CC
2.7 I
OH
eb
1mA
V
OL
Output LOW 54F 10% V
CC
0.5
V Min
I
OL
e
20 mA
Voltage 74F 10% V
CC
0.5 I
OL
e
20 mA
I
IH
Input HIGH 54F 20.0
mA Max
V
IN
e
2.7V
Current 74F 5.0
I
BVI
Input HIGH Current 54F 100
mA Max
V
IN
e
7.0V
Breakdown Test 74F 7.0
I
CEX
Output HIGH 54F 250
mA Max
V
OUT
e
V
CC
Leakage Current 74F 50
V
ID
Input Leakage
74F 4.75 V 0.0
I
ID
e
1.9 mA
Test All Other Pins Grounded
I
OD
Output Leakage
74F 3.75 mA 0.0
V
IOD
e
150 mV
Circuit Current All Other Pins Grounded
I
IL
Input LOW Current
b
0.6 mA Max V
IN
e
0.5V
I
OS
Output Short-Circuit Current
b
60
b
150 mA Max V
OUT
e
0V
I
CCL
Power Supply Current 28 40 mA Max V
O
e
LOW
3
AC Electrical Characteristics
74F 54F 74F
T
A
ea
25§C
T
A,VCC
e
Mil TA,V
CC
e
Com
Symbol Parameter V
CC
ea
5.0V
C
L
e
50 pF C
L
e
50 pF
Units
C
L
e
50 pF
Min Typ Max Min Max Min Max
f
max
Maximum Clock Frequency 100 140 75 100 MHz
t
PLH
Propagation Delay 3.5 5.0 6.5 3.0 8.5 3.5 7.5
ns
t
PHL
CP to Qn,Q
n
5.0 6.5 8.5 4.0 10.0 5.0 9.5
AC Operating Requirements
74F 54F 74F
Symbol Parameter
T
A
ea
25§C
T
A,VCC
e
Mil TA,V
CC
e
Com Units
V
CC
ea
5.0V
Min Max Min Max Min Max
ts(H) Setup Time, HIGH or LOW 3.0 4.0 3.0
t
s
(L) Dnto CP 3.0 4.0 3.0
ns
th(H) Hold Time, HIGH or LOW 1.0 2.0 1.0
t
h
(L) Dnto CP 1.0 2.0 1.0
ts(H) Setup Time, HIGH or LOW 6.0 8.0 6.0
t
s
(L) E to CP 6.0 8.0 6.0
ns
th(H) Hold Time, HIGH or LOW 0 0 0
t
h
(L) E to CP 0 0 0
tw(H) CP Pulse Width 4.0 5.0 4.0
ns
t
w
(L) HIGH or LOW 5.0 7.0 5.0
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74F 379 S C X
Temperature Range Family Special Variations
74F
e
Commercial QBeMilitary grade device with
54F
e
Military environmental and burn-in
processing
Device Type
X
e
Devices shipped in 13×reel
Package Code
Temperature Range
P
e
Plastic DIP
C
e
Commercial (0§Ctoa70§C)
D
e
Ceramic DIP
M
e
Military (b55§Ctoa125§C)
F
e
Flatpak
L
e
Leadless Chip Carrier (LCC)
S
e
Small Outline SOIC JEDEC
SJ
e
Small Outline SOIC EIAJ
4
Physical Dimensions inches (millimeters)
20-Lead Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
16-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J16A
5
Physical Dimensions inches (millimeters) (Continued)
16-Lead (0.150×Wide) Molded Small Outline Integrated Circuit (S)
NS Package Number M16A
16-Lead (0.300×Wide) Molded Small Outline Package, EIAJ (SJ)
NS Package Number M16D
6
Physical Dimensions inches (millimeters) (Continued)
16-Lead (0.300×Wide) Molded Dual-In-Line Package (P)
NS Package Number N16E
7
54F/74F379 Quad Parallel Register with Enable
Physical Dimensions inches (millimeters) (Continued)
16-Lead Ceramic Flatpak (F)
NS Package Number W16A
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into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
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