NSC 54F299LMQB, 54F299DMQB Datasheet
TL/F/9515
54F/74F299 Octal Universal Shift/Storage Register with Common Parallel I/O Pins
May 1995
54F/74F299 Octal Universal Shift/Storage Register
with Common Parallel I/O Pins
General Description
The ’F299 is an 8-bit universal shift/storage register with
TRI-STATE
É
outputs. Four modes of operation are possible: hold (store), shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Additional outputs,
Q
0–Q7
, are provided to allow easy serial cascading. A sep-
arate active LOW Master Reset is used to reset the register.
Features
Y
Common parallel I/O for reduced pin count
Y
Additional serial inputs and outputs for expansion
Y
Four operating modes: shift left, shift right, load and
store
Y
TRI-STATE outputs for bus-oriented applications
Y
Guaranteed 4000V minimum ESD protection
Commercial Military
Package
Package Description
Number
74F299PC N20A 20-Lead (0.300×Wide) Molded Dual-In-Line
54F299DM (Note 2) J20A 20-Lead Ceramic Dual-In-Line
74F299SC (Note 1) M20B 20-Lead (0.300×Wide) Molded Small Outline, JEDEC
74F299SJ (Note 1) M20D 20-Lead (0.300×Wide) Molded Small Outline, EIAJ
54F299FM (Note 2) W20A 20-Lead Cerpack
54F299LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C
Note 1: Devices also available in 13×reel. Use suffixeSCX and SJX.
Note 2: Military grade device with environmental and burn-in processing. Use suffix
e
DMQB, FMQB and LMQB.
Logic Symbols
TL/F/9515– 1
IEEE/IEC
TL/F/9515– 4
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.
Connection Diagrams
Pin Assignment
for DIP, SOIC and Flatpak
TL/F/9515– 2
Pin Assignment
for LCC
TL/F/9515– 3
Unit Loading/Fan Out
54F/74F
Pin Names Description
U.L. Input I
IH/IIL
HIGH/LOW Output IOH/I
OL
CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 mA/b0.6 mA
DS
0
Serial Data Input for Right Shift 1.0/1.0 20 mA/b0.6 mA
DS
7
Serial Data Input for Left Shift 1.0/1.0 20 mA/b0.6 mA
S0,S
1
Mode Select Inputs 1.0/2.0 20 mA/b1.2 mA
MR
Asynchronous Master Reset Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA
OE1,OE2TRI-STATE Output Enable Inputs (Active LOW) 1.0/1.0 20 mA/b0.6 mA
I/O
0
–I/O7Parallel Data Inputs or 3.5/1.083 70 mA/b0.65 mA
TRI-STATE Parallel Outputs 150/40(33.3)
b
3 mA/24 mA (20 mA)
Q
0,Q7
Serial Outputs 50/33.3
b
1 mA/20 mA
Functional Description
The ’F299 contains eight edge-triggered D-type flip-flops
and the interstage logic necessary to perform synchronous
shift left, shift right, parallel load and hold operations. The
type of operation is determined by S
0
and S1, as shown in
the Mode Select Table. All flip-flop outputs are brought out
through TRI-STATE buffers to separate I/O pins that also
serve as data inputs in the parallel load mode. Q
0
and Q
7
are also brought out on other pins for expansion in serial
shifting of longer words.
A LOW signal on MR
overrides the Select and CP inputs
and resets the flip-flops. All other state changes are initiated
by the rising edge of the clock. Inputs can change when the
clock is in either state provided only that the recommended
setup and hold times, relative to the rising edge of CP, are
observed.
A HIGH signal on either OE
1
or OE2disables the TRISTATE buffers and puts the I/O pins in the high impedance
state. In this condition the shift, hold, load and reset operations can still occur. The TRI-STATE outputs are also disabled by HIGH signals on both S
0
and S1in preparation for
a parallel load operation.
Mode Select Table
Inputs
Response
MR S1S0CP
L X X X Asynchronous Reset; Q0–Q
7
e
LOW
HHHLParallel Load; I/O
n
x
Q
n
HLHLShift Right; DS
0
x
Q0,Q
0
x
Q1, etc.
HHLLShift Left; DS
7
x
Q7,Q
7
x
Q6, etc.
H L L X Hold
HeHIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
L
e
LOW-to-HIGH Clock Transition
2
Logic Diagram
TL/F/9515– 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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