NSC 54F283LMQB, 54F283FMQB, 54F283DMQB, 54F283DM Datasheet

TL/F/9513

54F/74F283 4-Bit Binary Full Adder with Fast Carry

November 1994

54F/74F283
4-Bit Binary Full Adder with Fast Carry

General Description

The ’F283 high-speed 4-bit binary full adder with internal
carry lookahead accepts two 4-bit binary words (A

0–A3

,

B

0–B3

) and a Carry input (C0). It generates the binary Sum

outputs (S

0–S3

) and the Carry output (C4) from the most
significant bit. The ’F283 will operate with either active
HIGH or active LOW operands (positive or negative logic).

Features

Y

Guaranteed 4000V minimum ESD protection

Commercial Military

Package

Package Description

Number

74F283PC N16E 16-Lead (0.300×Wide) Molded Dual-In-Line

54F283DM (Note 2) J16A 16-Lead Ceramic Dual-In-Line

74F283SC (Note 1) M16A 16-Lead (0.150×Wide) Molded Small Outline, JEDEC

74F283SJ (Note 1) M16D 16-Lead (0.300×Wide) Molded Small Outline, EIAJ

54F283FM (Note 2) W16A 16-Lead Cerpack

54F283LL (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C

Note 1: Devices also available in 13×reel. Use suffixeSCX and SJX.

Note 2: Military grade device with environmental and burn-in processing. Use suffix

e

DMQB, FMQB and LMQB.

Logic Symbols Connection Diagrams

TL/F/9513– 1

IEEE/IEC

TL/F/9513– 4

Pin Assignment

for DIP, SOIC and Flatpak

TL/F/9513– 2

Pin Assignment

for LCC

TL/F/9513– 3

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

C

1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Unit Loading/Fan Out

54F/74F

Pin Names Description

U.L. Input I

IH/IIL

HIGH/LOW Output IOH/I

OL

A0–A

3

A Operand Inputs 1.0/2.0 20 mA/b1.2 mA

B

0–B3

B Operand Inputs 1.0/2.0 20 mA/b1.2 mA

C

0

Carry Input 1.0/1.0 20 m A/b0.6 mA

S0–S

3

Sum Outputs 50/33.3

b

1 mA/20 mA

C

4

Carry Output 50/33.3

b

1 mA/20 mA

Functional Description

The ’F283 adds two 4-bit binary words (A plus B) plus the
incoming Carry (C

0

). The binary sum appears on the Sum

(S

0–S3

) and outgoing carry (C4) outputs. The binary weight
of the various inputs and outputs is indicated by the sub­script numbers, representing powers of two.

2

0

(A

0

a

B

0

a

C0)a21(A

1

a

B1)

a

22(A

2

a

B2)a23(A

3

a

B3)

e

S

0

a

2S

1

a

4S

2

a

8S

3

a

16C

4

Where (a)eplus

Interchanging inputs of equal weight does not affect the op­eration. Thus C

0,A0,B0

can be arbitrarily assigned to pins
5, 6 and 7 for DIPS, and 7, 8 and 9 for chip carrier packages.
Due to the symmetry of the binary add function, the ’F283
can be used either with all inputs and outputs active HIGH
(positive logic) or with all inputs and outputs active LOW
(negative logic). See

Figure 1

. Note that if C0is not used it
must be tied LOW for active HIGH logic or tied HIGH for
active LOW logic.

Due to pin limitations, the intermediate carries of the ’F283
are not brought out for use as inputs or outputs. However,

other means can be used to effectively insert a carry into, or
bring a carry out from, an intermediate stage.

Figure 2

shows how to make a 3-bit adder. Tying the operand inputs
of the fourth adder (A

3,B3

) LOW makes S3dependent only
on, and equal to, the carry from the third adder. Using some­what the same principle,

Figure 3

shows a way of dividing
the ’F283 into a 2-bit and a 1-bit adder. The third stage
adder (A

2,B2,S2

) is used merely as a means of getting a

carry (C

10

) signal into the fourth stage (via A2and B2) and

bringing out the carry from the second stage on S

2

. Note

that as long as A

2

and B2are the same, whether HIGH or

LOW, they do not influence S

2

. Similarly, when A2and B

2

are the same the carry into the third stage does not influ­ence the carry out of the third stage.

Figure 4

shows a meth­od of implementing a 5-input encoder, where the inputs are
equally weighted. The outputs S

0,S1

and S2present a bina-

ry number equal to the number of inputs I

1–I5

that are true.

Figure 5

shows one method of implementing a 5-input ma-

jority gate. When three or more of the inputs I

1–I5

are true,

the output M

5

is true.

C0A0A1A2A3B0B1B2B3S0S1S2S3C

4

Logic Levels L LHLHHLLHHHLLH

Active HIGH 0 0101100111001
Active LOW 1 1010011000110

Active HIGH: 0a10a9e3a16 Active LOW: 1a5a6e12a0

FIGURE 1. Active HIGH versus Active LOW Interpretation

2

Functional Description (Continued)

TL/F/9513– 5

FIGURE 2. 3-Bit Adder

TL/F/9513– 6

FIGURE 3. 2-Bit and 1-Bit Adders

TL/F/9513– 7

FIGURE 4. 5-Input Encoder

TL/F/9513– 8

FIGURE 5. 5-Input Majority Gate

3