Nokia 9500 Service Manual 06 ra2 BB

Nokia Customer Care

6 - Baseband Description

and T roubleshooting

Issue 1 09/04 COMPANY CONFIDENTIAL

RA-2/3 6 - Baseband Description and Troubleshooting Nokia Customer Care

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RA-2/3 6 - Baseband Description and Troubleshooting Nokia Customer Care

Table of Contents

Page No

Abbreviations ......................................................................................................5

Baseband Top-Level Description ......................................................................7

Operating conditions.......................................................................................... 8

Functional Description of CMT........................................................................ 10

Interfaces between CMT and APE................................................................... 11

Functional Description of APE ........................................................................12

Audio................................................................................................................ 12

Audio control signals........................................................................................ 13

Audio modes.................................................................................................... 13

Internal interfaces ............................................................................................ 14

External interfaces........................................................................................... 15

UI interfaces..................................................................................................... 15

Functional Description of WLAN..................................................................... 20

WLAN medium access controller..................................................................... 20

WLAN – OMAP host interface ......................................................................... 21

WLAN baseband processor............................................................................. 21

WLAN energy management............................................................................. 23

Energy Management.........................................................................................26

CMT EM........................................................................................................... 28

APE EM ........................................................................................................... 28

Battery.............................................................................................................. 29

Charging .......................................................................................................... 30

Backup battery and RTC.................................................................................. 30

Display and keypad illumination....................................................................... 30

Power up and system states............................................................................ 30

System Connector ............................................................................................ 32

Universal Serial Bus (USB).............................................................................. 33

Accessory Control Interface (ACI) ................................................................... 34

HookInt............................................................................................................. 34

After Sales Interface ......................................................................................... 35

User Interface .................................................................................................... 36

Component placement and FPWB outline of 1BV........................................... 37

Hinge connector............................................................................................... 38

PDA display ..................................................................................................... 40

CMT display..................................................................................................... 42

CMT keypad..................................................................................................... 43

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RA-2/3

Nokia Customer Care 6 - Baseband Description and Troubleshooting

Bluetooth.......................................................................................................... 46

Baseband Troubleshooting.............................................................................. 47

Top level flowchart........................................................................................... 48

UI failure troubleshooting................................................................................. 50

Phone is dead troubleshooting ........................................................................ 54

IR troubleshooting............................................................................................ 55

WLAN BB troubleshooting............................................................................... 56

Bluetooth troubleshooting................................................................................ 57

USB troubleshooting........................................................................................ 59

Flash faults....................................................................................................... 60

Camera module troubleshooting...................................................................... 61

Audio faults troubleshooting............................................................................. 63

MMC troubleshooting....................................................................................... 69

Accessory detection troubleshooting ............................................................... 70

Charging troubleshooting................................................................................. 71

CMT troubleshooting........................................................................................ 72

APE troubleshooting........................................................................................ 73

SIM card error.................................................................................................. 75

APE memory troubleshooting.......................................................................... 76

MDOC troubleshooting .................................................................................... 77

Appendix A: BB Troubleshooting Measurement Points by Troubleshooting Tree 78

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Abbreviations

ACI Accessory Interface APE Application Processor Engine ASIC Application Specific Integrated Circuit BB Baseband BT Bluetooth (Low range radio link standard) CCS Customer Care Solution CMT Cellular Mobile Telephone CSR Cambridge Silicon Radio DAC Digital to Analog Converter DC/DC Switched mode power supply DCT4.x Digital Core Technology, fourth.x generation DSP Digital Signal Processing EEPROM Electrically Erasable Programmable Read Only Memory EM Energy Management EMC Electro Magnetic Compatibility EMIFF External Memory Interface Fast EMIFS External Memory Interface Slow ESD Electro Static Discharge FBUS Serial bus FM Frequency Modulation GSM G lobal System for Mobile communications HSCSD High Speed Circuit Switched Data HW Hardware IC Integrated Circuit IMEI International Mobile Equipment Identity IO Input / Output JTAG Joint Test Action Group – a standard trace and debugging interface LDO Low Drop Out MBUS Serial bus

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RA-2/3

Nokia Customer Care 6 - Baseband Description and Troubleshooting

MCU MicroController Unit MMC Multi-Media Card NAND Flash memory cell type OMAP Open Multimedia Architecture Platform OSP Organic Solderable Preservative PA Power Amplifier PWB Printed Wiring Board (same than PCB) RF Radio Frequency RTC Real Time Clock SDRAM Synchronous Dynamic Random Access Memory SPR Standard Product Requirements SW SoftWare UEM Universal Energy Management Asic (DCT4 EM asic) UI User Interface UPP Universal Phone Processor ASIC (DCT4 processor asic) USB Universal Serial Bus WLAN Wireless LAN

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Baseband Top-Level Description

RA-2/3 HW is based on a platform with a WLAN subsystem. RA-2/3 HW architecture consists of:

• Two colour displays

• QWERTY keyboard

• Cover keyboard

• Engine PWB

There are three PWBs: main engine board, QWERTY PWB and lid fle x. Both displays and the cover keyboard are connected to the engine via the lid flex. The QWERTY keyboard is connected to the engine through a QWERTY controller. Camera is located directly on the engine PWB.

RA-2/3 engine PWB architecture consists of four main building blocks:

• Application Processor Engine (APE)

• Cellular Mobile Telephone (CMT)

• WLAN and

•CMT RF

The APE part is constructed using OMAP1510 processor with external SDRAM and NAND based flash memory as the core. Other major parts for APE are power supplies, UI interfaces, audio support, Bluetooth and camera.

The WLAN subsystem is connected to the OMAP1510 flash interface. WLAN baseband is based on T TNETW1100B Medium Access Controller / Baseband Processor IC. The 2.4GHz radio part is based on zero-IF transceiver and PA. Bluetooth and W LAN share the same antenna and cannot be active simultaneously.

APE and CMT parts are connected together by serial communication buses and by a few control lines. The APE part reset and power control comes from the CMT side. Audio control is mostly on the APE side. APE and CMT operate with no clear master-slave nomination.

The diagram below shows a high level block diagram of RA-2/3.

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RA-2/3

Nokia Customer Care 6 - Baseband Description and Troubleshooting

Figure 1:Simplified RA-2/3 block diagram

CMT

Batte ry

VBAT

Flash 32Mb

UEM

UPP8M

ARM7

Lead3

Regulators

CODEC

SIM I/F

LPRFUART

DSPSIO

Bluetooth

Han ds -fre e In

Han d s-fre e O ut

SIM

MDOC NAND 128MB

SDRAM 64MB

WLAN

Enable

NAND/ NOR IF

Adapter

DAC

APE

REGULATORS

I2C

McBSP1

GP IO I/F

UART2

McBSP2

MCSI2

McBSP3

MCSI1

Flash I/F

SDRAM I/F

Back cover

Hall sw

OMAP1510

ARM925T

LEAD3ph3

LCD I/F CLKM

ARMIO

Botto m C o n n e c to r

MIC ACI

IHF

Camera

USB

UART3 /

PWT/PWL

UART1

SD-MMC

uWire

ARMIO

Keyboard

12MHz

I2C

OUTL

OUTR USB

IrDA

MMC

CBA keys

Backlights Keylights

UEM control

COP8

Cover

keys &

PDA display

Lid Hall

Lid Flex

QWERTY

Cover

display

QWERTY PWB

PWRkey

■ Operating conditions

Absolute maximum ratings

Table 1: Absolute maximum ratings

Signal Note

Battery Vo ltage (Idle) -0.3V - 5.5V Battery Vo ltage (Call) Max 4.8V Charger Input Voltage -0.3V - 16V

Battery voltage maximum values are specified during active charging.

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DC characteristics

Table 2: Battery voltage range

Signal Min Nom Max Note

VBAT 3.1V 3.6V 4.2V (charging high limit voltage) 3.4V SW RF cut off

Battery maximum voltage is specified when charging switch is disconnected after/between charging pulses.

Temperature conditions

Full functionality is achieved in the ambient temperature range -15 oC to +55 oC. Reduced functionality between -25

The required storage temperature is -40

C to -10 oC and +55 oC to +70 oC.

C to +85 oC.

ESD immunity

SPR limits are 8kV for galvanic contact and 15kV for air discharge with normal and reversed polarity.

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RA-2/3

Nokia Customer Care 6 - Baseband Description and Troubleshooting

Functional Description of CMT

The CMT architecture of RA-2/3 is based on DCT4 Common Baseband. The main functionality of the CMT baseband is implemented into two ASICs: UPP (Universal Phone Processor) and UEM (Universal Energy Management).

32Mbit NOR flash is used to store the program code. For a simplified block diagram of the RA2/3 CMT baseband, see Figure 2, “Simplified CMT baseband block diagram” on page 11.

System clock for the CMT is derived from the RF circuits. For GSM it is 26 MHz. The low frequency sleep clock is generated in the UEM using an external 32.768 kHz crystal. The I/O voltage of the CMT baseband is 1.8V and the analog parts are powered from 2.8V power rails. The core voltage of UPP can be altered with SW depending on the prevailing processing power requirements.

UEM is a dual voltage circuit. The digital parts are running from the baseband supply (1.8V) and the analog parts are running from the analog supply (2.8V). So me blocks of UEM are also connected directly to the battery voltage (VBAT). UEM includes 6 linear LDO (low drop-out) regulator for the baseband and 7 regulators for the RF. It also includes 4 current sources for biasing purposes and internal usage.

Some parts of the SIM interface have been integrated into UEM. The SIM interface supports only 1.8V and 3V SIM cards. Data transmission betwe en the UEM and UPP is handled via two serial buses: DBUS for DSP and CBUS for MCU. There are also separate signals for PDM coded audio. Digital speech processing is handled by the DSP inside UPP and the audio codec is in UEM.

The analog interface between the baseband and the RF sections has been implemented into UEM. UEM provides A/D and D/A conversion of the in-phase and quadrature receive and transmit signal paths and supplies the analog TXC and AFC signals to RF section under the UPP DSP control. The digital RF-BB interface, consisting of a dedicated RFIC control bus and a group of GenIO pins, is located in the UPP.

The baseband side supports both internal and external microphone inputs and speaker outputs. Input and output signal source selection and gain control is performed in the UEM according to control messages from the UPP. Keypad tones, DTMF, and other audio tones are generated and encoded by the UPP and transmitted to UEM for decoding.

RA-2/3 has two galvanic serial control interfaces for CMT: FBUS and MBUS. Communication between the APE and CMT parts is handled through 2 serial buses: XBUS and

XABUS. XBUS is the main communication channel for general use, and XABUS is intended mainly for audio data transfer. Also the system reset (PURX) and SleepClk for APE are taken from the CMT side. The PURX is delayed approximately 130ms to fulfil OMAP1510 reset timing requirements. One of UEM’s IR level shifters is used for SleepClk level shifting both to APE and WLAN.

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Figure 2:Simplified CMT baseband block diagram

CMT - APE interface

Prod/AS

Test IF

FBUS

UEMKUPP 8M

UEM

MBUS

32kH

CHRG current sense

1.8V/3V

PWR on key

SIM

EAR

MIC

RF-BB

JTAG

RFConv

RFIC

Control

RFClk

XBUS XABUS

PUR delay

+ lvl shift

PURX

RFConvIF

Internal SIM IF

SleepClk

Audio IF

MBUS

FBUS

DBUS

CBUS

Zocus

BATT. IF CHRG. IF

Control

from APE

IHF

Memory

32Mb Flash

PWREn

Accessory

regulator

MIC+ACI

L+R

System Connector

XEAR

Audio

DAC

Audio

AMP

L+R

■ Interfaces between CMT and APE

XBUS

XBUS is the main communication interface between the CMT and APE parts of RA-2/3. This 6-pin interface is implemented using UART2 of OMAP1510 (APE), LPRFUART of UPP (CMT) and 2 general purpose I/O pins from both ASICs.

XABUS

XABUS is a synchronous serial interface which is used for uncompressed PCM audio data transfer between the DSPs of UPP (CMT) and OMAP1510 (APE). This interface utilises the DSPSIO of UPP and the MCSI_2 of OMAP1510. In addition to these one UPP GenIO and two dedicated pins of OMAP1510 are needed for XABUS clock generation and control.

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RA-2/3

Nokia Customer Care 6 - Baseband Description and Troubleshooting

Functional Description of APE

APE term includes not only the processor itself but also the peripherals around it, clocking, resetting and power management for these parts.

APE is based around OMAP1510 (Open Multimedia Application Platform) processor. Peripherals attached to OMAP1510 include:

• Audio DAC

• Camera

• Bluetooth

• Cover display

•PDA display

• Memory card

•IrDA

• Cover keypad & CBA buttons

• QWERTY controller

• External SDRAM

• Flash memories

•WLAN

APE acts as a system slave compared to the CMT side. CMT holds the master reset and power management logic. APE and CMT are connected through a serial link called XBUS.

■ Audio

Figure 3:RA-2/3 Audio architecture

DSP_SIO

XABUS

PCM

CSR

XBUS

control

UPP

UART2

MCSI2

MCSI1

UART1

Ringtones

Streaming

engine

OMAP1510

MP3 decoder

Entertainment

effects

McBSP1

I2CI/F

McBSP2

UEM

L P

Stereo or mono

digital audi o

MIC1 MIC2 MIC3

EARP/EARN

HF/HFCM

XEAR

I2S, Digital Audio;

I2C

Control

Mic_In

TLV320AIC23B

R_Line_In

L_Line_In

R_HP_Out

L_HP_Out

R_Out

~10dB

Attenuator

L_Out

McBSP Contro l , S PI Mode;

IHFIn

Phone HS

RIn

Lin

LM4855

IHFOut

ROut

LOut

Tomahawk

As RA-2/3 is based on a dual-processor architecture, audios are also divided into APE and CMT parts. Audio control is mostly on the APE side. Phone audio is routed from the CMT side

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to APE in analog form. On the CMT side, audio HW is integrated into the UEM ASIC. On the APE side, the most important parts are OMAP1510, audio DAC and audio power amplifier.

The stereo output of this amplifier is designed for use with the ext ended Pop-port

connector.

It also has a differential mono output for driving the handsfree speaker. The battery voltage (VBAT) is used directly as a supply voltage for the audio amplifier. The type of DAC used is TLV320AIC23B and the supply voltage for this is coming from V28.

■ Audio control signals

Audio DAC is controlled via I2C bus by OMAP1510. Digital audio data from OMAP1510 to DAC is coming via MCBSP1.

The audio amplifier is controlled through a 3-wire SPI bus (MCBSP2 of OMAP1510). Audio mode of the amplifier and gain values are controlled via SPI bus.

The HEADINT signal is needed for recognising the external device (e.g. headset) connected to system. The recognition is based on the ACI-pin of the system connector, which is shorted to ground inside the external device.

The button of the external device generates HOOKINT interrupt and is used to answer or end a phone call.

■ Audio modes

HP call

The basic audio mode is the hand portable mode. This is entere d whe n no audio accessories are connected and handsfree mode is not selected by opening the cover.

The call is created by CMT. The internal earpiece is driven by the CMT engine for voice calls. The internal microphone is driven by the CMT for voice calls and voice recording. The internal microphone is enabled and uses the MICB1 bias voltage from UEM.

IHF call

This mode can be entered by user selection (opening the cover). The call is created by CMT. The internal microphone is driven by the CMT for voice calls and

voice recording. The internal microphone is enabled and uses the MICB1 bias voltage from UEM as in HP mode.

XEAR output of UEM is used to drive mono output signal is connected to the APE Audio DAC. Signal is then routed to the Phone_In_IHF input of the LM4855. This drives the internal speaker via the SPKRout driver.

Accessory call

This mode is used when accessory is connected to the system connector. The call is created by CMT. The uplink signal is generated by external microphone and trans-

ferred to UEM MIC2 input (via XMIC signals from Pop-port bias voltage and MIC2P/N inputs are enabled on UEM.

As in IHF call down link audio signal is routed through the single ended XEAR output driver in UEM. The mono XEAR output is connected to the DAC and then signal is routed to the L

Issue 1 09/04 COMPANY CONFIDENTIAL 13

connector). Hence the MIC2B

and

RA-2/3

Nokia Customer Care 6 - Baseband Description and Troubleshooting

RIN inputs of the LM4855. Accessories are driven via Pop-portTM connector using the L

OUT

driver of LM4855.

APE audio

This mode is entered when user starts the multimedia application (e.g. MP3, AAC etc.), which is played via IHF speaker or Pop-port

Audio data from MMC is sent by OMAP1510 to the external audio DAC through the I nection. The DAC performs the digital to analog audio conversion.

For playback via the internal speaker signal from DAC is routed to Phone_in_IHF input on LM4855.

For playback via the stereo/ mono headset or other Pop-port is routed to the L

/RIN inputs of the LM4855. In case of mono accessory OMAP1510 will pro-

duce monophonic signal to DAC.

accessories.

S con-

accessories signal from DAC

■ Internal interfaces

In practice, all APE internal interfaces consist of interfaces connected from OMAP1510 to peripheral devices. All UI related interfaces, memory interfaces, USB and MMC are covered in separate sections of this document.

McBSP interfaces

OMAP1510 can support maximum of three independent Multi-channel Buffer Serial Ports (McBSPs) interfaces. However, these ports are slightly different and particularly suitable for different purposes. McBSP1 supports I2S protocol and is connected to external audio codec. McBSP#2 and #3 can be used as general purpose SPI interface supporting bit rates up to 5Mbits/s. McBSP2 is used to control the audio PA. McBSP3 clock output is used as audio codec master clock. Other McBSP3 signals cannot be used because they are multiplexed with uWire signals.

MCSI interfaces

The MCSI is a serial interface with multi-channels transmission capability. MCSI1 is used to interface with Bluetooth and MCSI2 is used as XABUS (DSP-DSP bus between CMT and APE)

UART interfaces

OMAP1510 has three UART interfaces capable of 1.5Mbit/s data rates. UART1 is used as Bluetooth control interface, UART2 is used as XBUS (MCU-MCU bus between CMT and APE), UART3 includes 115.2 kbit/s IrDA modulation support, and is used to communicate with external IrDA device.

UWire interface

The uWire interface is a standard serial synchronous bus protocol with two chip select lines. Interface is used as PDA LCD control bus (CS3) and as a unidirectional data bus for the Cover display (CS0).

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I2C

The I2C is a half-duplex serial port using two lines, data and clock, for data communications with software addressable external devices. I control bus. External keyboard controller COP8 is also connected to APE via I

C is used as audio codec and camera module

ARMIO

ARMIO provides 5 ARM processor controllable GPIOs by default, and 5 more are available with different multiplexing scheme. ARMIOs also include a keyboard interface. The GPIOs consists programmable debouncing circuit but can be accessed directly only by the ARM processor. Both ARMIOs and keyboard interface signals can wake-up OMAP1510 from deep sleep and big sleep states.

GPIO

14 General Purpose Input/ Output External pins are multiplexed between ARM/DSP. Multiplex logic is programmed and controlled by ARM and supports pin-by-pin configuration.

■ External interfaces

Back cover switch

A hall switch is used for back cover removal detection. A magnet is attached to the back cover. A sensor gives a warning to prevent data loss or corruption when writing to the MMC card.

Lid hall switch

A hall switch is used to detect the lid position. The switch is located on QWERTY PWB and is connected to COP8 controller. The magnet is in the lid.

MMC

The MMC Interface in OMAP1510 is fully compliant with the MultiMediaCard system specification version 3.1. RA-2/3 MMC interface voltage is 3 V.

USB

The OMAP1510 USB Controller is a Full Speed Device (12 Mb/s) fully compliant with the Universal Serial Bus specification Revision 2.0. The USB Client (a mobile terminal) is connected to the USB Host (a PC) through the system connector.

■ UI interfaces

Displays

S80 display interface

S80 display utilizes the 16-bit synchronous LCD interface of OMAP1510, and uWire for control data.

Cover display interface

RA-2/3 has a separate small 65k colours display connected to OMAP1510 via uWire interface. There is an unidirectional level shifter between OMAP and the display, so no da ta can be read from the display.

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RA-2/3

Nokia Customer Care 6 - Baseband Description and Troubleshooting

Figure 4:Display interfaces

OMA P1510

DOUT

DIN

Cs0

CLK

RST

Cs3

RST

Level

Shifte rs

CMT Disp la y

Da ta

CS Clock Re s e t

PDA Display

Din

Dout Clk CS

Re s e t

S S

Vid e o data

Vid e o

data

Keyboards

Cover keyboard and CBA buttons

The cover keyboard and the four CBA buttons are directly connected to the OMAP1510 keyboard matrix.

QWERTY

An external keyboard controller is used for the QWERTY keyboard. COP8 is connected via I2C bus to OMAP1510 with an additional interrupt line to OMAP1510.

Power button

The power button is connected directly to UEM in the DCT4 engine. See Chapter Power up and system states for further details on the power button operation.

Camera

8-bit parallel camera interface connects OMAP1510 chip to the camera module. I2C bus is used for controlling the camera module.

Main features

Imaging and resolution:

• VGA resolution 640x480

• 1/4" sensor area

• 16bit colours (5+6+5 / R+G+B)

• Frame rate 15fps in all modes (30fps for QVGA, QQVGA, QCIF and subQCIF)

• Three different exposure modes: normal, long (frame rate / 4) and extra long mode.

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• Automatic image features: luminance level control, white balance control, blemish detection and control, fluorescent flicker frequency detection

Optics:

• Fixed focus (from 30cm to infinity)

• Two plastic lenses with antireflection coating

• Viewing angle 50.7 degrees

•F 2.8

Interface

The camera module contains a CMOS image sensor, image processing functions, camera image data IF (8-bit parallel data interface + sync and clock signals) and control IF blocks. The camera is connected to the camera interface of the OMAP1510. I2C interface is used for camera control (slave address 78H). Control IF supports transfer rate up to 400kbit/s (Fast mode I2C bus). Parallel image data stream is conformity with CCIR656. OMAP1510 contains camera interface block, which contains the buffer, the clock divider, the interrupt generator, and Rhea registers.

The camera module is connected to OMAP1510 processor on Nokia engine PWB via flex and a 20-pin connector. Description and order of the signals are shown in Table 3, “Interface signals of camera module with 20-pin connector”. All the signals go through the camera flex.

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Nokia Customer Care 6 - Baseband Description and Troubleshooting

Table 3: Interface signals of camera module with 20-pin connector

Pin #Signal name

(Camera)

1 GND1 GND - Ground line corresponding to VDDI 2 D0 CAM_D0 O Digital output data (LSB) 3 SDA SDA I/O

4 D1 CAM_D1 O Digital output data 5 SCL SCL O

6 D2 CAM_D2 O Digital output data 7 VDDI V18 - Supply volt age to a ca mera module (for

8 D3 CAM_D3 O Digital output data 9 Extclk CAM_EXCLK I System clock from Nokia engine to the

Signal name

(Engine)

I/O/Z Description

Serial data line of I2C bus

Serial clock line of I2C bus

digital)

camera module. Typical value for camera is 1.0 V.

10 D4 CAM_D4 O Digital output data 11 GND3 GND - Ground line corresponding to Extclk 12 D5 CAM_D5 O Digital output data 13 HD CAM_HS O Horizontal synchronization data 14 D6 CAM_D6 O Digital output data 15 VD CAM_VS O Vertical synchronization data 16 D7 CAM_D7 O Digital output data (MSB) 17 VDD V28 - Supply voltage to camera module (for

analog and I/O) 18 Dclk CAM_LCLK O Data clock synchronization pulse 19 Vctrl CAM_RSTZ I Activating signal for the camera module

(active HIGH). The min. high level of

Vctrl must be 1.5 V. Voltage divider

used.

20 GND2 GND - Ground line corresponding to VDD

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Bluetooth

A single chip Bluetooth solution, BC02, is used in RA-2/3. The chip contains radio and baseband parts as well as MCU and on-chip ROM memory. Together with some external components (filter, balun etc.) and the antenna, it forms the Bluetooth system, which is attached to the host (OMAP1510). Bluetooth components are mounted directly to the PWB. Bluetooth antenna and filter are shared with WLAN.

IrDA

RA-2/3 design includes a small (height 2.2 mm) metal shielded module. The modules use speeds up to 115.2kbps.

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RA-2/3

Nokia Customer Care 6 - Baseband Description and Troubleshooting

Functional Description of WLAN

RA-2/3 has an integrated 11Mbps 802.11b capable WLAN radio. WLAN power supply is based on a set of linear regulators and a load switch. A 22MHz crystal oscillator supplies main WLAN clock. Bluetooth shares the same physical antenna with WLAN.

The TNETW1100B MAC/BPP is connected to OMAP1510 flash memory interface via 16 data bits and 4 address bits, plus some control lines.

Figure 5:RA-2/3 WLAN block diagram

V28V18

2.4GHz WLAN

22MHz

BBP/MAC

VBAT

2.8V

1.8V2.8V

CORE

A_IO/A_AFE

IO/D_AFE A_AFE

RF Ctrl

EEPROM

A/D

D/A D/A

BBP

MAC

Host

ARM7

64kB

SRAM

RF5117

MAX2821

VCO/PLL

■ WLAN medium access controller

TNETW1100B

TNETW1100B implements basic IEEE802.11 functionality. The system is built on Arm7 and a dedicated DMA controller. Dedicated hardware accelerators for MAC protocol processing and WEP offload the processor. The chip integrates SRAM for storing both data and code.

DMA controller connects data memory and host interface with processor and baseband processor interface. Transmit and receive data buffers are implemented as linked lists of memory blocks. The DMA engine is capable of handling the lists without intervention from embedded Arm.

Clocking, reset and wake-up

WLAN uses a 22 MHz reference clock CMOS level signal. The reference oscillator has logic level enable signal and low-power sleep mode. The reference oscillator is controlled by a TNETW chip.

The sleep clock is derived from the GSM engine and it is constantly running. UEM generates 32 kHz sleep clock at 1.8 V signal level. UEM internal level converter is used to raise the sleep clock level to 2.8 V. The same sleep clock is used for both Helen and TNETW.

A Helen GPIO controls TNETW reset. Another GPIO controls the main power supplies to the WLAN hardware.

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Power up sequence

1. Helen enables the WLAN power regulators with a GPIO.

2. 50 ms delay to enable the WLAN powers to stabilize.

3. Helen takes the WLAN out of reset with a GPIO.

4. Helen configures EMIF_CS.

5. Helen activates TNETW1100B interface delay logic and enables the enhan ced slave mode.

6. Helen checks if the EEPROM is empty, and if it is empty, Helen programs a default content to it.

7. Helen downloads the WLAN firmware to the TNETW1100B and initializes it.

8. Power up sequence is complete.

■ WLAN – OMAP host interface

TNETW1100B is connected to Helen external memory interface (EMIFS). The interface is shared with RA-2/3 flash system consisting of NAND flash + controller on the same die (MDOC).

Figure 6:TNETW1100B and NAND Flash share Helen EMIFS interface

2.8 V TNETW1100B

Helen EMI FS

2.8 V

1Gb MDOC

TNETW1100B host interface I/O voltage is 2.8 V. Therefore the MDOC host interface also runs at 2.8V

Two GPIOs from Helen are used for controlling the WLAN hardware. One GPIO controls the main power supply regulators for WLAN, and the other is used for resetting the TNETW. One Helen Armio is used to generate interrupt from WLAN when Helen is in sleep. Helen can go to deep sleep while WLAN is active, ARMIO is capable of waking it up.

■ WLAN baseband processor

Baseband processor part of TNETW1100B implements signal processing required for transmission and reception of the IEEE802.11b signal. BBP includes mixed-signal interface to the radio (analog front-end, AFE).

Receiver portion of BBP controls the radio receive AGC and DC offset compensation circuitry. The receiver is capable of processing both long and short preambles and supports Barker and CCK modulations as well as proprietary 22 Mb/s PBCC mode.

Transmitter RF-BB interface

Transmitter RF-BB interfaces are shown in Figure 7, “Transmitter RF-BB interfaces” . TNETW has on-chip current mode differential output dual DAC for generating transmitted I/Q signals.

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The converters are clocked at 44 MHz. Current mode output is converted to differential voltage mode signals by means of resistive bias network (Q signal shown, I signal bias network identical). I/Q signals are fed into Maxim MAX2821 RFIC where they are modulated onto 2.4 GHz carrier.

Power amplifier is RF5117, which requires external OpAmp for transmit power detection, see Transmitter RF-BB interfaces.

Figure 7:Transmitter RF-BB interfaces

TNETW1100B

D/A

A/D

TX I TX Q

VGA_BIAS_CTL

TX_AGC

TX_PWR_DET

TX (RCTL_A1) RX (RCTL_A2) PA_EN (GPIO6) S_DATA, S_CLK, SER_EN

MAX2821

Mod

RF5117

Balun

TX RF

Receiver RF-BB interface

Receiver RF-BB interface is shown in Figure 8, “Receiver RF-BB interfaces” . Incoming RF signal is converted to differential signal in a balun. After balun there is a switchable LNA with high gain and low gain modes. The mode of the LNA is controlled by the TNETW based on the signal level on I/Q ADC output.

RX AGC control signal has a similar switchable resistive bias network as the transmitter chain. The switch is shared with TX AGC bias network.

Figure 8:Receiver RF-BB interfaces

RX RF

Balun

MAX2821

Demod

VGA_BIAS_CTL

TX (RCTL_A1)

RX (RCTL_A2)

RX I

RX Q

RX_AGC

AGC_STAT

ATT_SW

TNETW1100B

A/D

D/A

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■ WLAN energy management

WLAN regulators

Figure 9:WLAN EM block diagram

VBAT

3.0...4.2V

OMAP1510

WLAN

Power

Control

ORgate

V18

LM2708H

DC/DC Converter

1.8V@450mA

15mA in Linear

Mode

V28_WLAN_RF

LP3985

Regulator

2.8V @ 150mA

V28_WLAN_SYN

LP3985

Regulator

2.8V @ 150mA

GPIO7 GPIO 10

LOW_POWER

V18_WLAN_ANA

LP2985LV Regulator

1.8V @ 150mA

V28_WLAN_DIG

LP3985

Regulator

2.8V @ 150mA

V18_WLAN_DIG

FDG6331L

Power Switch

1.8V@100mohm

REFCLK_ENA

MAX2821

Zero_IF Transceiver

22MHz

Osc

TNETW1100B

BB/MAC

V30AAFE

V30AIO

V18AAFE

V33DAFE

V33DIO

V18DOSC

V18DCORE

V18DRAM

VDPCI

RFMD 5117 PA

V28

LP3981

Regulator

2.8V@300mA

Level shifted 32kHz Sleep Clock from

UEM (2.8V)

The 1.8V voltage for TNETW core and internal RAM is taken from DC-DC converter that is already present for powering Helen, SDRAM, etc. Helen controls the 1.8V voltage to TNETW by a load switch. The same Helen GPIO is used for controlling the 2. 8V linear regulator powering WLAN RF, TNETW analog IOs and AFE (analog front end). Another Helen controlled 2.8V linear regulator supplies TNETW digital IOs and D_AFE (digital parts of analog front end).

WLAN controls the DC-DC converter LDO mode together with APE. When WLAN is in active mode (i.e. Not in poweroff, doze or sleep), the REFCLK_ENA signal from TNETW1100B forces the DC-DC converter to active mode.

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TNETW controls two regulators to minimize current consumption during sleep mode. The 1.8V regulator supplies the A_AFE (analog parts of analog front end). The 2.8V regulator supplies the synthesizer part of MAX2821.

WLAN RF power amplifier is powered directly from VBAT. VBAT voltage is nominally 3.6 V, but reaches 4.8 V momentarily at the end of the charging. After charging the battery voltage can reach 4.2 V.

The 22 MHz reference oscillator has an enable signal and therefore it has no dedicated regulator.

WLAN EM concept and battery capacity

WLAN engine has two major power management modes: sleep and active. It is also possible to shut down the WLAN for reduced power but the wake-up time is in the order of seconds. Shutting down the WLAN is used when the user chooses to deactivate the WLAN by selecting Bluetooth.

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Table 4: WLAN power modes

Mode Description Current

Power Off

WLAN is powered down. Entering active mode requires firmware download and

~ 0 µA ~ 1 s

configuration of the WLAN engine. Wakeup can only be initiated by the host.

Deep Sleep

Deep Sleep is physically the same mode as Doze. Logical connection to network is

53µA 2-3 ms

not (yet) established. This is the state after firmware download and issuing sleep command. WLAN runs from 32 kHz sleepclock and 22 MHz reference clock is turned off. Radio is in low current standby mode. Analog 1.8V supply to TNETW and 2.8V synthesizer supply are turned off by TNETW to further reduce current consumption.

Doze Doze mode is similar to Deep Sleep

53 µA 2-3 ms mode. Wake-up time is dominated by the 22 MHz reference oscillator start-up time.

Wake-up

time

Active In active mode the WLAN system is

either in receive or transmit mode.

Note1: Values roughly estimated

~220 mA RX,

~270 mA TX.

WLAN MAC takes care of the transitions between Doze and Active mode. It also automatically controls the radio active modes (transmit and receive). These transitions are initiated by MAC protocol state machine. For example, mode change is initia ted when the host starts data transfer or when the MAC decides to listen for incoming beacons.

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Energy Management

Energy Management covers both CMT and APE sides. WLAN energy management is considered to be part of WLAN subsystem. Battery and charging functions are integrated into CMT Universal Energy Management (UEM) ASIC. UEM includes also all needed regulators for CMT BB and RF. APE side has its own discrete power supplies.

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