Nokia 8270 Service Manual 3 nsd5sys
Programmes After Market Services
NSD-5 Series Transceivers
3. System Module
Issue 1 05/02 Nokia Corporation
NSD-5
3. System Module PAMS Technical Documentation
Page 2 Nokia Corporation Issue 1 05/02
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PAMS Technical Documentation 3. System Module
Contents
Page No
Transceiver NSD-5 ........................................................................................................ 7
Introduction ..................................................................................................................7
Modes of Operation .....................................................................................................7
Interconnection Diagram........................................................................................... 8
System Module ............................................................................................................9
Circuit Description.................................................................................................... 9
Connectors ...................................................................................................................9
System Connector ..................................................................................................... 9
Baseband Module and Interface ................................................................................10
Block Diagram ........................................................................................................ 10
Baseband Elements ................................................................................................. 10
Baseband ASICS Description ................................................................................. 10
Baseband-related External Interface ....................................................................... 11
FBUS....................................................................................................................... 11
MBUS...................................................................................................................... 11
JTAG Interface........................................................................................................ 11
MAD4/External Memories Interface ...................................................................... 11
Functional Timing Parameters................................................................................ 13
MAD4/VIBRA Interface......................................................................................... 14
MAD4/RF Interface ................................................................................................ 15
MAD4/RF Synthesizer Interface............................................................................. 15
Functional Description............................................................................................ 15
Signal Definitions.................................................................................................... 15
MAD4/RF Receiver and Transmitter Interface....................................................... 17
Functional Description............................................................................................ 17
Signal Definitions.................................................................................................... 17
CAFE Module/Interface ............................................................................................19
CAFE Module Description...................................................................................... 19
Detailed Module Description .....................................................................................20
CDMA Mode........................................................................................................... 20
Clock ....................................................................................................................... 21
Audio....................................................................................................................... 21
General Description................................................................................................. 22
CAFE/MAD4 Serial Data Interface........................................................................ 24
CAFE/MAD4 TX Interface..................................................................................... 24
TX Gate Enable....................................................................................................... 24
CAFE/MAD4 Clock/Reset Interface ...................................................................... 24
CAFE/RF Interface ................................................................................................. 25
General Description................................................................................................. 25
RX/CAFE CDMA RX Interface............................................................................. 26
RF/CAFE CDMA TX Interfaces............................................................................. 27
Power Management (CCONT) Module and Interface ...............................................27
CCONT Module Functional Description................................................................ 27
CCONT Regulators................................................................................................. 28
Watchdog ................................................................................................................ 29
Power Up ...................................................................................................................29
Power Up by Power Button..................................................................................... 31
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Power Up When Charger Connected ...................................................................... 32
Power Up by IBI ..................................................................................................... 33
Power Up With RTC............................................................................................... 33
Charging – CHAPS ....................................................................................................33
CCONT/MAD4 and CCONT/Others Interface Signals ............................................34
User Interface .............................................................................................................36
Functional Description............................................................................................ 36
Signal Definitions.................................................................................................... 36
Functional Timing................................................................................................... 37
Serial Port Functional Timing................................................................................. 37
System/Accessory Interface .......................................................................................38
Description.............................................................................................................. 38
Signal Definitions.................................................................................................... 38
IR Interface.............................................................................................................. 39
Audio Accessories................................................................................................... 39
Battery Interface...................................................................................................... 40
Signal Characteristics.............................................................................................. 40
BSI and BTEMP Connections................................................................................. 40
BTEMP Connections............................................................................................... 40
BTEMP Connections, IBI Accessories................................................................... 41
BSI Connections...................................................................................................... 41
RF Module Overview ................................................................................................42
Environmental Specifications ................................................................................. 42
Vibration and Free Fall ........................................................................................... 42
Humidity and Water Resistance.............................................................................. 42
Technical Specifications ......................................................................................... 42
Maximum Ratings................................................................................................... 43
RF Connector .......................................................................................................... 43
Single Band Internal Antenna ................................................................................. 43
Transmitter .................................................................................................................43
Duplexer.................................................................................................................. 43
Power Amplifiers Module 1900MHz...................................................................... 43
1900MHz Transmitter Interstage Filtering ............................................................. 44
1900MHz Upconverter............................................................................................ 44
Driver ...................................................................................................................... 44
Transmitter Intermediate Frequency (TIF) ............................................................. 44
Receiver .....................................................................................................................45
Front End................................................................................................................. 45
Interstage SAW Filter.............................................................................................. 46
IF SAW Filter.......................................................................................................... 46
Receiver Intermediate Frequency (RIF).................................................................. 46
CDMA AGC ........................................................................................................... 47
IQ Demodulator....................................................................................................... 47
Synthesizer .................................................................................................................47
1st Rx/2nd Tx UHF LO Synthesizer....................................................................... 47
1st Tx VHF LO Synthesizer.................................................................................... 47
2nd Rx VHF LO Synthesizer.................................................................................. 48
System Reference Oscillator (VCTCXO)............................................................... 48
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Functional Description of LMX2330L ................................................................... 49
RF-Baseband Connections .........................................................................................55
RF Regulators ............................................................................................................57
Reference ..................................................................................................................... 58
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PAMS Technical Documentation 3. System Module
Transceiver NSD-5
Introduction
The NSD-5 is a single-band radio transceiver unit for the CDMA 1900 MHz network. TX
operates at 5V. The transceiver consists of System/RF module, User Interface module, and
assembly parts.
The RF interface, which is documented in this chapter, provides internal signal definition
and an internal interface that defines the characteristics of RF intra-module signals.
The baseband section defines the signal parameters between baseband intra-modules, as
well as the interface between baseband and RF. This section of the chapter also defines
the communication protocol between some of the submodules.
The third section of this chapter describes the interface between UI and baseband. Characteristics of interface signals between UI and baseband are defined as well.
The fourth section of the chapter covers the interface between system (transceiver) and
external accessories, including plug-and-play (PPH), headset, and battery.
Modes of Operation
There are five different operation modes:
• power-off mode
• idle mode
• active mode
• charge mode
• local mode
In the power-off mode, only the circuits needed for power-up are supplied.
In the idle mode, circuits are powered down and only the sleep clock is running.
In the active mode, all the circuits are supplied with power — although some parts might
be in the idle state part of the time.
The charge mode is effective in parallel with all the previous modes. The charge mode
itself consists of two different states: charge and maintenance mode.
The local mode is used for alignment and testing.
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Interconnection Diagram
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System Module
Circuit Description
The transceiver electronics consist of the Radio Module, RF + System blocks, the UI PCB,
the display module, and audio components. The keypad and the display module are connected to the Radio Module with connectors. System blocks and RF blocks are interconnected with PCB wiring. The Transceiver is connected to accessories via a bottom system
connector with charging and accessory control.
The RF block is designed for a handportable phone which operates in the CDMA 1900
system. The purpose of the RF block is to receive and de-modulate the radio frequency
signal from the base station and to transmit a modulated RF signal to the base station.
Connectors
System Connector
Figure 1: Bottom Connector
Note: Intelligent Battery Interface, IBI, is an accessory interface on the battery side of
the phone including the same signals as the bottom connector. The accessory (e.g., an IBI
accessory) can be a battery pack with special features or an accessory module attached
between the phone and a normal battery pack.
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Baseband Module and Interface
Block Diagram
TX/RX SIGNALS
Cafe SUPPLY
RF SUPPLIES
PA SUPPLY
SYSTEM CLOCK
19.2MHzCLK
UI
Baseband Elements
Baseband refers to all technology elements in the phone design, which do not include RF
functions. The Baseband Module therefore includes audio, logic control, signal processing, power supply, and user interface functions. Baseband functionality of this product
consists of third generation Digital Core Technology (DCT3) design solutions.
CCONT
BB SUPPLY
SYSCON
CHARGING
SWITCH
SLEEP CLOCK
BASEBAND
Cafe
MEMORIES
AUDIOLINES
MAD
+
Figure 2: Baseband Module and Interface Block Diagram
32kHz
CLK
VBAT
BATTERY
Baseband ASICS Description
MAD4
The MAD4 submodule includes the MAD4 ASIC (MCU, DSP, System Logic), external memories, and VIBRA circuitry.
The MCU block is used for general purpose processing applications such as UI control,
timers, PUP control, RX modem interface, audio control, evaluation of sensor data from
CCONT A\D, and battery charging control.
The DSP accommodates all communication protocols, such as CDMA data processing.
DSP also handles speech signal processing (e.g., vocodor).
The System Logic component includes: peripheral interface (MCU Parallel I/O, Serial I/O
[FBUS/MBUS]) and PWM control; accessory interface (FBUS); external memories interface; RF interface and control; clocking, timing, and interrupts; sleep control; CAFE control; user interface control; reset generator; clock generator; and test interface.
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Baseband-related External Interface
For detailed information on interfaces to CCONT, CAFE, UI, and accessories, consult the
CCONT, CAFE, and accessory modules in this chapter.
FBUS
FBUS (Fast Bus) is a serial interface between the DSP and data accessories and between
the DSP and multipath analyzer. FBUS also is used as a data path during flash code
downloading. This interface is a full-duplex, asynchronous, two-line bus. Figure 3 illustrates the timing for the FBUS.
Figure 3: USART synchronous mode receive (flashing mode)
Parameter Definition Minimum Maximum Unit
Tsds Data setup to rising edge 90 110 ns
Tsdh Data hold from rising edge 90 110 ns
MBUS
MBUS is a serial data bus of MCU, which is used for flash downloading (clock), testing,
and communication with external devices. Supported baud rates are 9.6, 19.2, 38.4, and
57.6 kbit/s.
JTAG Interface
JTAG Interface is used for MAD4 ASIC emulation including DSP and MCU emulation.
MAD4/External Memories Interface
Functional Description
The external memory consists of FLASH, SRAM, and EEPROM.
FLASH is used to contain the main program code for the MCU and EEPROM default values (local factory values). It has 2M x 16-bit size and uBGA package.
EEPROM stores tuning parameters and other systems permanently. Its size is 128k bytes.
The external memory interface is shared between the DSP and MCU processors. Both
8-bit and 16-bit external memories are supported. The interface supplies 22 address bits
to allow the MCU/DSP to address up to 4 Mbytes of linear address space for ROM1,
ROM2, and parallel EEPROM and 1 Mbyte of linear address space for SRAM (defined by
the chip-select signals). The DSP will use only the lower 16 bits of the address, and a
bank register is provided to set the 64K-word window for external memory accesses. A
read strobe, write strobe, and four-chip selects are provided for external memories.
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Table 1 illustrates the signal characteristics of the interface. Also see the MAD4 Technical Specification (Reference 1) for decoding memory map and chip selects.
Figure 4: Memory interface
Signal
MEMAD(21:0) < 0.62 > 2.24 MCU/DSP address bus to external memory
MEMDA(15:0) < 0.62 > 2.24 MCU/DSP bidirectional data bus to external
MEMRDX < 0.62 > 2.24 Read strobe to external memory
MEMWRX < 0.62 > 2.24 Write strobe to external memory
ROM1SELX < 0.62 > 2.24 FLASH chip select
ROM2SELX < 0.62 > 2.24 Not used
RAMSELX < 0.62 > 2.24 SRAM chip select
EEPROMSDA < 0.62 > 2.24 EEPROM serial data
Level (V)
Low High
Functional description
memory
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Signal
EEPROMSCLK < 0.62 > 2.24 EEPROM serial data clock
Level (V)
Low High
Table 1: Electrical characteristics of the external memory interface
Functional description
Functional Timing Parameters
Memory access timing is treated asynchronously. There are two reasons for this type of
access. First, the external memories are inherently asynchronous. Second, two separate
processors running at different frequencies share the memories.
The following two figures (Figure 5 and Figure 6) provide timing information on MAD4
memory access. See MAD4 Technical Specifications (Reference 1) and DCT3 MAD4
Resource Manager Specification and Implementation (Reference 2) for additional timing
information on external memory read/write cycles.
Figure 5: External memory write cycle
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Figure 6: External memory read cycle
Parameters Flash memory SRAM
Min (ns) Max (ns) Min (ns) Max (ns)
Memory Write
Ts(addr) 70 80
Th(addr) 0 0
Ts(data) 60 40
Th(data) 0 0
Ts(ce) 70 80
Th(ce) 0 0
Tw(we) 70 70
Memory Read
Tcyc 110 100
Td(addr) 110 100
Td(oe) 30 50
Td(ce) 110 100
Table 2: Timing information for Read/Write cycle required/provided by memory chips
MAD4/VIBRA Interface
VIBRA is a vibrating motor, used as a silent alarm device. It is driven by 11kHz or 22kHz
PWM signal, with a variable duty cycle to control the average current into the motor,
which in turn controls the intensity of the alarm. The duty cycle is set by software and
depends on the motor and the limits of the duty cycle.
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MAD4/RF Interface
MAD4/RF Synthesizer Interface
Functional Description
Figure 7 defines the MAD4/RF synthesizer interface. The synthesizer interface is capable
of programming National LMX2330L Dual PLL Frequency Synthesizer. See Figure 8 and
Reference 1 for synthesizer timing information such as set-up and hold time.
Signal Definitions
SYN_DAT
Figure 7: RF/MAD synthesizer interface
Figure 8: Synthesizer serial timing
Data sent from MAD pin E17 (mdRFSData) to the synthesizer divider and counters. It has
2.8V CMOS logic level.
High Low Reset/Inactive Current Filtering
Vdd - 0.6V 0 - 0.5V Low/low > 50 ns 1 mA max None
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SYN_CLK
19.2000 MHz clock sent from MAD pin E16 (mdRFSClk) to synthesizer. The rising edge of
the clock is used to clock data into the synthesizer.
High Low Reset/Inactive Current Filtering
Vdd - 0.6V 0 - 0.5V Low/low > 50 ns 1 mA max None
SYN_LE1
Loading enable signal from MAD pin F16 (mdRFSLE1) to RF for the dual synthesizer. See
data sheet of the synthesizer for details.
High Low Reset/Inactive Current Filtering
Vdd - 0.6V 0 - 0.5V Low/low > 50 ns 1 mA max None
AFC
Signal from MAD pin B17 (mdAFC) to RF VCTCXO to provide 19.2 MHz reference frequency adjustment. It is active in CDMA. When the level is above 1.2V, the frequency is
increased.
Type Range Resolution Current Filtering
PDM 0 - 2.8V 9bits @ 9.6MHz clock < 1 mA
BB: RC = 4.7 x 10
RF: RC = 1.0 x 10
-4
-5
Sec
Sec
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MAD4/RF Receiver and Transmitter Interface
Figure 9: MAD/RF TX/RX interface
Functional Description
Figure 9 shows the interface between MAD4 and RF receiver and transmitter. It includes
transmitter enable/disable, and RF power controlling. Some of the control signals have
2.8 CMOS level, while others have a PDM signal, which can be used to control RF behavior. The MAD4 PDM output is 2.8 V CMOS digital signal with pulse duration modulated
with 9.6 MHz clock. Baseband provides low pass filter to smooth the signal and avoid
digital noise into RF ground plane.
Signal Definitions
TIF_EN
High Low Load impedance Polarity Rising Time Filtering
Vdd - 0.6V 0 - 0.5V Min: 20k
Typ: 200k
Low: Disable < 25 ns
(10% - 90%)
None
RF_TX_GATE_P
Signal from MAD4 pin B14 (RF_TX_GATE_P) to RF transmitter to activate the bias of cel-
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lular PA section and switch regulator providing cellular PA driver. PA is activated discontinuously in CDMA mode.
High Low Polarity Rising time Filtering
Vdd - 0.6V 0 - 0.5V High: TX on
Low: TX off
< 25 ns
(10% - 90%_)
BB: RC = 1.0 x 10
TX_LIM
Signal from RF transmitter to MAD4 pin E15 (rfTxLim) to indicate maximum allowed output power is being exceeded, therefore to dynamically adjust the maximum commanded
transmitter gain in CDMA mode.
High Low Polarity Rising time
Vdd - 0.6V 0 - 0.5V High: Power exceeded
Low: Power not exceeded
< 10 ns
TX_LIM_ADJ
Signal from MAD4 pin D16 (mdGPPDM2) to RF transmitter to set trig point of indicator
where maximum transmit power is exceeded in CDMA.
Type Range Resolution
PDM 0.3V - 2.8 V 8bits @ 9.6 MHz clock 1M
Load
impedance
-5
sec
Filtering
BB: RC = 1.0 x 10
-4
sec
TX_IF_AGC
Signal from MAD4 pin A15 (mdTxlfAgc) to IF VGA to control the gain of the transmit IF
section.
Type Range Resolution Filtering
PDM 0.3V - 2.8 V 9bits @ 9.6 MHz clock
BB: RC = 2.2 x 10
Signal from MAD4 pin C14 (mdTxIfAgc) to RF VGA to control the gain of the transmit RF
section. It tracks TX_IF_AGC signal with separate slope adjustment.
Type Range Resolution Filtering
PDM 0.3V - 2.5 V 8bits @ 9.6 MHz clock
BB: RC = 2.2 x 10
RIF_EN
Signal from MAD pin D2 (mdP1GPIO(2)) to RIF to enable RIF and to provide AGC reference with PDM high voltage.
-5
sec
-5
sec
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