The Baseband module of the RH-34 transceiver is a trimode CDMA dual band engine. The
Baseband architecture is based on the DCT4 Apollo engine.
RH-34 Baseband consists of three main ASIC's: Universal Energy Management (UEM),
Universal Phone Processor (UPP), and a 128-Megabit FLASH.
The Baseband architecture supports a power-saving function called "sleep mode". This
sleep mode shuts off the VCTCXO, which is used as system clock source for both RF and
Baseband. During the sleep mode, the system runs from a 32 kHz crystal. The phone
awakes by a timer running from this 32 kHz clock. The sleep time is determined by network parameters. Sleep mode is entered when both the MCU and the DSP are in standby
mode and the 19.2MHz Clk (VCTCXO) is switched off.
RH-34 supports both two and three DCT3 type wire chargers. However, the three-wire
chargers are treated as two-type wire chargers. Charging is controlled by UEM ASIC and
EM SW.
BLD-3 Li-ion battery is used as main power source for RH-34. BLD-3 has nominal capacity of 780 mAh.
Power up and reset is controlled by the UEM ASIC. RH-34 baseband can be powered up
in the following ways:
1By the Power button, which means grounding the PWRONX pin of the UEM
2By connecting the charger to the charger input
3By the RTC Alarm, when the RTC logic has been programmed to give an alarm
After receiving one of the above signals, the UEM counts a 20ms delay and then enters in
reset mode. The watchdog starts up, and if the battery voltage is greater than Vcoff+, a
200ms delay is started to allow references, etc. to settle. After this delay elapses, the
VFLASH1 regulator is enabled. Then, 500us later VR3, VANA, VIO, and VCORE are enabled.
Finally, the PURX (Power Up Reset) line is held low for 20 ms. This reset, PURX, is fed to
the baseband ASIC UPP; resets are generated for the MCU and the DSP. During this reset
phase, the UEM forces the VCTCXO regulator on — regardless of the status of the sleep
control input signal — to the UEM. The FLSRSTx from the ASIC is used to reset the flash
during power up and to put the flash in power down during sleep. All baseband regulators are switched on when the UEM powers on. The UEM internal watchdogs are running
during the UEM reset state, with the longest watchdog time selected. If the watchdog
expires, the UEM returns to power-off state. The UEM watchdogs are internally acknowledged at the rising edge of the PURX signal in order to always give the same watchdog
response time to the MCU.
The following diagram represents UEM start-up sequence from reset to power-on mode.
When the Power on key is pressed, the UEM enters the power up sequence. Pressing the
power key causes the PWRONX pin on the UEM to be grounded. The UEM PWRONX signal is not part of the keypad matrix. The power key is only connected to the UEM. This
means that when pressing the power key, an interrupt is generated to the UPP that starts
the MCU. The MCU then reads the UEM interrupt register and notices that it is a
PWRONX interrupt. The MCU now reads the status of the PWRONX signal using the UEM
control bus, CBUS. If the PWRONX signal stays low for a certain time, the MCU accepts
this as a valid power on state and continues with the SW initialization of the baseband.
If the power on key does not indicate a valid power on situation the MCU powers off the
baseband.
Power up when charger is connected
In order to be able to detect and start charging in the case where the main battery is
fully discharged (empty) and hence UEM has no supply (NO_SUPPLY or BACKUP mode of
UEM), charging is controlled by START-UP CHARGING circuitry.
Whenever VBAT level is detected to be below master reset threshold (VMSTR-), charging
starts and is controlled by START_UP charge circuitry. Connecting a charger forces
VCHAR input to rise above the charger detection threshold, VCHDET+, and by detection
charging is started. UEM generates 100mA constant output current from the connected
charger's output voltage. As battery charges, its voltage rises and when VBAT voltage
level is detected to be higher than the master reset threshold limit (VMSTR+), START_UP
charge is terminated.
Monitoring the VBAT voltage level is done by charge control block (CHACON). MSTRX='1'
output reset signal (internal to UEM) is given to UEM's RESET block when VBAT>VMSTR+
and UEM enters into reset sequence.
If VBAT is detected to fall below VMSTR- during start-up charging, charging is cancelled.
It will restart if new rising edge on VCHAR input is detected (VCHAR rising above VCHDET+).
RTC alarm power up
If phone is in POWER_OFF mode when RTC alarm occurs, a wake-up procedure occurs.
After baseband is powered ON, an interrupt is given to MCU. When RTC alarm occurs
during ACTIVE mode, an interrupt to MCU is generated.
Power Off
The Baseband switches into power off mode if any of following statements is true
• Power key is pressed
• Battery voltage is too low (VBATT < 3.2 V)
• Or if Watchdog timer register expires
The Power down procedure is controlled by the UEM.
Power Consumption and Operation Modes
During power off mode, power (VBAT) is supplied to UEM, BUZZER, VIBRA, LED, PA and
PA drivers (Tomcat and Hornet). During this mode, the current consumption on this mode
is approximately 35uA. This is the UEM leakage current.
In sleep mode, both processors, MCU and DSP, are in stand-by mode. Phone will go to
sleep mode only when by both processors made this request. When SLEEPX signal is
detected low by the UEM, the phone enters SLEEP mode. VIO and VFLASH1 regulators are
put into low quiescent current mode, VCORE enters LDO mode and VANA and VFLASH2
regulators are disabled. All RF regulators are disabled during SLEEP mode. When SLEEPX
signal is detected high by the UEM, the phone enters ACTIVE mode and all functions are
activated.
The sleep mode is exited either by the expiration of a sleep clock counter in the UEM or
by some external interrupt, generated by a charger connection, key press, headset connection etc.
In sleep mode, the VCTCXO (19.2MHz Clk) is shut down and the 32 kHz sleep clock oscillator is used as reference clock for the baseband.
The average current consumption of the phone can vary depending mainly on SW state
like slot cycle 0, 1, or 2 and if the phone is working on IS95 or IS2000 for CDMA; however, on average is about 6 mA in slot cycle 0 on IS95.
In the ACTIVE mode, the phone is in normal operation, scanning for channels, listening to
a base station, transmitting and processing information. There are several sub-states in
the active mode depending on the phone present state such as: burst reception, burst
transmission, if DSP is working etc.
In active mode, SW controls the UEM RF regulators: VR1A and VR1B can be enabled or
disabled. These regulators work of the UEM charge pump. VSIM can be enabled or disabled and its output voltage can be programmed to be 1.8V or 3.3V. VR2 and VR4 -VR7
can be enabled or disabled or forced into low quiescent current mode. VR3 is always
enabled in active mode and disabled during Sleep mode and cannot be control by SW in
the same way as the other regulators. VR3 will only turn off if both processors (DSP and
MCU) request to be in sleep mode.
CHARGING mode can be performed in parallel with any other operating mode. A BSI
resistor inside the battery indicates the battery type/size. The resistor value corresponds
to a specific battery type and capacity. This capacity value is related to the battery technology.
Power
The battery voltage, temperature, size and charging current are measured by the UEM,
and the EM charging algorithm controls it.
The charging control circuitry (CHACON) inside the UEM controls the charging current
delivered from the charger to the battery. The battery voltage rise is limited by turning
the UEM switch off, when the battery voltage has reached 4.2 V. Charging current is
monitored by measuring the voltage drop across a 220 mOhm resistor.
In normal operation, the baseband is powered from the phone's battery. The battery consists of one Lithium-Ion cell. In the case of Lancelot, the battery capacity is 850 mAh.
The UEM ASIC controls the power distribution to whole phone through the BB and RF
regulators excluding the power amplifier (PA) and the DC/DC, which have a continuous
power rail directly from the battery. The battery feeds power directly to following parts
of the system: UEM, PA, DC/DC, buzzer, Vibra, display- and keyboard lights.
The heart of the power distribution to the phone is the power control ASIC, called UEM.
It includes all the voltage regulators and feeds power to the whole system. UEM handles
hardware functions of power up so that regulators are not powered and power up reset
(PURX) is not released if the battery voltage is less than 2.8 V.
RH-34 Baseband is powered from five different UEM regulators: VANA, VIO, VFLASH1,
VFLASH2, and VCORE DC/DC. See Table 1.
UEM voltage regulators: VR1A, VR1B, VR2, VR3, VR4, VR5, VR6 and VR7 are used by RF.
See Table 2.
VIO1501.8Enabled always except during power-off mode
VFLASH1702.78Enabled always except during power-off mode
VFLASH2402.78Enabled only when data cable is connected
VANA802.78Enabled only when the system is awake (off during sleep and
VSIM253.0
Regulator
VR1A104.75Enabled when the receiver is on
VR1B104.75Enabled when the transmitter is on
VR21002.78Enabled when the transmitter is on
3001.5Output voltage selectable 1.0V/1.3V/1.5V/1.8V
Default power at power-up is 1.5V
power-off modes)
Table 2: RH-34 RF Regulators
Maximum
current
(mA)
Vout (V)Notes
VR3202.78Enabled when SleepX is high
VR4502.78Enabled when the receiver is on
VR5502.78Enabled when the receiver is on
VR6502.78Enabled when the transmitter is on
VR7452.78Enabled when the receiver is on
A charge pump used by VR1A is constructed around UEM. The charge pump works with
Cbus (1.2 MHz Clk) and gives a 4.75 V regulated output voltage to RF.
Clock Distribution
RFClk (19.2 MHz Analog)
The main clock signal for the baseband is generated from the voltage and temperature
controlled crystal oscillator VCTCXO (G503). This 19.2 MHz clock signal is generated at
the RF and fed to RFCLK pin of UPP.
The UPP distributes the 19.2 MHz Clk to the internal processors, the DSP, and MCU,
where SW multiplies this clock by seven for the DSP and by two for the MCU.
A 1.2 MHz clock signal is used for CBUS, which is used by the MCU to transfer data
between UEM and UPP.
DBUS Clk Interface
A 9.6 MHz clock signal is used for DBUS, which is used by the DSP to transfer data
between UEM and UPP.
The system clock can stopped during sleep mode by disabling the VCTCXO power supply
from the UEM regulator output (VR3) by turning off the controlled output signal SleepX
from UPP.
The UEM provides a 32kHz sleep clock for internal use and to UPP, where it is used for
the sleep mode timing.
SleepCLK (Analog)
When the system enters sleep mode or power off mode, the external 32KHz crystal provides a reference to the UEM RTC circuit to turn on the phone during power off or sleep
mode.
The Flash programming equipment is connected to the baseband using test pads for galvanic connection. The test pads are allocated in such a way that they can be accessed
when the phone is assembled. The flash programming interface consist of the VPP,
FBUSTX, FBUSRX, MBUS, and BSI signals and use by the FPS8 to flash. The connection is
through the UEM which means that the logic voltage levels are corresponding to 2.78V.
Power is supplied to the phone using the battery contacts.
Baseband Power Up
The baseband power is controller by the flash prommer in production and in re-programming situations. Applying supply voltage to the battery terminals will cause the baseband to power up. Once the baseband is powered, flash programming indication is done
as described in the following section.
Flash Programming Indication
Flash programming is indicated to the UPP using MBUSRX signal between UPP and UEM.
The MBUS signal from the baseband to the flash prommer is used as clock for the synchronous communication. The flash prommer keeps the MBUS line low during UPP boot
to indicate that the flash prommer is connected. If the UPP MBUSRX signal is low on
UPP, the MCU enters flash programming mode. In order to avoid accidental entry to the
flash-programming mode, the MCU only waits for a specified time to get input data from
the flash prommer. If the timer expires without any data being received, the MCU will
continue the boot sequence. The MBUS signal from UEM to the external connection is
used as clock during flash programming. This means that flash-programming clock is
supplied to UPP on the MBUSRX signal.
The flash prommer indicates the UEM that flash programming/reprogramming by writing
an 8-bit password to the UEM. The data is transmitted on the FBUSRX line and the UEM
clocks the data on the FBUSRX line into a shift register. When the 8 bits have been
shifted in the register, the flash prommer generates a falling edge on the BSI line. This
loads the shift register content in the UEM into a compare register. If the 8-bits in the
compare registers matches with the default value preset in the UEM, programming
starts. At this point the flash prommer shall pull the MBUS signal to UEM low in order to
indicate to the MCU that the flash prommer is connected. The UEM reset state machine
performs a reset to the system, PURX low for 20 ms. The UEM flash programming mode is
valid until MCU sets a bit in the UEM register that indicates the end of flash programming. Setting this bit also clears the compare register in the UEM previously loaded at
the falling edge of the BSI signal. During the flash programming mode the UEM watchdogs are disabled. Setting the bit indicating end of flash programming enables and resets
the UEM watchdog timer to its default value. Clearing the flash programming bit also
causes the UEM to generate a reset to the UPP.
The BSI signal is used to load the value into the compare register. In order to avoid spurious loading of the register the BSI signal will be gated during UEM master reset and during power on when PURX is active. The BSI signal should not change state during normal
operation unless the battery is extracted, in this case the BSI signal will be pulled high,
note a falling edge is required to load the compare register.
Flashing
Flash programming is done through VPP, FBUSTX, FBUSRX, MBUS, and BSI signals.
When phone has entered to flash programming mode, prommer will indicate to UEM
that flash programming will take place by writing 8-bit password to UEM. Prommer will
first set BSI to "1" and then uses FBUSRX for writing and MBUS for clocking. After that
BSI is set back to "0".
MCU will indicate to prommer that it has been noticed, by using FBUSTX signal. After
this it reports UPP type ID and is ready to receive secondary boot code to its internal
SRAM.
FLASH_1
CH1 = BSI
CH2 = MBUS
CH3 = FBUSTX
CH4 = FBUSRX
Measure points
Production test pattern
(J396)
Figure 1: Flashing start
This boot code asks MCU to report prommer phone’s configuration information, including flash device type. Now the prommer can select and send algorithm code to MCU
SRAM (and SRAM/Flash self-tests can be executed)