Fault finding chart for UHF Synthesizer ................................................................ 55
Test Point Diagrams................................................................................................ 56
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9. TroubleshootingPAMS Te chnical Documentation
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NHP-2
PAMS Technical Documentation9. Troubleshooting
Transceiver Troubleshooting
Baseband Description
The baseband module is a CDMA dual-band engine. Baseband architecture is based on
the DCT4 Apollo engine. The baseband consists of three new ASICs: Universal Energy
Management (UEM), Universal Phone Processor (UPP), and Flash 64 Megabit.
The baseband architecture supports a power-saving function called “sleep mode”. This
sleep mode shuts off the VCTCXO, which is used as a system clock source for both RF and
Baseband. During the sleep mode, the system runs from a 32 kHz crystal. The phone is
wakened by a timer running from this 32 kHz clock supply. The sleep time is determined
by network parameters. Sleep mode is entered when both the MCU and the DSP are in
standby mode and the normal VCTCXO clock is switched off.
NHP-2 supports both three- and two-wire types of DCT3 chargers. There is a separate
PWM output for controlling the three-wire charger. Charging is controlled by the UEM
ASIC and by EM SW running in the UPP.
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NHP-2
9. TroubleshootingPAMS Te chnical Documentation
BB and RF Architecture
Figure 1: NHP-2 Power Distribution
Power Up and Reset
Power up and reset is controlled by the UEM ASIC. There are three ways to power up the
baseband module:
1Power Button (grounding the PWRONX pin of the UEM).
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PAMS Technical Documentation9. Troubleshooting
2Connect the charger to the charger input.
3RTC Alarm (when the RTC logic has been programmed to give an alarm).
Reference signal
PwrOnX
Charger Detection
RTC
UEMRSTX
VFlash1
VIO
VCORE
VANA
VR3
19.2MHz Clk
PURX
32kHz XTAL
t1 t2t4t3
t1 = 20ms
t2 = 200ms
t3 = 500us
t4 = 20ms
Figure 2: UEM start-up sequence from reset to power-on mode
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NHP-2
9. TroubleshootingPAMS Te chnical Documentation
Troubleshooting
First, carry out a thorough visual check of the module. Make sure that:
- there are no mechanical damages
- solder joints are OK
Before changing anything, ALL SUPPLY VOLTAGES AND SYSTEM CLOCK / SLEEP CLOCK
should be checked.
Power up faults
Power-up sequence
UEM acts as a HW master during start up
1VBATT limits: 2.1V for internal state machine, 3V triggering whole startup
2Regulator sequencing
•Hw "core" regulators "on": VANA, VIO, VFLA SH1, VFLASH2, and
VCORE, which provide nominal voltages and curre nts according to
Table 1.
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PAMS Technical Documentation9. Troubleshooting
Table 1: Baseband regulators
Maximum
Regulator
VCORE (dc/dc)3001.5Output voltage selectable 1.0V/1.3V/1.5V/1.8V.
VIO1501.8Always enabled, except during power-off mode.
VFLASH1702.78Always enabled, except during power-off mode.
VFLASH2402.78Enabled only when data cable is connected.
VANA802.78Enabled only when the system is awake. (Off
current
(mA)
Vout (V)Notes
Power-up default: 1.5V
during sleep mode and power-off mode.)
•UEM supplies voltages VR1A, VR1B, VR2, VR3, VR4, VR5, VR6,
and VR7 for RF. See Table 2.
Table 2: RF regulators
Maximum
Regulator
VR1A104.75Enabled when receiver is on.
VR1B104.75Enabled when transmitter is on
VR21002.78Enabled when transmitter is on
VR3202.78Enabled when SleepX is high
VR4502.78Enabled when receiver is on
VR5502.78Enabled when receiver is on
VR6502.78Enabled when transmitter is on
VR7452.78Enabled when receiver is on
current
(mA)
Vout (V)Notes
3Reset releasing delay
•Supply voltages stabilize to their UEM hw default value
•RFCLK grows to full swing
• Core is ready to run but waiting for PURX release
4Reset releasing
•UPP releases the SLEEPX up to "non sleep" -state to prevent the
UEM switching the regulators "OFF"
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9. TroubleshootingPAMS Te chnical Documentation
5MCU starts running the Bootsrap Code
•written in stone/ UPP internal ROM
•the program checks if there exists any reason for FDL mode (Flash
Down Load)
•If there exists executable code in FLASH and there exists no reason
for FDL, the MCU starts running the MCU pro gram from FLASH.
6MCU runs the FLASH MCU code the phone initialization, user interfaces, internal
blocks, etc.
•Core regulator voltage setting for required DSP speed
• Initializes the DSP and concerning hw
Releases DSP reset -> DSP starts running
1Power key pressed
•After 20ms, UEM enters RESET MODE if VBAT>Vmstr+
•VFLASH1, Vana, Vcore, Vio, and VR3 goes high.
•VCTCXO enabled by VR3 -> RFClk 19.44 MHz running.
2Purx released
•Purx released by UE M , U EM IN T go es high for 100 ms , Sle epX goes
high and SleepClk (32 KHz) starts running.
3Software running
•Default value of V core is 1.5 V.
•Cbus (1.2MHz) and Dbus (9.6MHz) clocks start running.
Note! In case of power up faults, it's not possible to force phone on by disabling watchdog. Instead it's
recommended to use normal or single triggering on oscilloscope, so that it's possible to see if signal
goes to its normal value even for a while when power key is pressed.
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PAMS Technical Documentation9. Troubleshooting
Phone is totally dead
Phone is dead
-If current is zero, check X101 solder and VBATT lines
-If current is too high, check for shorts
-Make sure all BB regulators are at their respective
voltage levels (e.g. , VANA, VIO, VCORE (DC-DC),
VFlash1, and VR3. See phone's top view diagram for
Yes
Phone current is zero
or too high?
test points
-Make sure the System Clk is 19.2 MHz and that the
Sleep Clk is 32 KHz
-Make sure PURX and SleepX signals are high (1.8V)
The flash programming equipment is connected to the baseband using test pads for galvanic connection. Test pads are allocated in such a way that they can be accessed when
the phone is assembled. The flash programming interface uses the VPP, FBUSTX, FBUSRX,
MBUS, and BSI connections for connection to the baseband. The connection is through
the UEM, which means that the logic levels correspond to 2.7V. Power is supplied using
the battery contacts.
Baseband power is controlled by the flash prommer in production and in reprogramming
situations. When supply voltage is applied to the battery terminals, the baseband will
power up.
Flash programming procedure
•Phone communicates with prommer via production test pattern, using
signals:
FBUSTX (serial data to phone),
FBUSRX (Serial data from phone),
MBUS (serial clock for FBUSRX)
VPP (External flashing voltage for speed up flashing)
Also BSI line is used when initializing flashing(battery connector)
•When phone has entered flash programming mode, prommer indicates
to UEM that flash programming will take place by writing 8-bit password
to UEM. Prommer will first set BSI to “1” and then uses FBUSRX for
writing and MBUS for clocking. After that, BSI is reset to “0”.
•MCU indicates to prommer that it has been noticed, by using the
FBUSTX signal. After this, it reports UP P type ID and is ready to receive
secondary boot code to its internal SRAM.
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NHP-2
X
rn
n
PAMS Technical Documentation9. Troubleshooting
FLASH_1
CH1 = BSI
CH2 = MBUS
CH3 = FBUSTX
CH4 = FBUSR
Measure points
Production test patte
(J396)
Figure 3: Flashing start
•This boot code asks MCU to report prommer phone’s configuration
information, including flash device type. Now, the prommer can select
and send algorithm code to MCU SRAM (and SRAM/Flash self-tests
can be execut ed).
FLASH_2
CH1 = PURX
CH2 = MBUS
CH3 = FBUSTX
CH4 = FBUSRX
Measure points
Production test patter
(J396)
Figure 4: Flashing, continued
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NHP-2
9. TroubleshootingPAMS Te chnical Documentation
FLASH_3
CH1 = PURX
CH2 = MBUS
CH3 = FBUSTX
CH4 = FBUSRX
Measure points
Produ c tio n te s t pattern
(J396)
Data transfer has
started (Fbus_Rx)
Figure 5: Flashing, continued
Flash programming error codes
•Error codes can be seen from the test results or from Phoenix's flashtool*
•Underlined note means that the connection un der consid eration is being
used for the first time.
•Some error codes may be added later. Here are the most common
ones.
Table 3: Flash programming error codes
ErrorDescriptionNot working properly
C101
C102
"The Phone does not set FbusTx line high after the startup." Vflash1
VBatt
BSI and FbusRX from prommer to UEM.
FbusTx from UPP->UEM->Prommer(SA0)
"The Phone does not set FbusTx line low after the line has
been high. The Prommer generates this error also when the
Phone is not connected to the Prommer."
PURX(also to Safari)
VR3
Rfclock(VCTCXO->Safari->UPP)
Mbus from Prommer->UEM>UPP(MbusRx)(SA0)
FbusTx from UPP->UEM->P rommer(SA 1)
BSI and FbusRX from prommer to UEM.
C103
C104
" Boot serial line fail."Mbus from Prommer->UEM-
>UPP(MbusRx)(SA1)
FbusRx from Prommer->UEM->UPP
FbusTx from UPP->UEM->Prommer
"MCU ID message sending failed in the Phone."FbusTx from UPP->UEM->Prommer
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PAMS Technical Documentation9. Troubleshooting
C105
C106
C107
C586
C686
Cx81
Cx82
A204
Cx83
Cx84
Cx85
"The Phone has not received Secondary boot codes length
bytes correctly."
"The Phone has not received Secondary code bytes correctly."Mbus from Prommer->UEM-
"The Phone MCU can not start Secondary code correctly."UPP
"The erasing status response from the Phone informs about
fail."
"The programming status response from the Phone informs
about fail."
"The Prommer has detected a checksum error in the message,
which it has received from the Phone."
"The Prommer has detected a wrong ID byte in the message,
which it has received from the Phone."
" The flash manufacturer and device Ids in the existing Algorithm files do not match with the Ids received from the target
phone."
"The Prommer has not received Phone acknowledge to the
message."
"The Phone has generated NAK signal during data block transfer."
"Data block handling timeout"
Mbus from Prommer->UEM>UPP(MbusRx)
FbusRx from Prommer->UEM->UPP
FbusTx from UPP->UEM->Prommer
>UPP(MbusRx)
FbusRx from Prommer->UEM->UPP
FbusTx from UPP->UEM->Prommer
Flash
Flash
FbusTx from UPP->UEM->Prommer
FbusTx from UPP->UEM->Prommer
Flash
UPP
VIO/VANA?
Signals between UPP-Flash
Mbus from Prommer->UEM>UPP(MbusRx)
FbusRx from Prommer->UEM->UPP
FbusTx from UPP->UEM->Prommer
Cx87
Startup
for
flashing
"Wrong MCU ID."RFClock
UPP(Vcore)
Required startup for flashingVflash1
VBatt
Issue 1 05/2002Nokia Corporation Page 17
NHP-2
9. TroubleshootingPAMS Te chnical Documentation
Flash programming
Flash faults
Phone does not set
Flashbus TXD line high
after start up
No
Measure BSI pulse during
Flash programming.
Yes
Measure FBusRx (2.78V)
signal during flash
programming from bottom
connector and test point
J412 (1.8V).
Is it the same?
Measure test point J411
(1.8V) and FBusTx signal
(2.78V) during flash
programming from bottom
connector.
Are they the same?
Is it OK?
Yes
Yes
No
No
No
Check BSI line X101, C230,
R206, C109, R202
Check R102, C103, and
R104.
If OK, then Change UEM.
Change UPP
No
Is there a pulse on J411?
Phone does not set
Flashbus TXD line low after
the line has been high
No
Change UEM
Yes
Measure MBus (2.78V) and
test point J410 (1.8V).
Are they the same?
Yes
Is pulse getting to test point
Yes
J410?
Change UEM
Yes
No
Is there a pulse on
FBusTx?
No
Check R100 and C101.
If OK, then change UEM.
No
Check R101 and C104
No
Is pulse getting to UEM?
Yes
Page 18Nokia Corporation Issue 1 05/2002
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