Nokia 636, 638 Service Manual 2syst
After Sales Technical Documentation
NHA–2 Series Transceiver
Chapter 4
SYSTEM MODULE
Original 06/97
NHA–2
After Sales
System Module
CHAPTER 4 – SYSTEM MODULE
Contents
Introduction Page 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Technical Specifications Page 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modes of Operation Page 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External and Internal Connections Page 4–5. . . . . . . . . . . . . . . . . . . . . .
Bottom Connector Page 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Display Connector Page 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Baseband Block Description Page 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Circuit Description Page 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microcontroller Page 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input/Output Ports of MCU Page 4–9. . . . . . . . . . . . . . . . . . . . . . . .
A/D Converter of MCU Page 4–13. . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCU SLEEP Mode Operation Page 4–15. . . . . . . . . . . . . . . . . . . . .
Audio Page 4–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NASTA RX Signal Paths Page 4–16. . . . . . . . . . . . . . . . . . . . . . . . . .
NASTA TX Signal Paths Page 4–16. . . . . . . . . . . . . . . . . . . . . . . . . .
User Interface Page 4–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Page 4–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Circuit Operation Page 4–18. . . . . . . . . . . . . . . . . . . . . . . . . .
MBUS Hardware Description Page 4–19. . . . . . . . . . . . . . . . . . . . . . . .
ESN Description Page 4–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Technical Documentation
RF Block Description Page 4–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver Page 4–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX Synthesizer Page 4–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX Loop Filter Page 4–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX VCO Page 4–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Synthesizer Page 4–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX VCO Page 4–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Loop Filter Page 4–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitter Page 4–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Regulators Page 4–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connections between RF and BB Sections (Version: 6.0 Edit: 42) Page 4–24. .
Block Diagram of Baseband Page 4–25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram of NASTA Page 4–26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram of MUUMI Page 4–27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram of Baseband Power Distribution Page 4–28. . . . . . . . . . . . .
JR4: Circuit Diagram of Baseband Section (Version:12 Edit:134) Page 4–29. . .
Page 4–2
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Technical Documentation
JR4: Circuit Diagram of Baseband Section (Version:13 Edit:140) Page 4–30. . .
JR4: Circuit Diagram of MCU & EEPROM (Version:12 Edit: 95) Page 4–31
JR4: Circuit Diagram of MCU & EEPROM (Version:13 Edit: 99) Page 4–32
JR4: Circuit Diagram of Audio (Version:12 Edit: 144) Page 4–33. . . . . . . .
JR4: Circuit Diagram of Audio (Version:13 Edit:159) Page 4–34. . . . . . . . .
JR4: Circuit Diagram of Power Supply (Version:12 Edit:128) Page 4–35. .
JR4: Circuit Diagram of Power Supply (Version:13 Edit:129) Page 4–36. .
JR4: Circuit Diagram of User Interface (Version:12 Edit: 89) Page 4–37. .
JR4: Circuit Diagram of User Interface (Version:13 Edit:89) Page 4–38. . .
Block Diagram of RF Section Page 4–39. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Distribution Diagram of RF Section Page 4–40. . . . . . . . . . . . . . . . . .
JR4: Circuit Diagram of RF Section (version 12) Page 4–41. . . . . . . . . . . .
JR4: Circuit Diagram of RF Section (version 13) Page 4–42. . . . . . . . . . . .
System Module
JR7: Circuit Diagram of RF Section (version 13) Page 4–43. . . . . . . . . . . .
JR4: Layout Diagrams (version 12) Page 4–44. . . . . . . . . . . . . . . . . . . . . . . .
JR4: Layout Diagrams (version 13) Page 4–45. . . . . . . . . . . . . . . . . . . . . . . .
JR7: Layout Diagrams (version 13) Page 4–46. . . . . . . . . . . . . . . . . . . . . . . .
JR7: Circuit Diagram of Baseband Section (Version:13 Edit:140) Page 4–47. . .
JR7: Circuit Diagram of MCU & EEPROM (Version:13 Edit: 98) Page 4–48
JR7: Circuit Diagram of Audio (Version:13 Edit: 159) Page 4–49. . . . . . . .
JR7: Circuit Diagram of Power Supply (Version:13 Edit:129) Page 4–50. .
JR7: Circuit Diagram of User Interface (Version:13 Edit: 89) Page 4–51. .
Part List of JR4 (Code: 0200613, Issue: 9.12) Page 4–52. . . . . . . . . . . . . .
Part List of JR4 (Code: 0200613, Issue: 13.0) Page 4–65. . . . . . . . . . . . . .
Part List of JR7 (Code: 0200843, EDMS Issue:13.0 ) Page 4–74. . . . . . . .
Original 06/97
Page 4–3
NHA–2
After Sales
System Module
Introduction
System module is designed to operate in handportable phone in AMPS system.
Baseband hardware is integrated to same printed circuit board with RF hard-
ware. Module includes modem, audio filters, microcontroller, power supply, non-
volatile memory, keyboard and display. Display is a different module. The mo-
dem and audio operations is integrated to NASTA ASIC. Power supply circuits
like regulators, voltage detection and charging control are integrated to custom
MUUMI circuit. The microcontroller is a Hitachi H8 series controller with mini-
mum 60–64 kbytes ROM and 2 kbytes RAM. The 2 kbyte nonvolatile EEPROM
memory is a serial IIC–bus type device. This custom EEPROM includes also 16
bytes one time programmable (OTP) part for electrical serial number (ESN)
The display is a 5*7 dot matrix, 2 line liquid crystal display with single chip con-
troller IC with negative voltage generation for LCD and RF VCOs.
Technical Specifications
Technical Documentation
Modes of Operation
The system module hardware module has 4 basic operation modes: active
(call), standby (service) and power off.
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Technical Documentation
External and Internal Connections
The system module has two connector, external bottom connector and internal
display module connector.
Bottom Connector
14
13
15
System Module
16
S0001130
Accessory Connector
Pin: Name: Description:
1 GND Digital ground
2 V_OUT Battery voltage out
3 XMIC External microphone input and accessory
4 NC No connection
5 NC No connection
6 MBUS Bidirectional asynchronous bus
7 NC No connection
7
12
17 20
16
• min/typ/max: 3.25...4...6 V (load 3 mA)
identification
• min/max: 0...VA+1.0 V
• logic low level: 0...05 V
• logic high level: 2.4...3.5 V
1918
8 SGND Signal ground
9 XEAR External audio output and mute control
Original 06/97
• mute on: 0...0.5 V d.c.
• mute off: 1.0...2.0 V d.c.
Page 4–5
NHA–2
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System Module
Pin: Name: Description:
10 HOOK Hook control, accessory connection detect
11 NC No connection
12 VIN Charging voltage input
Battery Connector
Pin: Name: Description:
13 GND Battery ground
14 BSI Battery size indicator
15 BTEM Battery temperature
Technical Documentation
• hook off (handset in use) : 0...05 V
• hook on, (handset not in use): 2.4...3.5 V
• max: 16 V
• R2=47k pullup resistor in
module
• 47 kΩ NTC in battery to gnd,
47 kΩ pullup in module
16 VBAT Battery voltage
Charging connectors
Pin: Name: Description:
17, 19 VC Charging voltage input
18, 20 GND Charger ground
• min/typ/max: 4.0...4.8...8.0 V
• min/max: 4...16 V
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Technical Documentation
Display Connector
1
S0001113
Pin: Name: Description:
1, 15 VBAT Battery voltage
System Module
9
16
8
• voltage min/typ/max: 4.2...4.8...6.8 V
• illumination current typ/max: 20...40 mA
2 LIGHTS Display illumination control
• lights on voltage typ/max: 1.4...1.75 V
• drive current typ/max: 100...200 µA
3 LCDCLK Display controller clock input
• 80 kHz/0...3.5 V
4, 16 GND Ground
5 –VOUT Negative voltage out
• voltage min/typ/max: –6.0...–6.6...–7.0 V
• max load current: 50 µA
6 VL Supply voltage to controller
• voltage min/typ/max: 3.1...3.3...3.5 V
• loading current typ/max: 1.4...1.5 mA
7 _RESET Controller reset input
• low/high voltage: 0.6 V/2.8 V
8 RS Register select
• low/high voltage: 0.6 V/2.8 V
9 R/W Read/write select
• low/high voltage: 0.6 V/2.8 V
10 E Enable controller bus
11–14 DB0–DB3 Controller 4–bit data bus, DB4=MSB
Original 06/97
• low/high voltage: 0.6 V/2.8 V
• low/high voltage: 0.6 V/2.8 V
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System Module
Baseband Block Description
Circuit Description
The module consists of following main components:
– H8/3042 16–bit single chip microcontroller with 64 kbytes ROM (EPROM)
and 2 kbytes RAM
– NASTA modem and audio ASIC
– External audio amplifier with on/off control and buzzer driver circuit
– MUUMI power supply (and control), ASIC and discrete charge switch control
logic
– serial I2C–bus 2 kbytes EEPROM with 16 bytes one time programmable
electrical serial number (ESN) area
– NJU6428 LCD controller with 2* VL negative voltage generation is located in
the separate display module
The baseband block diagram illustrates the baseband module connections and
interface to charger, battery and display module.
Technical Documentation
Microcontroller
NHA–2 microcontroller is a H8/3042, that is operating in single–chip normal
mode (mode 6) 64 kbyte address space. Maximum 62 kbytes ROM can be
used for program. MCU operating clock (=2.4 MHz) is generated on NASTA.
Microcontroller includes 2 serial channels, 5 pcs 16–bit timer units(ITU) with
PWM and interval capability, 10–bit A/D–converter with 8 channels, watchdog
timer and refresh timer. Serial channel 0 is used for asynchronous M2BUS–
communication and channel 1 is used for synchronous synthesizer interface.
Four timer units are used for pulse width modulation (PWM) outputs: buzzer
control(BUZZ_DRIVE) ITU0, charge control (CSWPWM) ITU1, TX power control (TXC) ITU2 and TX booster power control (BENA) ITU3. M2BUS net free
interrupt reserves one timer unit ITU4. Keyboard interface reserves 10
I/O–lines: 4 column outputs (COL3–0) and 6 row inputs. Different power on/off
switch is connected through MUUMI circuit to MCU input PWRON.
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Technical Documentation
Input/Output Ports of MCU
All input/output pins are used as I/O–ports. NASTA address and data bus is
connected to I/O–pins.
Port 1
Pin name Pin use description
P10/A0 NA0, NASTA address bus ,output
P11/A1 NA1, NASTA address bus ,output
P12/A2 NA2, NASTA address bus ,output
P13/A3 NA3, NASTA address bus ,output
P14/A4 NCS
P15/A5 NRD, NASTA read control output
P16/A6 NWR, NASTA write control output
P17/A7
Port 2
Pin name Pin use description
System Module
, NASTA chip select control output
Port 3
P20/A8 ROW0, Keyboard matrix row input 0 (input pullup used)
P21/A9 ROW1, Keyboard matrix row input 1 (input pullup used)
P22/A10 ROW2, Keyboard matrix row input 2 (input pullup used)
P23/A11 ROW3, Keyboard matrix row input 3 (input pullup used)
P24/A12 ROW4, Keyboard matrix row input 4 (input pullup used)
P25/A13 ROW5, Keyboard matrix row input 5 (input pullup used)
P26/A14 PWRON, buffered power on key input (=1 when PWR–
key pressed)
P27/A15 LIGHTS, Keyboard and display illumination on/off=1/0
control output
Pin name Pin use description
P30/D8 ND0, NASTA data bus,I/O
P31/D9 ND1, NASTA data bus,I/O
P32/D10 ND2, NASTA data bus,I/O
P33/D11 ND3, NASTA data bus,I/O
P34/D12 ND4, NASTA data bus,I/O
P35/D13 ND5, NASTA data bus,I/O
P36/D14 ND6, NASTA data bus,I/O
P37/D15 ND7, NASTA data bus,I/O
Original 06/97
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Port 4
Pin name Pin use description
P40/D0 SLE, Synthesizer latch enable
P41/D1 unused output
P42/D2 TXE, Transmitter regulator on/off=1/0 control
P43/D3 TXS, Transmitter synthesizer on/off control
P44/D4 RXV0, RX VCO aligning output
P45/D5 RXV1, RX VCO aligning output
P46/D6 RXV2, RX VCO aligning output
P47/D7 SLD, synthesizer lock detect input, internal pullup used
Port 5
Pin name Pin use description
P50/A16 COL0, Keyboard column output 0
P51/A17 COL1, Keyboard column output 1
P52/A18 COL2, Keyboard column output 2
P53/A19 COL3, Keyboard column output 3
Technical Documentation
(pullup used, when input)
(pullup used, when input)
(pullup used ,when input)
(pullup used ,when input)
Port 6
Pin name Pin use description
P60/WAIT DB0, LCD controller data bus,I/O
P61/BREQ DB1, LCD controller data bus,I/O
P62/BACK
P63/AS DB3, LCD controller data bus,I/O
P64/RD E, LCD controller bus enable control output
P65/HWR
P66/LWR RS, LCD controller register select control output
DB2, LCD controller data bus,I/O
R/W, LCD controller bus read/write control output
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Technical Documentation
Port 7
Pin name Pin use description
P70/AN0 VBSW, Battery (VBAT) voltage measurement input
P71/AN1 VCSW, Charger voltage measurement input
P72/AN2 BSI, Battery size indication
P73/AN3 BTEMP, Battery temperature measurement
P74/AN4 RSSI, Receiver Signal Strenght Indication
P75/AN5 TXI, Transmitter power indication
P76/AN6 RFTEMP, RF temperature measurement
P77/AN7 XMIC, external audio and accessory identification input
Port 8
Pin name Pin use description
System Module
(10–bit resolution)
HEADSET ADAPTER connected: 602 nominal
(685...505 accepted), Compact HF connected:
410 nominal (504...324 accepted )
Port 9
P80/RFS/IRQ0 NINT, Interrupt from NASTA
P81/CS3
P82/CS2
P83/CS1/IRQ3 unused output
P84/CS0
Pin name Pin use description
P90/TxD0 MBUS out
P91/TxD1 SDATA,Synthesizer serial data output
P92/RxD0 MBUS in
P93/RxD1 SDA, serial EEPROM IIC–bus data
P94/SCK0/IRQ4
P95/SCK1/IRQ5 SCLK, serial data clock output to synthesizers
/IRQ1 HOOK, HOOK on=1/off=0 status, accessory
connect interrupt (falling edge)
/IRQ2 EXT_RF, 0=external antenna in use, input
(not used in C1, configure as output)
unused output
SCL, serial EEPROM IIC–bus clock
Original 06/97
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System Module
Port A
Pin name Pin use description
PA0 XEARON, external audio amplifier on/off=1/0 and hands
PA1/TCLKB LCDCLK, 80 kHz clock input for slow clock PWM to timer
PA2/TIOCA0 BUZZ_DRIVE, Buzzer drive output from timer unit 0, level
PA3/TIOCB0 unused output
PA4/TIOCA1 CSWPWM, Charger PWM control output (Timer unit 1)
PA5/TIOCB1 XPWROFF, Power off and watchdog clear control output,
PA6/TIOCA2 TXC, Transmitter power control PWM output (Timer unit 2)
PA7/TIOCB2 RXV3, RX VCO aligning output
Port B
Pin name Pin use description
Technical Documentation
free mute (on=0) control
unit 1
adjust with PWM
watchdog cleared on falling edge
PB0/TP8/TIOCA3 BENA, TX booster power control PWM output
(not used in C1 product)
PB1/TP9/TIOCB3 ABC/PWR key input, =0 when ABC/PWR key pressed
PB2/TP10/TIOCA4 unused output
PB3/TP11/TIOCB4 MBUSNF, MBUS net free timer input (Timer unit 4)
PB4/TP12/TOCXA4 unused output
PB5/TP13/TOCXB4 unused output
PB6/TP14 unused output
PB7/TP15 unused output
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Technical Documentation
A/D Converter of MCU
A/D converter has 10 bit resolution with ±8 LSB absolute accuracy and 3.3 V
±3% reference voltage input. All 8 analog inputs can be multiplexed to A/D con-
verter input. The A/D conversion time is 134 CPU clock cycles maximum
(CKS=1) and input sampling time is 40 clock cycles.
Description of Input Channels
Channel 0: WBSW, Battery Voltage Measurement
Battery voltage can be measured from 4 V to 9.075 V nominal with 3.3 V reference voltage. The absolute accuracy is low because of the reference 3 % accuracy and A/D converter ±8 LSB accuracy. This battery voltage measurement
offset error must be calibrated with input voltage 4.8 V. The A/D conversion result can be calculated from equation:
A/D readout = 1024 * (VBSW* ( 4/11))/VREF VREF=3.3 V
For example (voltage, min/nom/max A/D value):
4.3 V 456...484...515 cutt off limit/idle
4.8 V 509...541...575 battery voltage reference trim
6.8 V 722...767...815 high battery charging voltage limit
System Module
Channel 1: VCSW, Charger Voltage Measurement
Charger voltage can be measured up to 21.6 V nominal. The A/D conversion
result can be calculated from equation:
A/D readout = 1024 * (VCSW*(18/118))/VREF VREF=3.3 V
For example:
4.8 V 198...227...257 Charger voltage reference trim
10 V 413...473...536 –
11 V 661...757...859 Max charger voltage
Channel 2: BSI, Battery Size Indication
Battery capacity can be defined with BSI resistor value calculated from equation:
BSI = 47 kΩ / ((4 mAh * 1023)/ C) –1)
A/D readout gives battery capacity from equation:
A/D readout = C/4 C= Battery capacity
For example:
470 mAh/6.8 kΩ 121...129...137
950 mAh/15 kΩ 235...247...261
1.2 Ah/20 kΩ 291...305...321
1.6 Ah/30 kΩ 382...398...416
Original 06/97
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System Module
Channel 3: BTEMP, Battery Temperature Measurement
Battery temperature measurement is implemented with 47 kΩ NTC and 47 kΩ
pullup resistor. The A/D conversion readout can be calculated from equation:
A/D readout= 1024* ( R
NTC
/( R
NTC
+47kΩ))
For example:
5 °C 705...743...780
25 °C 486...512...537
45 °C 289...305...320
Channel 4: RSSI, Receive Signal Strength
Receiving signal strength is proportional to input voltage / A/D–readout.
Typical value for noise level signal strength is 0.2 V = 0062= 03E H and for
maximum signal strength is 2.4 V = 0744 = 2E8 H. Input value for –90 dBm RF
input level is typically 1.16 V= 0360 = 168 H . RF input level change of 1 dBm
equals about 24 mV= 7.5 A/D steps.
Channel 5: TXI, Transmitter Power Level Indication
Transmitter power level indication is used to monitor the transmitted power level. A/D input is used to check, if TX power is on or off. The limit for check is
1.0 V, which is equal to 320 as A/D readout.
Technical Documentation
Channel 6: RFTEMP, RF VCXO Temperature Measure
VCXO module temperature measurement is based on CMOS temperature sensor chip with linear – 8.1 mV/K voltage output. The nominal output voltage of
sensor IC is at +30 °C 1.497 V. One degree temperature change is equal to 2.5
A/D quantisize steps.
For example:
–20 °C 549...589...636
+30 °C 429...464...508
+80 °C 304...336...376
Channel 7: ID, Accessory Identification Input
Accessory identification is included in XMIC signal d.c. voltage level = ID analog input. This d.c. voltage level is defined by pullup resistor. Compact HF unit
and headset adapter can be recognized from this input:
Compact HF unit 324...409...504 22 kΩ pulldown resistor
Headset adapter 505...601...685 47 kΩ pulldown resistor
LCD controller interface to microcontroller is a 4–bit parallel type including 4 bidirectional data lines DB3–0 (port 63–60), register select control RS (port 66)
output, read/write control R/W (port 65) output and bus enable control E (port
64) output. Data lines DB3–0 and control signals RS ,R/W must be set to high
state during standby operation because of the pullup resistors in LCD controller. LCD controller resetting requires clock during _RESET active low . This
clock is created with LCD controller internal RC–oscillator changing LCDCLK
output from NASTA to 3–state.
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Technical Documentation
Interface between microcontroller and NASTA circuit is bidirectional 8–bit parallel type with 4 address lines. Address, data and control lines are used in microcontroller as I/O–port pins. Data lines direction must be controlled with microcontroller data direction register. Interface includes address outputs NA3–0
(port 1), data inputs (read) / outputs (write) ND7–0 (port 3), chip select control
output NCS
NWR (port 16) and interrupt input NINT (port 80) . If NASTA circuit is not selected , control signals (read,write and chip select) must be in high state and
data lines must be outputs.
The serial I2C–bus interface EEPROM is connected to MCU I/O–pins:
SDA (serial data) to port 93 and SCL (serial clock) to port 94.
MCU SLEEP Mode Operation
Microcontroller is driven to sleep mode by software in order to save power. In
sleep mode all I/O–pins,RAM and CPU registers are held. Timers, clock and
supporting functions are active. MCU exits from sleep mode by interrupt: NASTA modem interrupt, MBUS serial communication interface interrupt (SCI 0) or
operating system timer interrupt (refresh controller timer).
(port 14), read control output NRD (port 15) , write control output
System Module
Audio
The main audio and modem operations are included in NASTA ASIC circuit.
NASTA includes following operations:
– AMPS/TACS modem with extended standby operation
– all RX/TX audio filters, compander, limiters, mute switches
– microphone amplifier, ceramic earpiece amplifier, accessory audio output
(XEAR) and input (XMIC).
– DTMF generator.
– IF counter and 8–bit D/A–output for AFC control
– voltage controlled oscillator and clock generation
The NASTA circuit is connected to MCU with 8–bit parallel bus and interrupt request line.
The 14.85 MHz clock input is generated in RF module voltage controlled crystal
oscillator (VCXO). This input clock is used to synthesize 4.8 MHz clock to NASTA internal circuits. NASTA creates 2.4 MHz clock to microcontroller
(CLKMCU) and 80 kHz clock to LCD controller. The buzzer driver amplifier is
driven by MCU PWM output. The buzzer volume level is adjusted with pulse
width. The accessory audio output line XEAR is driven by transistor pair (V53)
buffer. The buffer is short circuit protected with 47 ohm series resistor and has
on/off (mute) control from MCU output (XEARON). This XEAR buffer amplifier
outputs more than 1.6 V DC voltage to control accessory audio to mute off
state. Accessory audio input XMIC is connected also with low pass filter (R52
and C70) to MCU A/D–converter input. This accessory identification input (ID)
is used to recognize the connected accessory type and check, if accessory is
connected or not.
Original 06/97
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NASTA RX Signal Paths
The incoming audio, data and SAT (Supervisory Audio Tone) analog signal
(DAF = N2 pin 27) is connected through the RX trimmer and the anti alias filter
to modem data comparator input, to 6 kHz bandpass type SAT filter input and
to receive audio filter.
The data from the anti alias filter is connected through the comparator to a
Manchester decoder, which decodes Manchester data to the NRZ (Non Return
to Zero) format.Modem is synchronized to the receiving data with a digital
phase locked loop and a word synchronization detection block. Data validity is
continuously detected, and this information is used internally when word synchronization detection is accepted.The serial data from the Manchester decoder is 3/5 majority voted, BCH–decoded, corrected and shifted to receiver register. The Receiver timing block extracts the data from received frames on control
and voice channels and generates data transfer interrupts . It maintains bit and
word synchronization during different frames and passes the synchronization
status forward to the status register.
The SAT signal is filtered and amplified with a bandpass filter . Signal is converted to digital square wave signal with a comparator .SAT detection is done
with a digital PLL/detection circuitry. The regenerated SAT is then fed to transmit summing block.
Technical Documentation
RX audio signal is selected with the input mux. Other possibilities is to select
DTMF or RX mute. RX audio signal is filtered with a de–emphasis and bandpass filter. Signal is fed through amplitude expander 1:2 (EXP). RX volume level is controlled with amplifier in the range –20 ... +17.5 dB.Hands free control
block includes a bandpass filter, window comparator and controller for RX TX
attenuators. RX hands free attenuator has selectable minimum gain from
–30...–21 dB to max 0 dB. RX and TX attenuation sum is always constant at HF
use (30...21 dB). Side tone is added to earphone signal. The audio signal is fed
either to earphone amplifier output (EARM, EARP) or to accessory audio amplifier output (XEAR).
NASTA TX Signal Paths
The data to be transmitted will be loaded into the transmitting data register.
From the transmit data register the 8 bit data is transformed to serial data which
is fed to the Manchester encoder and then to the summing block output (MOD,
N2 pin 55).
Microphone signal is fed to microphone amplifier input (MIC, N2 pin 43). NASTA has a control for microphone bias current output (BIMIC, N2 pin 44). Signal
source can be selected with the input multiplexer: microphone, accessory input
(XMIC, N2 pin 46) or internal dtmf generator. TX hands free attenuator has selectable minimum gain from –30...–21 dB to maximum 0 dB. Signal is going to
trimmer, which is tuned for nominal speech deviation or DTMF level. Signal is
filtered in the TX audio bandpass filter.
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Technical Documentation
Signal is fed through amplitude compressor 2:1 to the first limiter for low frequency amplitude limiting. Signal is then pre–emphasised and limited again.
Signal is lowpass filtered and fed to trimmer for speech maximum deviation tuning. It is fed to the TX summing block to be summed with data, ST and SAT
signals.
DTMF generator generates dual and single tones for RX and TX lines. Tolerance of DTMF frequencies is ±1.5 %.
User Interface
The user interface includes interface to display module and keyboard with illumination. The display module is connected with 16 pin connector. The display
module interface includes 4 bit data bus (DB(3:0)), bus enable (E), read/write
(R_W), register select (RS), reset (_RESET) and 80 kHz clock input to LCD–
controller (LCDCLK). The keyboard illumination includes 12 LEDs and 2 transistor(V42, V43) drivers. Keyboard consists of 6*4 matrix and different ABC/
PWR–key and PWR–switch. The keyboard interface to microcontroller includes
4 column outputs from MCU (COL(3:0)), 6 row inputs (ROW(5:0)), ABC/PWR–
key input (ABCKEY) and PWR–switch input (PWRON).
System Module
Power
Module goes to power on state always, when either ABC/PWR–key or PWR
switch is pressed. The software decides, if ABC/PWR–key is active power key
or not. This and other key variations is defined by software.
The baseband power supplying circuit MUUMI includes:
– 3 pcs 3.3 V regulated outputs
– VL = Logic voltage for digital circuits
– VA = Analog voltage for analog circuits
– VREF = Reference voltage for A/D converter and RF regulator
– switched outputs of battery (VBSW) and charger voltage (VCSW)
measurement to MCU A/D–converter
– battery voltage detection and reset logic
– charger switch control output used to limit battery voltage VBAT < 8.0V
– power on/off switch input (XPWRON), buffered output to MCU (PWRON)
– watchdog timer using oscillator in COFF pin, cleared by falling edge input in
PWROFFX, elapsing time for WD timer is 1...3 seconds
– M2BUS open drain output driver
The charge switch driving circuit is implemented with discrete components. This
circuit includes transient voltage protection, soft charge switching, low voltage
battery charging and battery disconnecting with charger connected protection.
This circuit also limits battery voltage when charger is connected to protect
MUUMI and TX transistors.
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System Module
Power Circuit Operation
NHA–2 power circuitry have three different operating modes: POWER OFF,
RESET and POWER ON. In POWER OFF state MUUMI regulator outputs are
disabled and reset control output signal (PURX) is active low. MUUMI internal
oscillator at pin COFF is working in all operating modes. MUUMI goes through
short RESET state (100 ms) to POWER ON–state, if PWR–button is pressed or
charger voltage input is connected to charging input VC (charging voltage
detection in MUUMI input VCHAR is level active). In RESET–state regulator
outputs VL, VA and VREF are active and PURX–signal is active low. If battery
voltage VBAT is lower than 4.1 V (3.9 V...4.3 V) the circuit cannot go to POWER
ON state. MUUMI goes also to RESET state, when battery voltage is falling below 3.9 V (3.7 V...4.1 V). This situation is possible, when battery is fully discharged or battery is disconnected.
In POWER ON mode all regulator outputs are active and MUUMI reset signal
output PURX is inactive high. Microcontroller XPWROFF–output signal clears
at falling edge the watchdog inside MUUMI. If the watchdog is not cleared,
MUUMI goes to POWER OFF state. When the charger is connected and battery voltage is higher than 4.1 V, module stays in POWER ON mode.
Technical Documentation
The microcontroller controls battery charging with CSWPWM output and
MUUMI limits the maximum battery voltage to 7.6 V with CHRGSW–output.
No current flows from charger (VC) to battery, if MCU output CSWPWM is active low and _RESET signal is inactive high. The battery is charged also, when
charger is connected and _RESET signal is active low. The charging circuit
charges the battery during RESET to higher than 4.3 V
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Technical Documentation
MBUS Hardware Description
MBUS hardware interface consists of serial communication interface channel
inside MCU, net free timer (MCU), open drain output driver (MUUMI), 4.7 kΩ
pull–up resistor and protection/filtering resistor/capasitors. MBUS voltage levels
are based to 3.3 V supply voltage.
N1 (MUUMI)
M2BUSIN
11
asychronous data
output from MCU
(pin 12)
760k
M2BUSOUT
12
System Module
received data input to
MCU(pin 14) and net
free timer input to MCU
(pin 5)
Bidirectional MBUS
signal to system
connector
ESN Description
The Electrical Serial Number can be programmed only once and cannot be manipulated in the field. The custom EEPROM circuit includes 16 bytes one time
programmable (OTP) part for the ESN. The ESN component is a SO–8 package soldered to main printed circuit board.
The software of the microcontroller is not alterable and cannot even be read,
because of the microcontroller security option. The microcontroller program
memory is either OTP or mask type.
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NHA–2
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System Module
RF Block Description
Receiver
The receiver is a dual–conversion superheterodyne using two intermediate frequencies, 45 MHz and 450 kHz.
The RF signal from the duplexer RX port is applied to the RF amplifier. The amplifier is realized with transistor V700. Amplifier stage input matching is accomplished by C701. R700 and R701 are used for biasing. Output matching is carried out by Z03 and Z04. Components C702 and C703 are used for RF
bypassing. The RF amplifier and the IF circuit are connected in series with
R702 so that the same supply current is passed through both stages.
Next the signal is filtered with Z703. The filter is followed by a single balanced
diode mixer, realized with Z701, Z711, Z712, C709, C716 and V701.
After the mixer the 45 MHz IF signal is filtered with crystal filter Z702. The
matching between mixer and the filter is realized with L706 and C706. Next the
IF signal is amplified by V703. Input matching is realized with C714, L702 and
L705. The biasing is realized with R713, R714 and R710. From the amplifier
the IF–signal is applied to the second mixer.
Technical Documentation
The second mixer, the LO buffer transistor, IF amplifier and quadrature detector
are all integrated in the circuit N700. The second LO frequency, 44.55 MHz, is
third harmonic off the VCXO frequency. LO signal is realized with tank circuit
C719 and L710. After the mixer the 450 kHz IF signal is filtered with ceramic
filter Z704. Between the filter and IF amplifier is a band–pass filter consisting of
C728, L709 and C730. The IF amplifier output signal is phase shifted by resonance circuit C727, C723, R712 and L704. After this the signal is fed to a quadrature detector.
Signal DAF is low pass filtered by R716 and C734. The DAF, RSSI and 2nd IF
signal (450 kHz) are fed to the audio/logic unit.
RX Synthesizer
The first injection frequency is generated by a digital phase locked loop (PLL).
The output frequency of the loop (LO) is obtained from a voltage–controlled oscillator (VCO) V602. The bandwidth of the PLL can be varied by dataword programming. The VCO output signal is amplified by transistor V601 and fed to the
receiver mixer via Z06. The injection level required by the receiver mixer is
about +3 dBm. In addition, the signal is fed to the dualsynthesizer circuit N650
and via R625 to a LO amplifier which is realized with V661.
Page 4–20
The overall divisor of the chain is selected according to the desired channel.
The internal dividers of N650 are programmed with 17 bits, which are trans-
ferred serially on the SDATA (synthesizer data) line from the processor into an
internal shift register also locating in N650. Data transfer is timed with SCLK
clock pulses.
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Technical Documentation
The divided frequency is compared with a highly stable reference frequency by
a phase comparator in the PLL circuit (N650). The phase comparator controls
the VCO frequency by means of a d.c. voltage through the loop filter so as to
keep the divided frequency applied to the phase comparator equal to the fixed
reference frequency.
The reference frequency is 30 kHz. This reference frequency is obtained from
The voltage controlled crystal oscillator (VCXO). The oscillator frequency is
14.85 MHz. The VCXO frequency is divided by 495.
RX Loop Filter
Phase comparator output is pin 3. If the VCO frequency is too high, the output
goes low and discharge integrating capacitor C618. After this, the DC control
voltage and the VCO frequency will decrease.
If the VCO frequency is too low, the output goes high and charge the integrating capacitor C618. Thereafter the DC control voltage and the VCO frequency
will go up.
Output pulses from the phase detector have to be supplied to the loop filter.
The function of the integrator is to convert positive and negative pulses to DC
voltage. The remaining ripple and AC components are filtered in the lowpass
filter. The integrator comprises components R610, C619, C624 and C618. The
lowpass filter consists of R608 and C616.
System Module
RX VCO
The VCO is a Clapp type oscillator. The oscillator’s resonant frequency is determined by the circuitry Z600, C604, V603,C601, C614, C611, C612 and C613.
The center frequency of the VCO is adjusted by changing amount of constant
current generated by V100 in BB section. The VCO signal is amplified by buffer
amplifier V601. This amplifier produces a level of –5 dBm to the synthesizer
N650 and amplifier V661 in TX synthesizer via R625. The same buffer V601
produces +3 dBm level to the first mixer via Z06.
TX Synthesizer
The transmitter synthesizer generates a frequency modulated transmitter signal
for the transmitter section.
The TX offset synthesizer consists of a 90 MHz PLL circuit, passive loop filter
and a 90 MHz VCO equipped with a chip coil resonator. The bandwidth of the
PLL can be varied by dataword programming. Modulation is brought to the
VCO.
The TX signal is obtained by mixing the signals of offset synthesizer and RX
synthesizer with a single balanced diode mixer. From the mixer the –10 dBm
level is fed to the amplifier. The TX signal is filtered with a SAW filter before inputting it to the transmitter.
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NHA–2
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System Module
TX VCO
The VCO is a Clapp type oscillator. The oscillator’s resonance frequency is determined by the circuitry L651, C659, V659, C663, C630, C631 and C675. The
center frequency of the resonance circuit is not adjustable (By increasing or decreasing the capacitor C659 the resonance frequency can be changed). The
VCO signal is amplified by V657 and fed to the prescaler and to the mixer.
TX Loop Filter
Output pulses from the phase detector N650 pin 17 have to be supplied to the
loop filter. The integrator, which is constituted of R674, C680 and C683, converts positive and negative pulses to d.c. voltage. The remaining ripple is filtered in the low–pass filter accomplished by R672 and C665.
Transmitter
The transmitter is realized with four discrete transistors. The modulated RF signal from the TX synthesizer is applied to the input transistor V660 of the transmitter. V660 amplifies the signal for the power control stage V803, which is
biased to B–class. The power level is controlled by the collector voltage of
V803. Transistors V804 and V805 are biased to C–class and amplify the RF
signal to the desired output power level. The amplified RF signal is fed through
a low–pass filter to the duplex filter. The harmonics of the transmitter are reduced by the duplex filter. A voltage proportional to the output power is rectified
from a directional coupler by d.c. biased Schottky diode V801. This rectified
voltage is fed to a differential amplifier which consists of double transistor V809.
There is a negative feedback from the rectified voltage to the bias voltage of
diode V801 consisting of transistor V810 and associated components. The purpose of arranging the feedback is to suppress the rectified voltage to a range
below 3 volts. The reference voltage is filtered from the PWM signal TXC by
R814 and C826. The differential amplifier adjusts the collector voltage of the
transistor V803 so that the reference voltage and the voltage proportional to the
output power are equal. The transmitter is switched on when TXE goes high
(logic 1), which enables the transmitter power control circuit by transistor V808
and the first stage of the transmitter. When the transmitter is inactive (TXE low)
the RF level from the transmitter is reduced below –60 dBm.
Technical Documentation
Page 4–22
The rectified voltage, which is proportional to the power output signal, is fed
along TXI line through R820 to the BB–unit. This TXI line (TX power on Indicator) is used to avoid false transmission.
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Technical Documentation
Regulators
Transistors V901 and V902 form a voltage regulator for RF parts. It is realized
with discrete transistors because the output noise has to be very low. The 3.3 V
reference voltage (VREF) comes from the logic module. This regulated voltage
goes directly to RX part and also to RX synthesizer. TX synthesizer get it’s supply voltage via a switch. The switch is realized with transistors V651 and
V654.It is controlled over digital line TXS from the logic module.
System Module
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Page 4–23
NHA–2
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System Module
Technical Documentation
Connections between RF and BB Sections (Version: 6.0 Edit: 42)
Page 4–24
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Technical Documentation
Block Diagram of Baseband
NASTA
DAF
D/A
IF
CTR
SPEECH
DATA/ST
CLK
DIV
SYNBIAS
RXBIAS
14.85 MHz
MOD
AFC
IF
CTR
CLK
GEN
SAT
DATA
SAT
DET
MAN
DPLL
DEC
MCU INTERFACE
ND0–7,NA0–3
_NCS,_WR,_RD
_NINT
HF
DET
VOTE
SMUX
SMUX
DATA/
ST
ENCODE
System Module
EARPHONE
EAR
XEARON
XMIC
BUZZ_DRIVE
VBAT
XEAR
MIC
MICROPHONE
BUZZER
VC
4.8V
NTC
Battery
pack
–VMOD
TXE,TXS,TXC
SLE,SDATA,SCLK
Charge
switch
control
VBAT
BTEMP
BSI
ON/OFF
VCO
NEG VOLT
TRIM
–VLCD
XEARON
RXV(3:0)
RF CONTROLS
HOOK, EXT_RF
Charger
det,crl
VB det
RESET
PWR ON
WDOG
MUUMI
VBSW
VCSW
BTEMP
BSI
RSSI
TXI
RFTEMP
XMIC/ID
RESET,PWRON
MBUS
2.4MHz
WDOG
TIMER
ITU
16 BIT
TIMERS
INTERRUPT
CONTROL
A/D
10 BIT
8 CH
TXD,XPWROFF
VL=3.3V
VA=3.3V
VREF=3.3V
H8/3042
H8/300
CPU
ROM
64K
RAM
2K
SCL,SDA
EEPROM
2 kbytes
VCSW
VBSW
DMA
REFRESH
CONTRL
TPC,
TIMING
PATTERN CRL
SCI
SERIAL
IFCE
2 CHAN
80 kHz
RS,R/W,E,
DB0–3
LIGHTS
ROW0–5
COM1–7,COM9–15,COMMK
SEG1–60
LCD–
CONTROLLER
KEYBOARD
COL0–3
HOOK
EXT_RF
XEAR
XMIC
ACCESSORY
CONNECTOR
–VLCDout
MBUS
HOOK
EXT_RF
XEAR
XMIC
BENA
V_OUT
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