NEC UPD75P3018GK-BE9, UPD75P3018GC-3B9 Datasheet
DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD75P3018
4-BIT SINGLE-CHIP MICROCONTROLLER
The µPD75P3018 replaces the µPD753017’s internal mask ROM with a one-time PROM, and features expanded ROM
capacity.
Because the µPD75P3018 supports programming by users, it is suitable for use in evaluations of systems in
development stages using the µPD753012, 753016, or 753017, and for use in small-scale production.
The following document describes further details of the functions. Please make sure to read this document
before starting design.
µPD753017 User's Manual : U11282E
FEATURES
Compatible with µPD753017
Memory capacity:
• PROM : 32768 x 8 bits
• RAM : 1024 x 4 bits
Can operate in same power supply voltage as the mask version µPD753017
DD = 2.2 to 5.5 V
• V
LCD controller/driver
ORDERING INFORMATION
Part Number Package PROM (¥ 8 bits)
µ
PD75P3018GC-3B9 80-pin plastic QFP (14 x 14 mm, 0.65-mm pitch) 32768
µ
PD75P3018GK-BE9 80-pin plastic TQFP (fine pitch) (12 x 12 mm, 0.5-mm pitch) 32768
Caution Mask-option pull-up resistors are not provided in this device.
*
The information in this document is subject to change without notice.
Document No. U10956EJ1V0DS00 (1st edition)
(Previous No. IP-3538)
Date Published August 1996 P
Printed in Japan
The mark shows major revised points.
*
©
©
1994
1994
FUNCTION OUTLINE
Instruction execution time • 0.95, 1.91, 3.81, 15.3 µs (main system clock: at 4.19 MHz operation)
Internal memory PROM 32768 x 8 bits
General-purpose register • 4 bit-operation: 8 ¥ 4 banks
Input/output port CMOS input 8 On-chip pull-up resistor connection can be specified by using software: 23
*
LCD controller/driver • Segment number selection : 24/28/32 segments (can be changed to CMOS
Timer 5 channels:
Serial interface • 3-wire serial I/O mode ... MSB or LSB can be selected for transferring top bit
Bit sequential buffer (BSB) 16 bits
Clock output (PCL) • F, 524, 262, 65.5 kHz (main system clock: at 4.19 MHz operation)
Buzzer output (BUZ) • 2, 4, 32 kHz (main system clock: at 4.19 MHz operation
Vectored interrupts • External : 3
Test input • External : 1
System clock oscillator • Ceramic or crystal oscillator for main system clock oscillation
Standby function STOP/HALT mode
Power supply voltage VDD = 2.2 to 5.5 V
*
Package • 80-pin plastic QFP (14 x 14 mm)
Item Function
• 0.67, 1.33, 2.67, 10.7 µs (main system clock: at 6.0 MHz operation)
• 122 µs (subsystem clock: at 32.768 kHz operation)
RAM 1024 x 4 bits
• 8 bit-operation: 4 ¥ 4 banks
CMOS input/output 16
CMOS output 8 Also used for segment pins
N-ch open drain input/output
Total 40
8 13-V breakdown voltage
output port in 4 time-unit; max. 8)
• Display mode selection : Static 1/2 duty (1/2 bias)
1/3 duty (1/2 bias)
1/3 duty (1/3 bias)
1/4 duty (1/3 bias)
• 8-bit timer/event counter: 3 channels (can be used for 16-bit timer/event counter)
• Basic interval timer/watchdog timer: 1 channel
• Watch timer: 1 channel
• 2-wire serial I/O mode
• SBI mode
• F, 750, 375, 93.8 kHz (main system clock: at 6.0 MHz operation)
or subsystem clock: at 32.768 kHz operation)
• 2.86, 5.72, 45.8 kHz (main system clock: at 6.0 MHz operation)
• Internal : 5
• Internal : 1
• Crystal oscillator for subsystem clock oscillation
• 80-pin plastic TQFP (fine pitch) (12 x 12 mm)
µ
PD75P3018
2
µ
PD75P3018
CONTENTS
1. PIN CONFIGURATION (Top View) .................................................................................................. 4
2. BLOCK DIAGRAM ........................................................................................................................... 5
3. PIN FUNCTIONS .............................................................................................................................. 6
3.1 Port Pins .................................................................................................................................................... 6
3.2 Non-port Pins ............................................................................................................................................ 8
3.3 Pin Input/Output Circuits.......................................................................................................................... 10
3.4 Recommended Connection for Unused Pins ......................................................................................... 12
4. SWITCHING FUNCTION BETWEEN Mk I AND Mk II MODE .......................................................... 13
4.1 Difference between Mk I Mode and Mk II Mode ...................................................................................... 13
4.2 Setting of Stack Bank Selection Register (SBS) .................................................................................... 14
5. DIFFERENCES BETWEEN µPD75P3018 AND µPD753012, 753016, AND 753017....................... 15
6. MEMORY CONFIGURATION ........................................................................................................... 16
7. INSTRUCTION SET .......................................................................................................................... 20
8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY ................................................... 30
8.1 Operation Modes for Program Memory Write/Verify ............................................................................. 30
8.2 Program Memory Write Procedure .......................................................................................................... 31
8.3 Program Memory Read Procedure .......................................................................................................... 32
8.4 One-time PROM Screening ...................................................................................................................... 33
9. ELECTRICAL CHARACTERISTICS ................................................................................................ 34
10. PACKAGE DRAWINGS ................................................................................................................... 48
11. RECOMMENDED SOLDERING CONDITIONS................................................................................ 50
APPENDIX A µPD75316B, 753017 AND 75P3018 FUNCTION LIST ................................................... 51
APPENDIX B DEVELOPMENT TOOLS ................................................................................................ 53
APPENDIX C RELATED DOCUMENTS ................................................................................................ 57
*
*
*
3
1. PIN CONFIGURATION (Top View)
• 80-pin plastic QFP (14
µ
PD75P3018GC-3B9
• 80-pin plastic TQFP (fine pitch) (12
µ
PD75P3018GK-BE9
¥¥
¥ 14 mm)
¥¥
¥¥
¥ 12 mm)
¥¥
µ
PD75P3018
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24/BP0
S25/BP1
S26/BP2
S27/BP3
S28/BP4
S29/BP5
S30/BP6
S31/BP7
PIN IDENTIFICATIONS
S1180S1079S978S877S776S675S574S473S372S271S170S069RESET68P73/KR7
67
33
32
Vss
66
P50/D434P51/D535P52/D636P53/D7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
24
COM021COM122COM223COM3
25
26
LC0
V
BIAS
27
28
LC1
LC2
V
V
P40/D029P41/D130P42/D231P43/D3
P72/KR6
P71/KR5
P70/KR4
65
64
63
37
P63/KR3
P62/KR2
62
61
38
39
P01/SCK
P00/INT4
P61/KR1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
P02/SO/SB0
P60/KR0
X2
X1
V
PP
XT2
XT1
V
DD
P33/MD3
P32/MD2
P31/SYNC/MD1
P30/LCDCL/MD0
P23/BUZ
P22/PCL/PTO2
P21/PTO1
P20/PTO0
P13/TI0
P12/INT2/TI1/TI2
P11/INT1
P10/INT0
P03/SI/SB1
P00-P03 : Port0 S0-31 : Segment Output 0-31
P10-P13 : Port1 COM0-3 : Common Output 0-3
P20-P23 : Port2 V
LC0-2 : LCD Power Supply 0-2
P30-P33 : Port3 BIAS : LCD Power Supply Bias Control
P40-P43 : Port4 LCDCL : LCD Clock
P50-P53 : Port5 SYNC : LCD Synchronization
P60-P63 : Port6 TI0-2 : Timer Input 0-2
P70-P73 : Port7 PTO0-2 : Programmable Timer Output 0-2
BP0-BP7 : Bit Port 0-7 BUZ : Buzzer Clock
KR0-KR7 : Key Return 0-7 PCL : Programmable Clock
SCK : Serial Clock INT0, 1, 4 : External Vectored Interrupt 0, 1, 4
SI : Serial Input INT2 : External Test Input 2
SO : Serial Output X1, 2 : Main System Clock Oscillation 1, 2
SB0, 1 : Serial Bus 0,1 XT1, 2 : Subsystem Clock Oscillation 1, 2
RESET : Reset V
MD0-MD3 : Mode Selection 0-3 V
PP : Programming Power Supply
DD : Positive Power Supply
D0-D7 : Data Bus 0-7 Vss : Ground
4
2. BLOCK DIAGRAM
µ
PD75P3018
PTO1/P21
TI1/TI2/
P12/INT2
PTO2/P22/PCL
TI0/P13
PTO0/P20
BUZ/P23
SI/SB1/P03
SO/SB0/P02
SCK/P01
INT0/P10
INT1/P11
INT2/P12
INT4/P00
KR0/P60 to
KR7/P73
TIMER/EVENT
COUNTER
INT1
TIMER/EVENT
COUNTER
INT2
BASIC
INTERVAL
TIMER/
WATCHDOG
TIMER
INTBT
TIMER/EVENT
COUNTER
INT 0
WATCH
TIMER
INTW
CLOCKED
SERIAL
INTERFACE
INTCSI
INTERRUPT
CONTROL
8
BIT SEQ.
BUFFER (16)
#1
#2
#0
TOUT0
TOUT0
f
LCD
TOUT0
PROGRAM
COUNTER
(15)
PROM
PROGRAM
MEMORY
32768 x 8 BITS
CLOCK
OUTPUT
CONTROL
DECODE
CONTROL
fx/2
CLOCK
DIVIDER
ALU
AND
N
SYSTEM CLOCK
GENERATOR
CPU CLOCK Φ
MAINSUB
SP (8)
CY
1024 x 4 BITS
SBS
BANK
GENERAL
REG.
RAM
DATA
MEMORY
STAND BY
CONTROL
f
LCD
PORT0 P00 to P034
PORT1 P10 to P134
PORT2 P20 to P234
PORT3
PORT4
PORT5
PORT6 P60 to P634
PORT7 P70 to P734
8
4
LCD
/DRIVER
CONTROLLER
P30 to P33
4
/MD0 to MD3
P40/D0 to
4
P43/D3
P50/D4 to
4
P53/D7
S0 to S2324
S24/BP0 to
S31/BP7
COM0 to
COM3
V
LC0
3
BIAS
LCDCL/P30
SYNC/P31
to V
LC2
PCL/P22
V
V
X2X1XT2XT1
DD
SS
RESETV
PP
5
3. PIN FUNCTIONS
3.1 Port Pins (1/2)
µ
PD75P3018
Pin name I/O Shared by Function 8-bit Status I/O circuit
I/O after reset type
P00 Input INT4 This is a 4-bit input port (PORT0). — Input <B>
P01 to P03 are 3-bit pins for which an internal
P01 I/O SCK pull-up resistor connection can be specified <F>-A
by software.
P02 I/O SO/SB0 <F>-B
P03 I/O SI/SB1 <M>-C
P10 Input INT0 This is a 4-bit input port (PORT1). — Input <B>-C
These are 4-bit pins for which an internal pull-up
P11 INT1 resistor connection can be specified by software.
INT0 includes noise elimination function.
P12 TI1/TI2/INT2
P13 TI0
P20 I/O PTO0 This is a 4-bit I/O port (PORT2). — Input E-B
These are 4-bit pins for which an internal pull-up
P21 PTO1 resistor connection can be specified by software.
P22 PCL/PTO2
P23 BUZ
P30 I/O LCDCL/MD0 This is a programmable 4-bit I/O port (PORT3). — Input E-B
Input and output in single-bit units can be specified.
P31 SYNC/MD1 When set for 4-bit units, an internal pull-up resistor
connection can be specified by software.
P32 MD2
Note 1
P33 MD3
Note 2
*
*
P40
P41
P42
P43
P50
P51
P52
P53
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
I/O D0 This is an N-ch open-drain 4-bit I/O port (PORT4). š High M-E
When set to open-drain, voltage is 13 V. impedance
D1 Also functions as data I/O pin (lower 4 bits)
for program memory (PROM) write/verify.
D2
D3
I/O D4 This is an N-ch open-drain 4-bit I/O port (PORT5). High M-E
When set to open-drain, voltage is 13 V. impedance
D5 Also functions as data I/O pin (upper 4 bits)
for program memory (PROM) write/verify.
D6
D7
Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger input.
2. Low-level input leakage current increases when input instructions or bit manipulation instructions are executed.
6
3.1 Port Pins (2/2)
µ
PD75P3018
Pin name I/O Shared by Function 8-bit Status I/O circuit
I/O after reset type
P60 I/O KR0 This is a programmable 4-bit I/O port (PORT6). š Input <F>-A
Input and output in single-bit units can be specified.
P61 KR1 When set for 4-bit units, an internal pull-up resistor
connection can be specified by software.
P62 KR2
P63 KR3
P70 I/O KR4 This is a 4-bit I/O port (PORT7). Input <F>-A
When set for 4-bit units, an internal pull-up resistor
P71 KR5 connection can be specified by software.
P72 KR6
P73 KR7
BP0 Output S24 1-bit I/O port (BIT PORT). These pins are also used — Note 2 H-A
as segment output pin.
BP1 S25
BP2 S26
BP3 S27
BP4 Output S28
BP5 S29
Note 1
BP6 S30
BP7 S31
Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger input.
2. V
LC1 is selected as the input source for BP0 to BP7. The output level varies depending on the external circuit
for BP0 to BP7 and V
LC1.
Example: As shown below, BP0 to BP7 are mutually connected via the µPD75P3018, so the output levels of BP0 to BP7
are determined by the sizes of R
V
LC1
R
1
1, R2, and R3.
ON
ON
BP0
BP1
V
DD
R
2
R
3
µPD75P3018
7
3.2 Non-port Pins (1/2)
µ
PD75P3018
Pin name I/O Shared by Function Status I/O circuit
after reset type
TI0 Input P13 External event pulse input to timer/event counter Input <B>-C
TI1, TI2 Input P12/INT2
PTO0 I/O P20 Timer/event counter output Input E-B
PTO1 P21
PTO2 P22
PCL Output P22 Clock output Input E-B
BUZ I/O P23 Frequency output (for buzzer or system clock trimming) Input E-B
SCK I/O P01 Serial clock I/O Input <F>-A
SO/SB0 I/O P02 Serial data output Input <F>-B
Serial data bus I/O
SI/SB1 I/O P03 Serial data input Input <M>-C
Serial data bus I/O
INT4 Input P00 Edge detection vectored interrupt input Input <B>
(valid for detecting both rising and falling edges)
INT0 Input P10 Edge detection vectored interrupt input Clock synch/asynch Input <B>-C
(detected edge is selectable) is selectable
INT1 P11 Asynch
INT2 Input P12/TI1/TI2 Rising edge detection test input Asynch Input <B>-C
KR0-KR3 I/O P60-P63 Parallel falling edge detection test input Input <F>-A
KR4-KR7 I/O P70-P73 Parallel falling edge detection test input Input <F>-A
X1 Input — Ceramic/crystal oscillation circuit connection for main system — —
clock. If using an external clock, input to X1 and input
X2 — inverted phase to X2.
XT1 Input — Crystal oscillation circuit connection for subsystem clock. — —
If using an external clock, input to XT1 and input inverted
XT2 — phase to XT2. XT1 can be used as a 1-bit (test) input.
RESET Input — System reset input — <B>
MD0 I/O P30/LCDCL Mode selection for program memory (PROM) write/verify Input E-B
MD1 P31/SYNC
MD2, MD3 P32, P33
D0-D3 I/O P40-P43 Data bus for program memory (PROM) write/verify Input M-E
D4-D7 P50-P53
VPP — — Programmable power supply voltage for program memory — —
(PROM) write/verify.
For normal operation, connect directly to VDD.
Apply +12.5 V for PROM write/verify.
VDD — — Positive power supply — —
Vss — — Ground — —
Note
Note Circuit types enclosed in brackets indicate Schmitt trigger input.
8
µ
PD75P3018
3.2 Non-port Pins (2/2)
Pin name I/O Shared by Function Status I/O circuit
after reset type
S0-S23 Output — Segment signal output Note 1 G-A
S24-S31 Output BP0-BP7 Segment signal output Note 1 H-A
COM0-COM3 Output — Common signal output Note 1 G-B
VLC0-VLC2 — — Power source for LCD driver — —
BIAS Output — Output for external split resistor cut High —
Note 2
LCDCL
SYNC
Note 2
I/O P30 Clock output for driving external expansion driver Input E-B
I/O P31 Clock output for synchronization of external expansion driver Input E-B
impedance
Notes 1. The VLCX (X = 0, 1, 2) shown below are selected as the input source for the display outputs.
S0-S31: V
LC1, COM0-COM2: VLC2, COM3: VLC0
2. These pins are provided for future system expansion. Currently, only P30 and P31 are used.
9
3.3 Pin Input/Output Circuits
The input/output circuits for the µPD75P3018’s pins are shown in abbreviated form below.
TYPE A TYPE D
V
DD
µ
PD75P3018
V
DD
IN
P-ch
N-ch
CMOS standard input buffer
IN
Data
Output
disable
Push-pull output that can be set to high impedance output
(with both P-ch and N-ch OFF).
TYPE E-BTYPE B
P.U.R.
enable
Data
Type D
Output
disable
P-ch
N-ch
V
DD
P.U.R.
P-ch
IN/OUT
OUT
Schmitt trigger input with hysteresis characteristics.
TYPE B-C TYPE F-A
V
DD
P.U.R.
P-ch
IN
P.U.R. : Pull-Up Resistor
P.U.R.
enable
Output
disable
Data
Type A
P.U.R. : Pull-Up Resistor
P.U.R.
enable
Type D
Type B
P.U.R. : Pull-Up Resistor
V
DD
P.U.R.
P-ch
IN/OUT
(Continued)
10
µ
PD75P3018
TYPE F-B TYPE H-A
P.U.R.
Output
disable
(P)
Data
Output
disable
Output
disable
(N)
P.U.R. : Pull-Up Resistor
enable
V
DD
P-ch
N-ch
V
DD
P-ch
IN/OUT
P.U.R.
SEG
data
Bit Port
data
Output
disable
TYPE M-CTYPE G-A
*
V
LC0
P-ch
V
LC1
N-chP-ch
*
Type G-A
Type E-B
P.U.R.
enable
V
DD
IN/OUT
P.U.R.
P-ch
IN/OUT
OUT
SEG
data
V
LC2
N-ch
TYPE G-B TYPE M-E
V
LC0
P-ch
V
LC1
P-ch
COM
data
N-ch
V
LC2
N-ch
N-ch
N-ch
OUT
P-ch
Data
Output
disable
Output
disable
Input instruction
Pull-up resistor operated only when executing input instructions
Note
(when pins are low level, current flows from VDD to pins).
P.U.R. : Pull-Up Resistor
*
Data
V
DD
P-ch
P.U.R.
N-ch
Note
Voltage
controller
IN/OUT
N-ch
(+13-V
breakdown
voltage)
(+13-V
breakdown
voltage)
11
3.4 Recommended Connection for Unused Pins
Pin Recommended connection
P00/INT4 Connect to VSS or VDD
P01/SCK Connect to VSS or VDD
P02/SO/SB0
P03/SI/SB1 Connect to VSS
P10/INT0, P11/INT1 Connect to VSS or VDD
P12/TI1/TI2/INT2
P13/TI0
P20/PTO0 Input status :connect to Vss or VDD through
P21/PTO1 individual resistor
P22/PTO2/PCL Output status :open
P23/BUZ
P30/LCDCL/MD0
P31/SYNC/MD1
P32/MD2, P33/MD3
P40-P43
P50-P53
P60/KR0-P63/KR3
P70/KR4-P73/KR7
S0-S23 Open
S24/BP0-S31/BP7
COM0-COM3
VLC0-VLC2 Connect to Vss
BIAS Connect to Vss only when VLC0 to VLC2 are all not used.
Note
XT1
Note
XT2
In other cases, leave open.
Connect to Vss
Open
µ
PD75P3018
*
Note When subsystem clock is not used, specify SOS.0 = 1 (indicates that
internal feedback resistor is disconnected).
12
µ
PD75P3018
4. SWITCHING FUNCTION BETWEEN Mk I AND Mk II MODE
Setting a stack bank selection (SBS) register for the µPD75P3018 enables the program memory to be switched between
Mk I mode and Mk II mode. This function is applicable when using the µPD75P3018 to evaluate the µPD753012, 753016,
or 753017.
When the SBS bit 3 is set to 1 : sets Mk I mode (supports Mk I mode for µPD753012, 753016, and 753017)
When the SBS bit 3 is set to 0 : sets Mk II mode (supports Mk II mode for µPD753012, 753016, and 753017)
4.1 Difference between Mk I Mode and Mk II Mode
Table 4-1 lists points of difference between the Mk I mode and the Mk II mode for the µPD75P3018.
Table 4-1. Difference between Mk I Mode and Mk II Mode
Item Mk I Mode Mk II Mode
Program counter PC13-0 PC14-0
PC14 is fixed at 0
Program memory (bytes) 16384 32768
Data memory (bits) 1024 x 4
Stack Stack bank Selectable via memory banks 0 to 3
No. of stack bytes 2 bytes 3 bytes
Instruction BRA !addr1 instruction Use disabled Use enabled
CALLA !addr1 instruction
Instruction CALL !addr instruction 3 machine cycles 4 machine cycles
execution time CALLF !faddr instruction 2 machine cycles 3 machine cycles
Supported mask ROMs When set to Mk I mode: When set to Mk II mode:
µPD753012, 753016, and 753017 µPD753012, 753016, and 753017
Caution The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and 75XL series. Therefore,
this mode is effective for enhancing software compatibility with products that have a program area of
more than 16 Kbytes.
With regard to the number of stack bytes during execution of subroutine call instructions, the usable
area increases by 1 byte per stack compared to the Mk I mode when the Mk II mode is selected.
However, when the CALL !addr and CALLF !faddr instructions are used, the machine cycle becomes
longer by 1 machine cycle. Therefore, if more emphasis is placed on RAM use efficiency and
processing performance than on software compatibility, the Mk I mode should be used.
*
13
µ
PD75P3018
4.2 Setting of Stack Bank Selection Register (SBS)
Use the stack bank selection register to switch between Mk I mode and Mk II mode. Figure 4-1 shows the format for doing
this.
The stack bank selection register is set using a 4-bit memory manipulation instruction. When using the Mk I mode, be
sure to initialize the stack bank selection register to 10XXB
Note
be sure to initialize it to 00XXB
.
Note
at the beginning of the program. When using the Mk II mode,
Note Set the desired value for XX.
Figure 4-1. Format of Stack Bank Selection Register
Address 3 2 1 0
SBS3 SBS2 SBS1 SBS0F84H
Symbol
SBS
Stack area specification
0
0
Memory bank 0
0
1
Memory bank 1
1
0
Memory bank 2
1
1
Memory bank 3
0 Be sure to enter “0” for bit 2.
Mode selection specification
01Mk II mode
Mk I mode
Cautions 1. SBS3 is set to “1” after RESET input, and consequently the CPU operates in Mk I mode. When using
instructions for Mk II mode, set SBS3 to “0” and set Mk II mode before using the instructions.
2. When using Mk II mode, execute a subroutine call instruction and an interrupt instruction after
RESET input and after setting the stack bank selection register.
14
µ
PD75P3018
5. DIFFERENCES BETWEEN µPD75P3018 AND µPD753012, 753016, AND 753017
The µPD75P3018 replaces the internal mask ROM in the µPD753012, 753016, and 753017 with a one-time PROM and
features expanded ROM capacity. The µPD75P3018’s Mk I mode supports the Mk I mode in the µPD753012, 753016,
and 753017 and the µPD75P3018’s Mk II mode supports the Mk II mode in the µPD753012, 753016, and 753017.
Table 5-1 lists differences among the µPD75P3018 and the µPD753012, 753016, and 753017. Be sure to check the
differences among these products before using them with PROMs for debugging or prototype testing of application
systems or, later, when using them with a mask ROM for full-scale production.
For the CPU functions and internal hardwares, refer to µPD753017 User's Manual (U11282E).
Table 5-1. Differences between µPD75P3018 and µPD753012, 753016, and 753017
Item µPD753012 µPD753016 µPD753017 µPD75P3018
Program counter 14 bits 15 bits
Program memory (bytes) Mask ROM One-time PROM
During 12288 16384 16384 16384
Mk I mode
During 12288 16384 24576 32768
Mk II mode
Data memory (x 4 bits) 1024
Mask options Pull-up resistor for Yes (Can be specified whether to incorporate or not)
Pin configuration Pin Nos. 29 to 32 P40 to P43 P40/D0 to P43/D3
Other Noise resistance and noise radiation may differ due to the different circuit sizes and mask
PORT4 and PORT5
LCD split resistor
Feed back resistor Yes (Can be specified with the SOS register whether to
for subsystem clock incorporate or not)
Wait time Yes (Can be specified either 217/fX or 215/fX)
during RESET
Pin Nos. 34 to 37 P50 to P53 P50/D4 to P53/D7
Pin No. 50 P30/LCDCL P30/LCDCL/MD0
Pin No. 51 P31/SYNC P31/SYNC/MD1
Pin Nos. 52 and 53 P32, P33 P32/MD2, P33/MD3
Pin No. 57 IC VPP
layouts.
Note
No (Cannot incorporate)
No (Cannot incorporate)
No (Fixed at 215/fX)
Note
*
*
Note For 217/fX, during 6.0 MHz operation is 21.8 ms, and during 4.19 operation is 31.3 ms.
15
/fX, during 6.0 MHz operation is 5.46 ms, and during 4.19 operation is 7.81 ms.
For 2
Caution Noise resistance and noise radiation are different in PROM and mask ROMs. In transferring to mask
ROM versions from the PROM version in a processe between prototype development and full
production, be sure to fully evaluate the mask ROM version’s CS (not ES).
15
µ
PD75P3018
6. MEMORY CONFIGURATION
6.1 Program Counter (PC) ... 15 bits
This is a 15-bit binary counter that stores program memory address data.
Bit 15 is valid during Mk II mode. But PC14 is fixed at zero during Mk I mode, and the lower 14 bits are all valid.
Figure 6-1. Configuration of Program Counter
PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PC
Fixed at zero during
Mk I mode
6.2 Program Memory (PROM) ... 32768 x 8 bits
The program memory consists of 32768 x 8-bit one-time PROM. The program memory address can be selected as shown
below by setting the stack bank selection (SBS) register.
Mk I mode Mk II mode
Usable address 0000H to 3FFFH 0000H to 7FFFH
Figures 6-2 and 6-3 show the addressing ranges for the program memory and branch instruction and the subroutine call
instruction, during Mk I and Mk II modes.
16
0000H
0002H
0004H
0006H
0008H
000AH
000CH
Figure 6-2. Program Memory Map (Mk I mode)
765 0
MBE
RBE
Internal reset start address (upper 6 bits)
Internal reset start address (lower 8 bits)
MBE
RBE
INTBT/INT4 start address (upper 6 bits)
INTBT/INT4 start address (lower 8 bits)
MBE
RBE
INT0 start address (upper 6 bits)
INT0 start address (lower 8 bits)
MBE
RBE
INT1 start address (upper 6 bits)
INT1 start address (lower 8 bits)
MBE
RBE
INTCSI start address (upper 6 bits)
INTCSI start address (lower 8 bits)
MBE
RBE
INTT0 start address (upper 6 bits)
INTT0 start address (lower 8 bits)
MBE
RBE
INTT1, INTT2 start address (upper 6 bits)
INTT1, INTT2 start address (lower 8 bits)
CALLF
!faddr instruction
entry address
µ
BRCB
!caddr instruction
branch address
• BR BCDE instruction
• BR BCXA instruction
• BR !addr instruction
• CALL !addr instruction
branch address
PD75P3018
Branch/call
address
0020H
007FH
0080H
07FFH
0800H
0FFFH
1000H
1FFFH
2000H
2FFFH
3000H
3FFFH
Reference table for GETI instruction
BRCB
!caddr instruction
branch address
BRCB
!caddr instruction
branch address
BRCB
!caddr instruction
branch address
by GETI
BR $addr instruction
relative branch address
(–15 to –1,
+2 to +16)
Remark For instructions other than those noted above, the BR PCDE and BR PCXA instructions can be used to branch
to addresses with changes in the PC’s lower 8 bits only.
17
0000H
0002H
0004H
0006H
0008H
000AH
000CH
Figure 6-3. Program Memory Map (Mk II mode)
765 0
MBE
RBE
Internal reset start address (upper 6 bits)
Internal reset start address (lower 8 bits)
MBE
RBE
INTBT/INT4 start address (upper 6 bits)
INTBT/INT4 start address (lower 8 bits)
MBE
RBE
INT0 start address (upper 6 bits)
INT0 start address (lower 8 bits)
MBE
RBE
INT1 start address (upper 6 bits)
INT1 start address (lower 8 bits)
MBE
RBE
INTCSI start address (upper 6 bits)
INTCSI start address (lower 8 bits)
MBE
RBE
INTT0 start address (upper 6 bits)
INTT0 start address (lower 8 bits)
MBE
RBE
INTT1, INTT2 start address (upper 6 bits)
INTT1, INTT2 start address (lower 8 bits)
CALLF
!faddr instruction
entry address
!caddr instruction
branch address
BRCB
µ
PD75P3018
Branch addresses for
the following instructions
• BR BCDE
• BR BCXA
• BRA !addr1
• CALLA !addr1
BR $addr1 instruction
relative branch address
(–15 to –1,
+2 to +16)
0020H
007FH
0080H
07FFH
0800H
0FFFH
1000H
1FFFH
2000H
2FFFH
3000H
3FFFH
4000H
4FFFH
5000H
5FFFH
6000H
6FFFH
7000H
7FFFH
Reference table for GETI instruction
!addr instruction
branch address
!addr instruction
branch address
Branch/call
address
by GETI
BRCB
!caddr instruction
branch address
BRCB
!caddr instruction
branch address
BRCB
!caddr instruction
branch address
BRCB
!caddr instruction
branch address
BRCB
!caddr instruction
branch address
BRCB
!caddr instruction
branch address
BRCB
!caddr instruction
branch address
BR
CALL
Caution To allow the vectored interrupt’s 14-bit start address (noted above), set the address within a 16-K area
(0000H to 3FFFH).
Remark For instructions other than those noted above, the BR PCDE and BR PCXA instructions can be used to branch
18
to addresses with changes in the PC’s lower 8 bits only.
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