NEC UPD75P3018GK-BE9, UPD75P3018GC-3B9 Datasheet

DATA SHEET

MOS INTEGRATED CIRCUIT

µ

PD75P3018

4-BIT SINGLE-CHIP MICROCONTROLLER

The µPD75P3018 replaces the µPD753017’s internal mask ROM with a one-time PROM, and features expanded ROM
capacity.
Because the µPD75P3018 supports programming by users, it is suitable for use in evaluations of systems in
development stages using the µPD753012, 753016, or 753017, and for use in small-scale production.

The following document describes further details of the functions. Please make sure to read this document
before starting design.

µPD753017 User's Manual : U11282E

FEATURES

Compatible with µPD753017
Memory capacity:

• PROM : 32768 x 8 bits

• RAM : 1024 x 4 bits

Can operate in same power supply voltage as the mask version µPD753017

DD = 2.2 to 5.5 V

• V

LCD controller/driver

ORDERING INFORMATION

Part Number Package PROM (¥ 8 bits)

µ

PD75P3018GC-3B9 80-pin plastic QFP (14 x 14 mm, 0.65-mm pitch) 32768

µ

PD75P3018GK-BE9 80-pin plastic TQFP (fine pitch) (12 x 12 mm, 0.5-mm pitch) 32768

Caution Mask-option pull-up resistors are not provided in this device.

*

The information in this document is subject to change without notice.

Document No. U10956EJ1V0DS00 (1st edition)
(Previous No. IP-3538)
Date Published August 1996 P
Printed in Japan

The mark shows major revised points.

*

©

©

1994

1994

FUNCTION OUTLINE

Instruction execution time • 0.95, 1.91, 3.81, 15.3 µs (main system clock: at 4.19 MHz operation)

Internal memory PROM 32768 x 8 bits

General-purpose register • 4 bit-operation: 8 ¥ 4 banks

Input/output port CMOS input 8 On-chip pull-up resistor connection can be specified by using software: 23

*

LCD controller/driver • Segment number selection : 24/28/32 segments (can be changed to CMOS

Timer 5 channels:

Serial interface • 3-wire serial I/O mode ... MSB or LSB can be selected for transferring top bit

Bit sequential buffer (BSB) 16 bits
Clock output (PCL) • F, 524, 262, 65.5 kHz (main system clock: at 4.19 MHz operation)

Buzzer output (BUZ) • 2, 4, 32 kHz (main system clock: at 4.19 MHz operation

Vectored interrupts • External : 3

Test input • External : 1

System clock oscillator • Ceramic or crystal oscillator for main system clock oscillation

Standby function STOP/HALT mode
Power supply voltage VDD = 2.2 to 5.5 V

*

Package • 80-pin plastic QFP (14 x 14 mm)

Item Function

• 0.67, 1.33, 2.67, 10.7 µs (main system clock: at 6.0 MHz operation)

• 122 µs (subsystem clock: at 32.768 kHz operation)

RAM 1024 x 4 bits

• 8 bit-operation: 4 ¥ 4 banks

CMOS input/output 16
CMOS output 8 Also used for segment pins
N-ch open drain input/output
Total 40

8 13-V breakdown voltage

output port in 4 time-unit; max. 8)

• Display mode selection : Static 1/2 duty (1/2 bias)
1/3 duty (1/2 bias)
1/3 duty (1/3 bias)
1/4 duty (1/3 bias)

• 8-bit timer/event counter: 3 channels (can be used for 16-bit timer/event counter)

• Basic interval timer/watchdog timer: 1 channel

• Watch timer: 1 channel

• 2-wire serial I/O mode

• SBI mode

• F, 750, 375, 93.8 kHz (main system clock: at 6.0 MHz operation)

or subsystem clock: at 32.768 kHz operation)

• 2.86, 5.72, 45.8 kHz (main system clock: at 6.0 MHz operation)

• Internal : 5

• Internal : 1

• Crystal oscillator for subsystem clock oscillation

• 80-pin plastic TQFP (fine pitch) (12 x 12 mm)

µ

PD75P3018

2

µ

PD75P3018

CONTENTS

1. PIN CONFIGURATION (Top View) .................................................................................................. 4

2. BLOCK DIAGRAM ........................................................................................................................... 5

3. PIN FUNCTIONS .............................................................................................................................. 6

3.1 Port Pins .................................................................................................................................................... 6

3.2 Non-port Pins ............................................................................................................................................ 8

3.3 Pin Input/Output Circuits.......................................................................................................................... 10

3.4 Recommended Connection for Unused Pins ......................................................................................... 12

4. SWITCHING FUNCTION BETWEEN Mk I AND Mk II MODE .......................................................... 13

4.1 Difference between Mk I Mode and Mk II Mode ...................................................................................... 13

4.2 Setting of Stack Bank Selection Register (SBS) .................................................................................... 14

5. DIFFERENCES BETWEEN µPD75P3018 AND µPD753012, 753016, AND 753017....................... 15

6. MEMORY CONFIGURATION ........................................................................................................... 16

7. INSTRUCTION SET .......................................................................................................................... 20

8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY ................................................... 30

8.1 Operation Modes for Program Memory Write/Verify ............................................................................. 30

8.2 Program Memory Write Procedure .......................................................................................................... 31

8.3 Program Memory Read Procedure .......................................................................................................... 32

8.4 One-time PROM Screening ...................................................................................................................... 33

9. ELECTRICAL CHARACTERISTICS ................................................................................................ 34

10. PACKAGE DRAWINGS ................................................................................................................... 48

11. RECOMMENDED SOLDERING CONDITIONS................................................................................ 50

APPENDIX A µPD75316B, 753017 AND 75P3018 FUNCTION LIST ................................................... 51

APPENDIX B DEVELOPMENT TOOLS ................................................................................................ 53

APPENDIX C RELATED DOCUMENTS ................................................................................................ 57

*
*

*

3

1. PIN CONFIGURATION (Top View)

• 80-pin plastic QFP (14

µ

PD75P3018GC-3B9

• 80-pin plastic TQFP (fine pitch) (12

µ

PD75P3018GK-BE9

¥¥

¥ 14 mm)

¥¥

¥¥

¥ 12 mm)

¥¥

µ

PD75P3018

S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22

S23
S24/BP0
S25/BP1
S26/BP2
S27/BP3
S28/BP4
S29/BP5
S30/BP6
S31/BP7

PIN IDENTIFICATIONS

S1180S1079S978S877S776S675S574S473S372S271S170S069RESET68P73/KR7

67

33

32

Vss

66

P50/D434P51/D535P52/D636P53/D7

1
2

3
4
5
6
7
8
9
10
11
12
13

14
15
16
17

18
19

20

24

COM021COM122COM223COM3

25

26

LC0

V

BIAS

27

28

LC1

LC2

V

V

P40/D029P41/D130P42/D231P43/D3

P72/KR6

P71/KR5

P70/KR4

65

64

63

37

P63/KR3

P62/KR2

62

61

38

39

P01/SCK

P00/INT4

P61/KR1

60
59

58
57
56
55
54
53
52
51
50
49
48
47
46

45
44
43
42

41

40

P02/SO/SB0

P60/KR0
X2
X1
V

PP

XT2
XT1
V

DD

P33/MD3
P32/MD2
P31/SYNC/MD1
P30/LCDCL/MD0
P23/BUZ
P22/PCL/PTO2
P21/PTO1
P20/PTO0

P13/TI0
P12/INT2/TI1/TI2

P11/INT1
P10/INT0
P03/SI/SB1

P00-P03 : Port0 S0-31 : Segment Output 0-31
P10-P13 : Port1 COM0-3 : Common Output 0-3
P20-P23 : Port2 V

LC0-2 : LCD Power Supply 0-2

P30-P33 : Port3 BIAS : LCD Power Supply Bias Control
P40-P43 : Port4 LCDCL : LCD Clock
P50-P53 : Port5 SYNC : LCD Synchronization
P60-P63 : Port6 TI0-2 : Timer Input 0-2
P70-P73 : Port7 PTO0-2 : Programmable Timer Output 0-2
BP0-BP7 : Bit Port 0-7 BUZ : Buzzer Clock
KR0-KR7 : Key Return 0-7 PCL : Programmable Clock
SCK : Serial Clock INT0, 1, 4 : External Vectored Interrupt 0, 1, 4
SI : Serial Input INT2 : External Test Input 2
SO : Serial Output X1, 2 : Main System Clock Oscillation 1, 2
SB0, 1 : Serial Bus 0,1 XT1, 2 : Subsystem Clock Oscillation 1, 2
RESET : Reset V
MD0-MD3 : Mode Selection 0-3 V

PP : Programming Power Supply
DD : Positive Power Supply

D0-D7 : Data Bus 0-7 Vss : Ground

4

2. BLOCK DIAGRAM

µ

PD75P3018

PTO1/P21

TI1/TI2/

P12/INT2

PTO2/P22/PCL

TI0/P13

PTO0/P20

BUZ/P23

SI/SB1/P03

SO/SB0/P02

SCK/P01

INT0/P10
INT1/P11
INT2/P12
INT4/P00

KR0/P60 to

KR7/P73

TIMER/EVENT

COUNTER

INT1

TIMER/EVENT

COUNTER

INT2

BASIC
INTERVAL
TIMER/
WATCHDOG
TIMER

INTBT

TIMER/EVENT

COUNTER

INT 0

WATCH
TIMER

INTW

CLOCKED
SERIAL
INTERFACE

INTCSI

INTERRUPT
CONTROL

8

BIT SEQ.
BUFFER (16)

#1

#2

#0

TOUT0

TOUT0

f

LCD

TOUT0

PROGRAM

COUNTER

(15)

PROM

PROGRAM

MEMORY

32768 x 8 BITS

CLOCK

OUTPUT

CONTROL

DECODE

CONTROL

fx/2

CLOCK

DIVIDER

ALU

AND

N

SYSTEM CLOCK
GENERATOR

CPU CLOCK Φ

MAINSUB

SP (8)

CY

1024 x 4 BITS

SBS

BANK

GENERAL

REG.

RAM

DATA

MEMORY

STAND BY
CONTROL

f

LCD

PORT0 P00 to P034

PORT1 P10 to P134

PORT2 P20 to P234

PORT3

PORT4

PORT5

PORT6 P60 to P634

PORT7 P70 to P734

8

4

LCD

/DRIVER

CONTROLLER

P30 to P33

4

/MD0 to MD3

P40/D0 to

4

P43/D3

P50/D4 to

4

P53/D7

S0 to S2324

S24/BP0 to
S31/BP7

COM0 to
COM3

V

LC0

3

BIAS
LCDCL/P30
SYNC/P31

to V

LC2

PCL/P22

V

V

X2X1XT2XT1

DD

SS

RESETV

PP

5

3. PIN FUNCTIONS

3.1 Port Pins (1/2)

µ

PD75P3018

Pin name I/O Shared by Function 8-bit Status I/O circuit

I/O after reset type

P00 Input INT4 This is a 4-bit input port (PORT0). — Input <B>

P01 to P03 are 3-bit pins for which an internal

P01 I/O SCK pull-up resistor connection can be specified <F>-A

by software.

P02 I/O SO/SB0 <F>-B

P03 I/O SI/SB1 <M>-C

P10 Input INT0 This is a 4-bit input port (PORT1). — Input <B>-C

These are 4-bit pins for which an internal pull-up

P11 INT1 resistor connection can be specified by software.

INT0 includes noise elimination function.

P12 TI1/TI2/INT2

P13 TI0

P20 I/O PTO0 This is a 4-bit I/O port (PORT2). — Input E-B

These are 4-bit pins for which an internal pull-up

P21 PTO1 resistor connection can be specified by software.

P22 PCL/PTO2

P23 BUZ

P30 I/O LCDCL/MD0 This is a programmable 4-bit I/O port (PORT3). — Input E-B

Input and output in single-bit units can be specified.

P31 SYNC/MD1 When set for 4-bit units, an internal pull-up resistor

connection can be specified by software.

P32 MD2

Note 1

P33 MD3

Note 2

*

*

P40

P41

P42

P43

P50

P51

P52

P53

Note 2

Note 2

Note 2

Note 2

Note 2

Note 2

Note 2

I/O D0 This is an N-ch open-drain 4-bit I/O port (PORT4). š High M-E

When set to open-drain, voltage is 13 V. impedance

D1 Also functions as data I/O pin (lower 4 bits)

for program memory (PROM) write/verify.

D2

D3

I/O D4 This is an N-ch open-drain 4-bit I/O port (PORT5). High M-E

When set to open-drain, voltage is 13 V. impedance

D5 Also functions as data I/O pin (upper 4 bits)

for program memory (PROM) write/verify.

D6

D7

Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger input.

2. Low-level input leakage current increases when input instructions or bit manipulation instructions are executed.

6

3.1 Port Pins (2/2)

µ

PD75P3018

Pin name I/O Shared by Function 8-bit Status I/O circuit

I/O after reset type

P60 I/O KR0 This is a programmable 4-bit I/O port (PORT6). š Input <F>-A

Input and output in single-bit units can be specified.

P61 KR1 When set for 4-bit units, an internal pull-up resistor

connection can be specified by software.

P62 KR2

P63 KR3

P70 I/O KR4 This is a 4-bit I/O port (PORT7). Input <F>-A

When set for 4-bit units, an internal pull-up resistor

P71 KR5 connection can be specified by software.

P72 KR6

P73 KR7

BP0 Output S24 1-bit I/O port (BIT PORT). These pins are also used — Note 2 H-A

as segment output pin.

BP1 S25

BP2 S26

BP3 S27

BP4 Output S28

BP5 S29

Note 1

BP6 S30

BP7 S31

Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger input.

2. V

LC1 is selected as the input source for BP0 to BP7. The output level varies depending on the external circuit

for BP0 to BP7 and V

LC1.

Example: As shown below, BP0 to BP7 are mutually connected via the µPD75P3018, so the output levels of BP0 to BP7

are determined by the sizes of R

V

LC1

R

1

1, R2, and R3.

ON

ON

BP0

BP1

V

DD

R

2

R

3

µPD75P3018

7

3.2 Non-port Pins (1/2)

µ

PD75P3018

Pin name I/O Shared by Function Status I/O circuit

after reset type
TI0 Input P13 External event pulse input to timer/event counter Input <B>-C
TI1, TI2 Input P12/INT2
PTO0 I/O P20 Timer/event counter output Input E-B
PTO1 P21
PTO2 P22
PCL Output P22 Clock output Input E-B
BUZ I/O P23 Frequency output (for buzzer or system clock trimming) Input E-B
SCK I/O P01 Serial clock I/O Input <F>-A
SO/SB0 I/O P02 Serial data output Input <F>-B

Serial data bus I/O

SI/SB1 I/O P03 Serial data input Input <M>-C

Serial data bus I/O

INT4 Input P00 Edge detection vectored interrupt input Input <B>

(valid for detecting both rising and falling edges)

INT0 Input P10 Edge detection vectored interrupt input Clock synch/asynch Input <B>-C

(detected edge is selectable) is selectable
INT1 P11 Asynch
INT2 Input P12/TI1/TI2 Rising edge detection test input Asynch Input <B>-C
KR0-KR3 I/O P60-P63 Parallel falling edge detection test input Input <F>-A
KR4-KR7 I/O P70-P73 Parallel falling edge detection test input Input <F>-A
X1 Input — Ceramic/crystal oscillation circuit connection for main system — —

clock. If using an external clock, input to X1 and input
X2 — inverted phase to X2.

XT1 Input — Crystal oscillation circuit connection for subsystem clock. — —

If using an external clock, input to XT1 and input inverted
XT2 — phase to XT2. XT1 can be used as a 1-bit (test) input.

RESET Input — System reset input — <B>
MD0 I/O P30/LCDCL Mode selection for program memory (PROM) write/verify Input E-B
MD1 P31/SYNC
MD2, MD3 P32, P33
D0-D3 I/O P40-P43 Data bus for program memory (PROM) write/verify Input M-E
D4-D7 P50-P53
VPP — — Programmable power supply voltage for program memory — —

(PROM) write/verify.

For normal operation, connect directly to VDD.

Apply +12.5 V for PROM write/verify.
VDD — — Positive power supply — —
Vss — — Ground — —

Note

Note Circuit types enclosed in brackets indicate Schmitt trigger input.

8

µ

PD75P3018

3.2 Non-port Pins (2/2)

Pin name I/O Shared by Function Status I/O circuit

after reset type
S0-S23 Output — Segment signal output Note 1 G-A
S24-S31 Output BP0-BP7 Segment signal output Note 1 H-A
COM0-COM3 Output — Common signal output Note 1 G-B
VLC0-VLC2 — — Power source for LCD driver — —
BIAS Output — Output for external split resistor cut High —

Note 2

LCDCL
SYNC

Note 2

I/O P30 Clock output for driving external expansion driver Input E-B
I/O P31 Clock output for synchronization of external expansion driver Input E-B

impedance

Notes 1. The VLCX (X = 0, 1, 2) shown below are selected as the input source for the display outputs.

S0-S31: V

LC1, COM0-COM2: VLC2, COM3: VLC0

2. These pins are provided for future system expansion. Currently, only P30 and P31 are used.

9

3.3 Pin Input/Output Circuits

The input/output circuits for the µPD75P3018’s pins are shown in abbreviated form below.

TYPE A TYPE D

V

DD

µ

PD75P3018

V

DD

IN

P-ch

N-ch

CMOS standard input buffer

IN

Data

Output

disable

Push-pull output that can be set to high impedance output
(with both P-ch and N-ch OFF).

TYPE E-BTYPE B

P.U.R.
enable

Data

Type D

Output

disable

P-ch

N-ch

V

DD

P.U.R.

P-ch

IN/OUT

OUT

Schmitt trigger input with hysteresis characteristics.

TYPE B-C TYPE F-A

V

DD

P.U.R.

P-ch

IN

P.U.R. : Pull-Up Resistor

P.U.R.
enable

Output

disable

Data

Type A

P.U.R. : Pull-Up Resistor

P.U.R.
enable

Type D

Type B

P.U.R. : Pull-Up Resistor

V

DD

P.U.R.

P-ch

IN/OUT

(Continued)

10

µ

PD75P3018

TYPE F-B TYPE H-A

P.U.R.

Output

disable

(P)

Data

Output

disable

Output

disable

(N)

P.U.R. : Pull-Up Resistor

enable

V

DD

P-ch

N-ch

V

DD

P-ch

IN/OUT

P.U.R.

SEG

data

Bit Port

data

Output

disable

TYPE M-CTYPE G-A

*

V

LC0

P-ch

V

LC1

N-chP-ch

*

Type G-A

Type E-B

P.U.R.
enable

V

DD

IN/OUT

P.U.R.

P-ch

IN/OUT

OUT

SEG

data

V

LC2

N-ch

TYPE G-B TYPE M-E

V

LC0

P-ch

V

LC1

P-ch

COM

data

N-ch

V

LC2

N-ch

N-ch

N-ch

OUT

P-ch

Data

Output

disable

Output

disable

Input instruction

Pull-up resistor operated only when executing input instructions

Note

(when pins are low level, current flows from VDD to pins).

P.U.R. : Pull-Up Resistor

*

Data

V

DD

P-ch

P.U.R.

N-ch

Note

Voltage

controller

IN/OUT

N-ch

(+13-V
breakdown
voltage)

(+13-V
breakdown
voltage)

11

3.4 Recommended Connection for Unused Pins

Pin Recommended connection
P00/INT4 Connect to VSS or VDD
P01/SCK Connect to VSS or VDD
P02/SO/SB0
P03/SI/SB1 Connect to VSS
P10/INT0, P11/INT1 Connect to VSS or VDD
P12/TI1/TI2/INT2
P13/TI0
P20/PTO0 Input status :connect to Vss or VDD through
P21/PTO1 individual resistor
P22/PTO2/PCL Output status :open
P23/BUZ
P30/LCDCL/MD0
P31/SYNC/MD1
P32/MD2, P33/MD3
P40-P43
P50-P53
P60/KR0-P63/KR3
P70/KR4-P73/KR7
S0-S23 Open
S24/BP0-S31/BP7
COM0-COM3
VLC0-VLC2 Connect to Vss
BIAS Connect to Vss only when VLC0 to VLC2 are all not used.

Note

XT1

Note

XT2

In other cases, leave open.
Connect to Vss
Open

µ

PD75P3018

*

Note When subsystem clock is not used, specify SOS.0 = 1 (indicates that

internal feedback resistor is disconnected).

12

µ

PD75P3018

4. SWITCHING FUNCTION BETWEEN Mk I AND Mk II MODE

Setting a stack bank selection (SBS) register for the µPD75P3018 enables the program memory to be switched between
Mk I mode and Mk II mode. This function is applicable when using the µPD75P3018 to evaluate the µPD753012, 753016,
or 753017.

When the SBS bit 3 is set to 1 : sets Mk I mode (supports Mk I mode for µPD753012, 753016, and 753017)
When the SBS bit 3 is set to 0 : sets Mk II mode (supports Mk II mode for µPD753012, 753016, and 753017)

4.1 Difference between Mk I Mode and Mk II Mode
Table 4-1 lists points of difference between the Mk I mode and the Mk II mode for the µPD75P3018.

Table 4-1. Difference between Mk I Mode and Mk II Mode

Item Mk I Mode Mk II Mode

Program counter PC13-0 PC14-0

PC14 is fixed at 0
Program memory (bytes) 16384 32768
Data memory (bits) 1024 x 4
Stack Stack bank Selectable via memory banks 0 to 3

No. of stack bytes 2 bytes 3 bytes

Instruction BRA !addr1 instruction Use disabled Use enabled

CALLA !addr1 instruction
Instruction CALL !addr instruction 3 machine cycles 4 machine cycles
execution time CALLF !faddr instruction 2 machine cycles 3 machine cycles
Supported mask ROMs When set to Mk I mode: When set to Mk II mode:

µPD753012, 753016, and 753017 µPD753012, 753016, and 753017

Caution The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and 75XL series. Therefore,

this mode is effective for enhancing software compatibility with products that have a program area of
more than 16 Kbytes.
With regard to the number of stack bytes during execution of subroutine call instructions, the usable
area increases by 1 byte per stack compared to the Mk I mode when the Mk II mode is selected.
However, when the CALL !addr and CALLF !faddr instructions are used, the machine cycle becomes
longer by 1 machine cycle. Therefore, if more emphasis is placed on RAM use efficiency and
processing performance than on software compatibility, the Mk I mode should be used.

*

13

µ

PD75P3018

4.2 Setting of Stack Bank Selection Register (SBS)

Use the stack bank selection register to switch between Mk I mode and Mk II mode. Figure 4-1 shows the format for doing
this.
The stack bank selection register is set using a 4-bit memory manipulation instruction. When using the Mk I mode, be
sure to initialize the stack bank selection register to 10XXB

Note

be sure to initialize it to 00XXB

.

Note

at the beginning of the program. When using the Mk II mode,

Note Set the desired value for XX.

Figure 4-1. Format of Stack Bank Selection Register

Address 3 2 1 0

SBS3 SBS2 SBS1 SBS0F84H

Symbol

SBS

Stack area specification

0

0

Memory bank 0

0

1

Memory bank 1

1

0

Memory bank 2

1

1

Memory bank 3

0 Be sure to enter “0” for bit 2.

Mode selection specification

01Mk II mode

Mk I mode

Cautions 1. SBS3 is set to “1” after RESET input, and consequently the CPU operates in Mk I mode. When using

instructions for Mk II mode, set SBS3 to “0” and set Mk II mode before using the instructions.

2. When using Mk II mode, execute a subroutine call instruction and an interrupt instruction after
RESET input and after setting the stack bank selection register.

14

µ

PD75P3018

5. DIFFERENCES BETWEEN µPD75P3018 AND µPD753012, 753016, AND 753017

The µPD75P3018 replaces the internal mask ROM in the µPD753012, 753016, and 753017 with a one-time PROM and
features expanded ROM capacity. The µPD75P3018’s Mk I mode supports the Mk I mode in the µPD753012, 753016,
and 753017 and the µPD75P3018’s Mk II mode supports the Mk II mode in the µPD753012, 753016, and 753017.
Table 5-1 lists differences among the µPD75P3018 and the µPD753012, 753016, and 753017. Be sure to check the
differences among these products before using them with PROMs for debugging or prototype testing of application
systems or, later, when using them with a mask ROM for full-scale production.
For the CPU functions and internal hardwares, refer to µPD753017 User's Manual (U11282E).

Table 5-1. Differences between µPD75P3018 and µPD753012, 753016, and 753017

Item µPD753012 µPD753016 µPD753017 µPD75P3018
Program counter 14 bits 15 bits
Program memory (bytes) Mask ROM One-time PROM

During 12288 16384 16384 16384
Mk I mode

During 12288 16384 24576 32768

Mk II mode
Data memory (x 4 bits) 1024
Mask options Pull-up resistor for Yes (Can be specified whether to incorporate or not)

Pin configuration Pin Nos. 29 to 32 P40 to P43 P40/D0 to P43/D3

Other Noise resistance and noise radiation may differ due to the different circuit sizes and mask

PORT4 and PORT5

LCD split resistor

Feed back resistor Yes (Can be specified with the SOS register whether to

for subsystem clock incorporate or not)

Wait time Yes (Can be specified either 217/fX or 215/fX)

during RESET

Pin Nos. 34 to 37 P50 to P53 P50/D4 to P53/D7

Pin No. 50 P30/LCDCL P30/LCDCL/MD0

Pin No. 51 P31/SYNC P31/SYNC/MD1

Pin Nos. 52 and 53 P32, P33 P32/MD2, P33/MD3

Pin No. 57 IC VPP

layouts.

Note

No (Cannot incorporate)

No (Cannot incorporate)

No (Fixed at 215/fX)

Note

*
*

Note For 217/fX, during 6.0 MHz operation is 21.8 ms, and during 4.19 operation is 31.3 ms.

15

/fX, during 6.0 MHz operation is 5.46 ms, and during 4.19 operation is 7.81 ms.

For 2

Caution Noise resistance and noise radiation are different in PROM and mask ROMs. In transferring to mask

ROM versions from the PROM version in a processe between prototype development and full
production, be sure to fully evaluate the mask ROM version’s CS (not ES).

15

µ

PD75P3018

6. MEMORY CONFIGURATION

6.1 Program Counter (PC) ... 15 bits

This is a 15-bit binary counter that stores program memory address data.
Bit 15 is valid during Mk II mode. But PC14 is fixed at zero during Mk I mode, and the lower 14 bits are all valid.

Figure 6-1. Configuration of Program Counter

PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PC

Fixed at zero during
Mk I mode


6.2 Program Memory (PROM) ... 32768 x 8 bits

The program memory consists of 32768 x 8-bit one-time PROM. The program memory address can be selected as shown
below by setting the stack bank selection (SBS) register.

Mk I mode Mk II mode

Usable address 0000H to 3FFFH 0000H to 7FFFH

Figures 6-2 and 6-3 show the addressing ranges for the program memory and branch instruction and the subroutine call
instruction, during Mk I and Mk II modes.

16

0000H

0002H

0004H

0006H

0008H

000AH

000CH

Figure 6-2. Program Memory Map (Mk I mode)

765 0

MBE

RBE

Internal reset start address (upper 6 bits)
Internal reset start address (lower 8 bits)

MBE

RBE

INTBT/INT4 start address (upper 6 bits)
INTBT/INT4 start address (lower 8 bits)

MBE

RBE

INT0 start address (upper 6 bits)
INT0 start address (lower 8 bits)

MBE

RBE

INT1 start address (upper 6 bits)
INT1 start address (lower 8 bits)

MBE

RBE

INTCSI start address (upper 6 bits)
INTCSI start address (lower 8 bits)

MBE

RBE

INTT0 start address (upper 6 bits)
INTT0 start address (lower 8 bits)

MBE

RBE

INTT1, INTT2 start address (upper 6 bits)
INTT1, INTT2 start address (lower 8 bits)

CALLF

!faddr instruction

entry address

µ

BRCB

!caddr instruction

branch address

• BR BCDE instruction

• BR BCXA instruction

• BR !addr instruction

• CALL !addr instruction
branch address

PD75P3018

Branch/call

address

0020H

007FH

0080H

07FFH

0800H

0FFFH

1000H

1FFFH

2000H

2FFFH

3000H

3FFFH

Reference table for GETI instruction

BRCB

!caddr instruction

branch address

BRCB

!caddr instruction

branch address

BRCB

!caddr instruction

branch address

by GETI

BR $addr instruction

relative branch address

(–15 to –1,

+2 to +16)

Remark For instructions other than those noted above, the BR PCDE and BR PCXA instructions can be used to branch

to addresses with changes in the PC’s lower 8 bits only.

17

0000H

0002H

0004H

0006H

0008H

000AH

000CH

Figure 6-3. Program Memory Map (Mk II mode)

765 0

MBE

RBE

Internal reset start address (upper 6 bits)
Internal reset start address (lower 8 bits)

MBE

RBE

INTBT/INT4 start address (upper 6 bits)
INTBT/INT4 start address (lower 8 bits)

MBE

RBE

INT0 start address (upper 6 bits)
INT0 start address (lower 8 bits)

MBE

RBE

INT1 start address (upper 6 bits)
INT1 start address (lower 8 bits)

MBE

RBE

INTCSI start address (upper 6 bits)
INTCSI start address (lower 8 bits)

MBE

RBE

INTT0 start address (upper 6 bits)
INTT0 start address (lower 8 bits)

MBE

RBE

INTT1, INTT2 start address (upper 6 bits)
INTT1, INTT2 start address (lower 8 bits)

CALLF

!faddr instruction

entry address

!caddr instruction

branch address

BRCB

µ

PD75P3018

Branch addresses for

the following instructions

• BR BCDE

• BR BCXA

• BRA !addr1

• CALLA !addr1

BR $addr1 instruction

relative branch address

(–15 to –1,

+2 to +16)

0020H

007FH

0080H

07FFH

0800H

0FFFH

1000H

1FFFH

2000H

2FFFH

3000H

3FFFH

4000H

4FFFH

5000H

5FFFH

6000H

6FFFH

7000H

7FFFH

Reference table for GETI instruction

!addr instruction

branch address

!addr instruction
branch address

Branch/call

address
by GETI

BRCB

!caddr instruction

branch address

BRCB

!caddr instruction

branch address

BRCB

!caddr instruction

branch address

BRCB

!caddr instruction

branch address

BRCB

!caddr instruction

branch address

BRCB

!caddr instruction

branch address

BRCB

!caddr instruction

branch address

BR

CALL

Caution To allow the vectored interrupt’s 14-bit start address (noted above), set the address within a 16-K area

(0000H to 3FFFH).

Remark For instructions other than those noted above, the BR PCDE and BR PCXA instructions can be used to branch

18

to addresses with changes in the PC’s lower 8 bits only.

µ

PD75P3018

6.3 Data Memory (RAM) ... 1024 x 4 bits
Figure 6-4 shows the data memory configuration.

Data memory consists of a data area and a peripheral hardware area. The data area consists of 1024 x 4-bit static RAM.

Figure 6-4. Data Memory Map

Data area

static RAM

(1024 x 4)

Display data memory

Stack area

Note

General-purpose register area

000H

01FH

020H

0FFH

100H

1DFH

1E0H

1FFH

200H

Data memory

(8 x 4)

256 x 4

(248 x 4)

256 x 4

(224 x 4)

(32 x 4)

256 x 4

Memory bank

0

1

2

2FFH

300H

3FFH

F80H

Peripheral hardware area

FFFH

Note Memory bank 0, 1, 2, or 3 can be selected as the stack area.

256 x 4

Not incorporated

128 x 4

3

15

19

µ

PD75P3018

7. INSTRUCTION SET

(1) Representation and coding formats for operands

In the instruction’s operand area, use the following coding format to describe operands corresponding to the instruction’s
operand representations (for further description, see the RA75X Assembler Package User’s Manual –Language (EEU-

1363)). When there are several codes, select and use just one. Codes that consist of upper-case letters and + or – symbols
are key words that should be entered as they are.
For immediate data, enter an appropriate numerical value or label.
Enter register flag symbols as label descriptors instead of mem, fmem, pmem, bit, etc. (For details, refer to the User's
Manual). The number of labels that can be entered for fmem and pmem are restricted.

Representation Coding format
reg X, A, B, C, D, E, H, L
reg1 X, B, C, D, E, H, L
rp XA, BC, DE, HL
rp1 BC, DE, HL
rp2 BC, DE
rp’ XA, BC, DE, HL, XA’, BC’, DE’, HL’
rp’1 BC, DE, HL, XA’, BC’, DE’, HL’
rpa HL, HL+, HL–, DE, DL
rpa1 DE, DL
n4 4-bit immediate data or label
n8 8-bit immediate data or label
mem 8-bit immediate data or label
bit 2-bit immediate data or label
fmem FB0H-FBFH, FF0H-FFFH immediate data or label
pmem FC0H-FFFH immediate data or label
addr 0000H-3FFFH immediate data or label (Mk I mode and Mk II mode)
addr1 0000H-7FFFH immediate data or label (Mk II mode only)
caddr 12-bit immediate data or label
faddr 11-bit immediate data or label
taddr 20H-7FH immediate data (however, bit0 = 0) or label
PORTn PORT0-PORT7
IEXXX IEBT, IECSI, IET0, IET1, IET2, IE0-IE2, IE4, IEW
RBn RB0-RB3
MBn MB0-MB3, MB15

Note

20

Note When processing 8-bit data, only even-numbered addresses can be specified.

(2) Operation legend

A : A register; 4-bit accumulator
B : B register
C : C register
D : D register
E : E register
H : H register
L : L register
X : X register
XA : Register pair (XA); 8-bit accumulator
BC : Register pair (BC)
DE : Register pair (DE)
HL : Register pair (HL)
XA’ : Expansion register pair (XA’)
BC’ : Expansion register pair (BC’)
DE’ : Expansion register pair (DE’)
HL’ : Expansion register pair (HL’)
PC : Program counter
SP : Stack pointer
CY : Carry flag; bit accumulator
PSW : Program status word
MBE : Memory bank enable flag
RBE : Register bank enable flag
PORTn : Port n (n = 0 to 7)
IME : Interrupt master enable flag
IPS : Interrupt priority selection register
IEXXX : Interrupt enable flag
RBS : Register bank selection register
MBS : Memory bank selection register
PCC : Processor clock control register
. : Delimiter for address and bit
(XX) : Addressed data
XXH : Hexadecimal data

µ

PD75P3018

21

(3) Description of symbols used in addressing area

MB = MBE • MBS

*1

MB = 0

*2
*3

MBE = 0 :

MBE = 1 :

MB = 15, fmem = FB0H-FBFH, FF0H-FFFH

*4

MB = 15, pmem = FC0H-FFFH

*5

addr = 0000H-3FFFH

*6

addr, addr1 =*7(Current PC) –15 to (Current PC) –1

caddr =0000H-0FFFH (PC

*8

MBS = 0-3, 15

MB = 0 (000H-07FH)
MB = 15 (F80H-FFFH)
MB = MBS
MBS = 0-3, 15

(Current PC) +2 to (Current PC) +16

14, 13, 12

= 000B: Mk I or Mk II mode) or
1000H-1FFFH (PC
2000H-2FFFH (PC
3000H-3FFFH (PC
4000H-4FFFH (PC
5000H-5FFFH (PC
6000H-6FFFH (PC
7000H-7F7FH (PC

14, 13, 12

= 001B: Mk I or Mk II mode) or

14, 13, 12

= 010B: Mk I or Mk II mode) or

14, 13, 12

= 011B: Mk I or Mk II mode) or

14, 13, 12

= 100B: Mk II mode) or

14, 13, 12

= 101B: Mk II mode) or

14, 13, 12

= 110B: Mk II mode) or

14, 13, 12

= 111B: Mk II mode)

µ

PD75P3018

Data memory

addressing

Program memory

addressing

faddr = 0000H-07FFH

*9

taddr = 0020H-007FH

*10

addr1 = 0000H-7FFFH (Mk II mode only)

*11

Remarks 1. MB indicates access-enabled memory banks.

2. In area *2, MB = 0 for both MBE and MBS.

3. In areas *4 and *5, MB = 15 for both MBE and MBS.

4. Areas *6 to *11 indicate corresponding address-enabled areas.

22

µ

PD75P3018

(4) Description of machine cycles

S indicates the number of machine cycles required for skipping of skip-specified instructions. The value of S varies as
shown below.

• No skip .....................................................................S = 0

• Skipped instruction is 1-byte or 2-byte instruction.... S = 1

Note

• Skipped instruction is 3-byte instruction

Note 3-byte instructions: BR !addr, BRA !addr1, CALL !addr, CALLA !addr1

Caution The GETI instruction is skipped for one machine cycle.

..............S = 2

One machine cycle equals one cycle (= t

CY) of the CPU clock F. Use the PCC setting to select among four cycle times.

23

µ

PD75P3018

Instruction Mnemonic Operand

group

Transfer MOV A, #n4 1 1 A<-n4 String-effect A

reg1, #n4 2 2 reg1<-n4
XA, #n8 2 2 XA<-n8 String-effect A
HL, #n8 2 2 HL<-n8 String-effect B
rp2, #n8 2 2 rp2<-n8
A, @HL 1 1 A<-(HL) *1
A, @HL+ 1 2+S A<-(HL), then L<-L+1 *1 L=0
A, @HL– 1 2+S A<-(HL), then L<-L–1 *1 L=FH
A, @rpa1 1 1 A<-(rpa1) *2
XA, @HL 2 2 XA<-(HL) *1
@HL, A 1 1 (HL)<-A *1
@HL, XA 2 2 (HL)<-XA *1
A, mem 2 2 A<-(mem) *3
XA, mem 2 2 XA<-(mem) *3
mem, A 2 2 (mem)<-A *3
mem, XA 2 2 (mem)<-XA *3
A, reg1 2 2 A<-reg1
XA, rp’ 2 2 XA<-rp’
reg1, A 2 2 reg1<-A
rp’1, XA 2 2 rp’1<-XA

XCH A, @HL 1 1 A<->(HL) *1

A, @HL+ 1 2+S A<->(HL), then L<-L+1 *1 L=0
A, @HL– 1 2+S A<->(HL), then L<-L–1 *1 L=FH
A, @rpa1 1 1 A<->(rpa1) *2
XA, @HL 2 2 XA<->(HL) *1
A, mem 2 2 A<->(mem) *3
XA, mem 2 2 XA<->(mem) *3
A, reg1 1 1 A<->reg1

XA, rp’ 2 2 XA<->rp’
Table MOVT XA, @PCDE 1 3 XA<-(PC13-8+DE)ROM
reference XA, @PCXA 1 3 XA<-(PC13-8+XA)ROM

XA, @BCDE 1 3 XA<-(BCDE)ROM

XA, @BCXA 1 3 XA<-(BCXA)ROM

No. of Machine

bytes cycle area

Operation

Note

Note

Addressing

*11
*11

Skip

condition

Note Only the lower 3 bits in the B register are valid.

24

µ

PD75P3018

Instruction Mnemonic Operand

group

Bit transfer MOV1 CY, fmem.bit 2 2 CY<-(fmem.bit) *4

CY, pmem.@L 2 2 CY<-(pmem7-2+L3-2.bit(L1-0)) *5
CY, @H+mem.bit 2 2 CY<-(H+mem3-0.bit) *1
fmem.bit, CY 2 2 (fmem.bit)<-CY *4
pmem.@L, CY 2 2 (pmem7-2+L3-2.bit(L1-0))<-CY *5
@H+mem.bit, CY 2 2 (H+mem3-0.bit)<-CY *1

Arithmetic ADDS A, #n4 1 1+S A<-A+n4 carry

XA, #n8 2 2+S XA<-XA+n8 carry
A, @HL 1 1+S A<-A+(HL) *1 carry
XA, rp’ 2 2+S XA<-XA+rp’ carry
rp’1, XA 2 2+S rp’1<-rp’1+XA carry

ADDC A, @HL 1 1 A, CY<-A+(HL)+CY *1

XA, rp’ 2 2 XA, CY<-XA+rp’+CY
rp’1, XA 2 2 rp’1, CY<-rp’1+XA+CY

SUBS A, @HL 1 1+S A<-A–(HL) *1 borrow

XA, rp’ 2 2+S XA<-XA–rp’ borrow
rp’1, XA 2 2+S rp’1<-rp’1–XA borrow

SUBC A, @HL 1 1 A, CY<-A–(HL)–CY *1

XA, rp’ 2 2 XA, CY<-XA–rp’–CY
rp’1, XA 2 2 rp’1, CY<-rp’1–XA–CY

AND A, #n4 2 2 A<-A^n4

A, @HL 1 1 A<-A^(HL) *1
XA, rp’ 2 2 XA<-XA^rp’
rp’1, XA 2 2 rp’1<-rp’1^XA

OR A, #n4 2 2 A<-Avn4

A, @HL 1 1 A<-Av(HL) *1
XA, rp’ 2 2 XA<-XAvrp’
rp’1, XA 2 2 rp’1<-rp’1vXA

XOR A, #n4 2 2 A<-Avn4

A, @HL 1 1 A<-Av(HL) *1
XA, rp’ 2 2 XA<-XAvrp’

rp’1, XA 2 2 rp’1<-rp’1vXA
Accumulator RORC A 1 1 CY<-A0, A3<-CY, An-1<-An
manipulation NOT A 2 2 A<-A
Increment/ INCS reg 1 1+S reg<-reg+1 reg=0
decrement rp1 1 1+S rp1<-rp1+1 rp1=00H

@HL 2 2+S (HL)<-(HL)+1 *1 (HL)=0

mem 2 2+S (mem)<-(mem)+1 *3 (mem)=0

DECS reg 1 1+S reg<-reg–1 reg=FH

rp’ 2 2+S rp’<-rp’–1 rp’=FFH

No. of Machine

bytes cycle area

Operation

Addressing

Skip

condition

25

µ

PD75P3018

Instruction Mnemonic Operand

group

Comparison SKE reg, #n4 2 2+S Skip if reg=n4 reg=n4

@HL, #n4 2 2+S Skip if (HL)=n4 *1 (HL)=n4
A, @HL 1 1+S Skip if A=(HL) *1 A=(HL)
XA, @HL 2 2+S Skip if XA=(HL) *1 XA=(HL)
A, reg 2 2+S Skip if A=reg A=reg

XA, rp’ 2 2+S Skip if XA=rp’ XA=rp’
Carry flag SET1 CY 1 1 CY<-1
manipulation CLR1 CY 1 1 CY<-0

SKT CY 1 1+S Skip if CY=1 CY=1

NOT1 CY 1 1 CY<-CY
Memory bit SET1 mem.bit 2 2 (mem.bit)<-1 *3
manipulation fmem.bit 2 2 (fmem.bit)<-1 *4

pmem.@L 2 2 (pmem7-2+L3-2.bit(L1-0))<-1 *5
@H+mem.bit 2 2 (H+mem3-0.bit)<-1 *1

CLR1 mem.bit 2 2 (mem.bit)<-0 *3

fmem.bit 2 2 (fmem.bit)<-0 *4
pmem.@L 2 2 (pmem7-2+L3-2.bit(L1-0))<-0 *5
@H+mem.bit 2 2 (H+mem3-0.bit)<-0 *1

SKT mem.bit 2 2+S Skip if(mem.bit)=1 *3 (mem.bit)=1

fmem.bit 2 2+S Skip if(fmem.bit)=1 *4 (fmem.bit)=1
pmem.@L 2 2+S Skip if(pmem7-2+L3-2.bit(L1-0))=1 *5 (pmem.@L)=1
@H+mem.bit 2 2+S Skip if(H+mem3-0.bit)=1 *1

SKF mem.bit 2 2+S Skip if(mem.bit)=0 *3 (mem.bit)=0

fmem.bit 2 2+S Skip if(fmem.bit)=0 *4 (fmem.bit)=0
pmem.@L 2 2+S Skip if(pmem7-2+L3-2.bit(L1-0))=0 *5 (pmem.@L)=0
@H+mem.bit 2 2+S Skip if(H+mem3-0.bit)=0 *1

SKTCLR fmem.bit 2 2+S Skip if(fmem.bit)=1 and clear *4 (fmem.bit)=1

pmem.@L 2 2+S
@H+mem.bit 2 2+S Skip if(H+mem3-0.bit)=1 and clear *1

AND1 CY, fmem.bit 2 2 CY<-CY^(fmem.bit) *4

CY, pmem.@L 2 2 CY<-CY^(pmem7-2+L3-2.bit(L1-0)) *5
CY, @H+mem.bit 2 2 CY<-CY^(H+mem3-0.bit) *1

OR1 CY, fmem.bit 2 2 CY<-CYv(fmem.bit) *4

CY, pmem.@L 2 2 CY<-CYv(pmem7-2+L3-2.bit(L1-0)) *5
CY, @H+mem.bit 2 2 CY<-CYv(H+mem3-0.bit) *1

XOR1 CY, fmem.bit 2 2 CY<-CYv (fmem.bit) *4

CY, pmem.@L 2 2 CY<-CYv(pmem7-2+L3-2.bit(L1-0)) *5
CY, @H+mem.bit 2 2 CY<-CYv(H+mem3-0.bit) *1

No. of Machine

bytes cycle area

Skip if(pmem7-2+L3-2.bit (L1-0))=1 and clear

Operation

Addressing

*5 (pmem.@L)=1

condition

(@H+mem.bit)=1

(@H+mem.bit)=0

(@H+mem.bit)=1

Skip

26

µ

PD75P3018

Instruction Mnemonic Operand

group

Branch BR

Note 1

addr — — PC14<-0, PC13-0<-addr *6

addr1 — — PC14-0<-addr1 *11

!addr 3 3 PC14<-0, PC13-0<-addr *6
$addr 1 2 PC14<-0, PC13-0<-addr *7
$addr1 1 2 PC14<-0, PC13-0<-addr1

PCDE 2 3 PC14<-0, PC13-0<-PC13-8+DE

PCXA 2 3 PC14<-0, PC13-0<-PC13-8+XA

BCDE 2 3 PC14<-0, PC13-0<-BCDE

BCXA 2 3 PC14<-0, PC13-0<-BCXA

Note 1

BRA

!addr1 3 3 PC14-0<-addr1 *11

BRCB !caddr 2 2 PC14<-0, PC13-0<-PC13, 12+caddr11-0 *8

No. of Machine

Operation

Addressing

bytes cycle area

Use the assembler to select the
most appropriate instruction
among the following.

• BR !addr

• BRCB !caddr

• BR $addr

Use the assembler to select
the most appropriate instruction
among the following.

• BRA !addr1

• BR !addr

• BRCB !caddr

• BR $addr1

PC14-0<-addr1

PC14-0<-PC14-8+DE

PC14-0<-PC14-8+XA

PC14-0<-BCDE

PC14-0<-BCXA

Note 2

Note 2

Note 2

Note 2

*11

*11

PC14-0<-PC14, 13, 12+caddr11-0

Skip

condition

Notes 1. Shaded areas indicate support for Mk II mode only.

2. The only following bits are valid in the B register.

For Mk I mode : Lower 2 bits
For Mk II mode : Lower 3 bits

27

µ

PD75P3018

Instruction Mnemonic Operand

group

Subroutine CALLA

Note

!addr1 3 3 (SP–5)<-0, PC14-12 *11

No. of Machine

Operation

bytes cycle area

stack control (SP–6)(SP–3)(SP–4)<-PC11-0

(SP–2)<-X, X, MBE, RBE
PC14–0<-addr1, SP<-SP–6

Note

CALL

!addr 3 3 (SP–4)(SP–1)(SP–2)<-PC11-0 *6

(SP–3)<-MBE, RBE, PC13, 12
PC14<-0, PC13–0<-addr, SP<-SP–4

4 (SP–5)<-0, PC14-12

(SP–6)(SP–3)(SP–4)<-PC11-0
(SP–2)<-X, X, MBE, RBE
PC14<-0, PC13-0<-addr, SP<-SP–6

Note

CALLF

!faddr 2 2 (SP–4)(SP–1)(SP–2)<-PC11-0 *9

(SP–3)<-MBE, RBE, PC13, 12
PC14<-0, PC13-0<-000+faddr, SP<-SP–4

3 (SP–5)<-0, PC14-12

(SP–6)(SP–3)(SP–4)<-PC11-0
(SP–2)<-X, X, MBE, RBE
PC14-0<-0000+faddr, SP<-SP–6

Note

RET

1 3 MBE, RBE, PC13, 12<-(SP+1)

PC11-0<-(SP)(SP+3)(SP+2)
PC14<-0, SP<-SP+4
X, X, MBE, RBE<-(SP+4)
0, PC14-12<-(SP+1)
PC11-0<-(SP)(SP+3)(SP+2)
SP<-SP+6

Note

RETS

1 3+S MBE, RBE, PC13, 12<-(SP+1) Unconditional

PC11-0<-(SP)(SP+3)(SP+2)
PC14<-0, SP<-SP+4
then skip unconditionally
X, X, MBE, RBE<-(SP+4)
0, PC14-12<-(SP+1)
PC11-0<-(SP)(SP+3)(SP+2)
SP<-SP+6
then skip unconditionally

Note

RETI

13PC13, 12<-(SP+1)1, 0, PC14<-0

PC11-0<-(SP)(SP+3)(SP+2)
PSW<-(SP+4)(SP+5), SP<-SP+6
0, PC14-12<-(SP+1)
PC11-0<-(SP)(SP+3)(SP+2)
PSW<-(SP+4)(SP+5), SP<-SP+6

Addressing

Skip

condition

Note Shaded areas indicate support for Mk II mode only. Other areas indicate support for Mk I mode only.

28

µ

PD75P3018

Instruction Mnemonic Operand

group

No. of Machine

Operation

bytes cycle area
Subroutine PUSH rp 1 1 (SP–1)(SP–2)<-rp, SP<-SP–2
stack control BS 2 2

(SP–1)<-MBS, (SP–2)<-RBS, SP<-SP–2

POP rp 1 1 rp<-(SP+1)(SP), SP<-SP+2

BS 2 2 MBS<-(SP+1), RBS<-(SP), SP<-SP+2
Interrupt EI 2 2 IME(IPS.3)<-1
control IEXXX 2 2 IEXXX<-1

DI 2 2 IME(IPS.3)<-0

IEXXX 2 2 IEXXX<-0
I/O IN

Note 1

A, PORTn 2 2 A<-PORTn (n=0-7)

XA, PORTn 2 2 XA<-PORTn+1, PORTn (n=4, 6)

Note 1

OUT

PORTn, A 2 2 PORTn<-A (n=2-7)

PORTn, XA 2 2 PORTn+1, PORTn<-XA (n=4, 6)
CPU control HALT 2 2 Set HALT Mode(PCC.2<-1)

STOP 2 2 Set STOP Mode(PCC.3<-1)
NOP 1 1 No Operation

Special SEL RBn 2 2 RBS<-n (n=0-3)

MBn 2 2 MBS<-n (n=0-3, 15)

Note 2, 3

GETI

taddr 1 3 • When using TBR instruction *10

PC13-0<-(taddr)5-0+(taddr+1), PC14<-0

- - - - - - - - - - - - - - - - - - - - - - - - - - -

• When using TCALL instruction
(SP–4)(SP–1)(SP–2)<-PC11-0

(SP–3)<-MBE, RBE, PC13, 12, PC14<-0
PC13-0<-(taddr)5-0+(taddr+1)
SP<-SP–4

- - - - - - - - - - - - - - - - - - - - - - - - - - -

• When using instruction other than Determined by
TBR or TCALL referenced
Execute (taddr)(taddr+1) instructions instruction

1 3 • When using TBR instruction *10

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

PC13-0<-(taddr)5-0+(taddr+1), PC14<-0

4 • When using TCALL instruction

(SP–5)<-0, PC14-12
(SP–6)(SP–3)(SP–4)<-PC11-0
(SP–2)<-X, X, MBE, RBE, PC14<-0
PC13-0<-(taddr)5-0+(taddr+1)

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

SP<-SP–6

3 • When using instruction other than Determined by

TBR or TCALL referenced
Execute (taddr)(taddr+1) instructions instruction

Addressing

Skip

condition

- - - - - - - - - - - -

- - - - - - - - - - - -

- - - - - - - - - - - -

- - - - - - - - - - - -

Notes 1. Before executing the IN or OUT instruction, set MBE to 0 or 1 and set MBS to 15.

2. TBR and TCALL are assembler pseudo-instructions for the GETI instruction’s table definitions.

3. Shaded areas indicate support for Mk II mode only. Other areas indicate support for Mk I mode only.

29

8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY

The program memory contained in the µPD75P3018 is a 32768 x 8-bit one-time PROM that can be electrically written one
time only. The pins listed in the table below are used for this PROM’s write/verify operations. Clock input from the X1
pin is used instead of address input as a method for updating addresses.

Pin Function

VPP Pin where program voltage is applied during program memory

write/verify (usually VDD potential)

X1, X2 Clock input pins for address updating during program memory

write/verify. Input the X1 pin’s inverted signal to the

X2 pin.
MD0-MD3 Operation mode selection pin for program memory write/verify
D0/P40 to D3/P43 8-bit data I/O pins for program memory write/verify

(lower 4 bits)
D4/P50 to D7/P53
(upper 4 bits)

VDD Pin where power supply voltage is applied.

*

Applies VDD = 2.2 to 5.5 V in normal operation mode and +6 V

for program memory write/verify.

µ

PD75P3018

Caution Pins not used for program memory write/verify should be connected to Vss.

8.1 Operation Modes for Program Memory Write/Verify

When +6 V is applied to the V
mode. The following operation modes can be specified by setting pins MD0 to MD3 as shown below.

Operation mode specification Operation mode
VPP VDD MD0 MD1 MD2 MD3
+12.5 V +6 V H L H L Zero-clear program memory address

X: L or H

DD pin and +12.5 V to the VPP pin, the µPD75P3018 enters the program memory write/verify

L H H H Write mode
L L H H Verify mode
H X H H Program inhibit mode

30

8.2 Program Memory Write Procedure

Program memory can be written at high speed using the following procedure.

(1) Pull unused pins to Vss through resistors. Set the X1 pin low.
(2) Supply 5 V to the V

DD and VPP pins.

(3) Wait 10 µs.
(4) Select the zero-clear program memory address mode.
(5) Supply 6 V to the V

DD and 12.5 V to the VPP pins.

(6) Select the program inhibit mode.
(7) Write data in the 1 ms write mode.
(8) Select the program inhibit mode.
(9) Select the verify mode. If the data is correct, go to step (10) and if not, repeat steps (7) to (9).
(10) (X : number of write operations from steps (7) to (9)) x 1 ms additional write.
(11) Select the program inhibit mode.
(12) Apply four pulses to the X1 pin to increment the program memory address by one.
(13) Repeat steps (7) to (12) until the end address is reached.
(14) Select the zero-clear program memory address mode.
(15) Return the V

DD and VPP pins back to 5 V.

(16) Turn off the power.

µ

PD75P3018

The following figure shows steps (2) to (12).

Write

VPP

VPP

VDD

VDD + 1

VDD

V

DD

X1

D0/P40 to D3/P43
D4/P50 to D7/P53

MD0

(P30)

MD1

(P31)

Data input

X repetitions

Verify

Data

output

Additional write

Data input

Address

increment

MD2

(P32)

MD3

(P33)

31

µ

PD75P3018

8.3 Program Memory Read Procedure

The µPD75P3018 can read program memory contents using the following procedure.

(1) Pull unused pins to Vss through resistors. Set the X1 pin low.
(2) Supply 5 V to the V

DD and VPP pins.

(3) Wait 10 µs.
(4) Select the zero-clear program memory address mode.
(5) Supply 6 V to the V

DD and 12.5 V to the VPP pins.

(6) Select the program inhibit mode.
(7) Select the verify mode. Apply four pulses to the X1 pin. Every four clock pulses will output the data stored in one

address.
(8) Select the program inhibit mode.
(9) Select the zero-clear program memory address mode.
(10) Return the V

DD and VPP pins back to 5 V.

(11) Turn off the power.

The following figure shows steps (2) to (9).

V

PP

V

PP

V

DD

V

DD

+ 1

V

DD

DD

V

X1

D0/P40 to D3/P43
D4/P50 to D7/P53

MD0

(P30)

MD1

(P31)

MD2

(P32)

Data output Data output

“L”

32

MD3

(P33)

µ

PD75P3018

8.4 One-time PROM Screening

Due to its structure, the one-time PROM cannot be fully tested before shipment by NEC. Therefore, NEC recommends
that after the required data is written and the PROM is stored under the temperature and time conditions shown below,
the PROM should be verified via a screening.

Storage temperature Storage time

125°C 24 hours

33

9. ELECTRICAL CHARACTERISTICS

*

Absolute Maximum Ratings (TA = 25 °C)

Parameter Symbol Conditions Ratings Unit
Supply voltage VDD –0.3 to +7.0 V
PROM supply voltage VPP –0.3 to +13.5 V
Input voltage VI1 Other than ports 4 and 5 –0.3 to VDD + 0.3 V

Output voltage VO –0.3 to VDD + 0.3 V
High-level output current IOH Per pin –10 mA

Low-level output current IOL Per pin 30 mA

Operating ambient TA –40 to +85 °C
temperature

Storage temperature Tstg –65 to +150 °C

VI2

µ

PD75P3018

Ports 4 and 5 (During N-ch open drain)

Total of all pins –30 mA

Total of all pins 220 mA

–0.3 to +14 V

Caution If the absolute maximum rating of even one of the parameters is exceeded even momentarily, the

quality of the product may be degraded. The absolute maximum ratings are therefore values which,
when exceeded, can cause the product to be damaged. Be sure that these values are never exceeded
when using the product.

Capacitance (T

Input capacitance CIN f = 1 MHz 15 pF
Output capacitance COUT Unmeasured pins returned to 0 V 15 pF
I/O capacitance CIO 15 pF

A = 25 °C, VDD = 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

34

µ

PD75P3018

Main System Clock Oscillation Circuit Characteristics (TA = –40 to +85 °C)

Resonator Recomended Constants Parameter Conditions MIN. TYP. MAX. Unit

Ceramic VDD = 2.2 to 5.5 V Oscillation frequency 1.0 6.0
resonator (fX)

Note 1

X1 X2

Note 2

MHz

C1 C2

V

DD

Crystal VDD = 2.2 to 5.5 V Oscillation frequency 1.0 6.0
resonator (fX)

Oscillation After VDD has 4 ms
stabilization time

Note 3

reached MIN. value
of oscillation voltage
range

Note 2

Note 1

MHz

X1 X2

C1 C2

V

DD

External VDD = 1.8 to 5.5 V X1 input frequency 1.0 6.0
clock (fX)

Oscillation VDD = 4.5 to 5.5 V 10 ms
stabilization time

Note 3

30

Note 2

Note 1

MHz

X1 X2

X1 input high-/ 83.3 500 ns
low-level widths
(tXH, tXL)

Notes1.The oscillation frequency and X1 input frequency shown above indicate characteristics of the oscillation circuit

only. For the instruction execution time, refer to AC Characteristics.

2.When the supply voltage is 1.8 V ≤ VDD < 2.7 V and the oscillation frequency is 4.19 MHz < fX ≤ 6.0 MHz, do
not select processor clock control register (PCC) = 0011 as the instruction execution time. If PCC = 0011, one

µ

machine cycle is less than 0.95

3.The oscillation stabilization time is the time required for oscillation to be stabilized after V

s, falling short of the rated value of 0.95 µs.

DD has been applied

or STOP mode has been released.

CautionWhen using the main system clock oscillation circuit, wire the portion enclosed in the broken line in

the above figure as follows to prevent adverse influences due to wiring capacitance:

• Keep the wiring length as short as possible.

• Do not cross the wiring with other signal lines.

• Do not route the wiring in the vicinity of a line through which a high alternating current flows.

• Always keep the ground point of the capacitor of the oscillation circuit at the same potential as V

DD.

• Do not ground to a power supply pattern through which a high current flows.

• Do not extract signals from the oscillation circuit.

35

µ

PD75P3018

Subsystem Clock Oscillation Circuit Characteristics (TA = –40 to +85 °C, VDD = 2.2 to 5.5 V)

Resonator Recomended Constants Parameter Conditions MIN. TYP. MAX. Unit

Crystal Oscillation frequency 32 32.768 35 kHz
resonator (fXT)

XT1 XT2

R

C3 C4

V

DD

Note 1

Oscillation VDD = 4.5 to 5.5 V 1.0 2 s
stabilization time

Note 2

VDD ≥ 2.2 V 10

External XT1 input frequency 32 100 kHz
clolck (fXT)

XT1 XT2

Note 1

XT1 input high-/ 5 15
low-level widths
(tXTH, tXTL)

µ

s

Notes1.The oscillation frequency and XT1 input frequency shown above indicate characteristics of the oscillation circuit

only. For the instruction execution time, refer to AC Characteristics.

2.The oscillation stabilization time is the time required for oscillation to be stabilized after V

DD has been applied.

CautionWhen using the subsystem clock oscillation circuit, wire the portion enclosed in the broken line in the

above figure as follows to prevent adverse influences due to wiring capacitance:

• Keep the wiring length as short as possible.

• Do not cross the wiring with other signal lines.

• Do not route the wiring in the vicinity of a line through which a high alternating current flows.

• Always keep the ground point of the capacitor of the oscillation circuit at the same potential as V

DD.

• Do not ground to a power supply pattern through which a high current flows.

• Do not extract signals from the oscillation circuit.

The subsystem clock oscillation circuit has a low amplification factor to reduce current dissipation and
is more susceptible to noise than the main system clock oscillation circuit. Therefore, exercise utmost
care in wiring the subsystem clock oscillation circuit.

36

µ

PD75P3018

DC Characteristics (TA = –40 to +85 °C, VDD = 2.2 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit
Low-level output IOL Per pin 15 mA
current Total of all pins 150 mA
High-level input VIH1 Ports 2, 3 2.7 V ≤ VDD ≤ 5.5 V 0.7 VDD VDD V
voltage 2.2 V ≤ VDD < 2.7 V 0.9 VDD VDD V

VIH2 Ports 0, 1, 6, 7, RESET 2.7 V ≤ VDD ≤ 5.5 V 0.8 VDD VDD V

2.2 V ≤ VDD < 2.7 V 0.9 VDD VDD V

VIH3 Ports 4, 5 2.7 V ≤ VDD ≤ 5.5 V 0.7 VDD 13 V

(During N-ch open drain) 2.2 V ≤ VDD < 2.7 V 0.9 VDD 13 V

VIH4 X1, XT1 VDD – 0.1 VDD V
Low-level input VIL1 Ports 2, 3, 4, 5 2.7 V ≤ VDD ≤ 5.5 V 0 0.3 VDD V
voltage 2.2 V ≤ VDD < 2.7 V 0 0.1 VDD V

VIL2 Ports 0, 1, 6, 7, RESET 2.7 V ≤ VDD ≤ 5.5 V 0 0.2 VDD V

2.2 V ≤ VDD < 2.7 V 0 0.1 VDD V

VIL3 X1, XT1 0 0.1 V
High-level output VOH SCK, SO/SB0, SB1, Ports 2, 3, 6, 7, BP0 to 7 VDD – 0.5 V
voltage IOH = –1 mA
Low-level output VOL1 SCK, SO, Ports 2, 3, 4, 5, 6, 7, IOL = 15 mA 0.2 2.0 V
voltage BP0 to 7 VDD = 4.5 to 5.5 V

IOL = 1.6 mA 0.4 V

VOL2 SB0, SB1 During N-ch open drain 0.2 VDD V

Pull-up resistor ≥ 1 kΩ
High-level input ILIH1 VIN = VDD Pins other than X1, XT1 3
leakage current ILIH2 X1, XT1 20

ILIH3 VIN = 13 V Ports 4, 5 (During N-ch open drain) 20
Low-level input ILIL1 VIN = 0 V Pins other than X1, XT1, Ports 4, 5 –3
leakage current ILIL2 X1, XT1 –20

ILIL3 Ports 4, 5 (During N-ch open drain) –30

When input instruction VDD = 5.0 V –10 –27

is executed VDD = 3.0 V –3 –8
High-level output ILOH1 VOUT = VDD SCK, SO/SB0, SB1, Ports 2, 3, 6, 7 3
leakage current ILOH2 VOUT = 13 V Ports 4, 5 (During N-ch open drain) 20
Low-level output ILOL VOUT = 0 V –3
leakage current
Internal pull-up RL1 VIN = 0 V Ports 0, 1, 2, 3, 6, 7 (except P00 pin) 50 100 200 kΩ
resistor

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

37

µ

PD75P3018

DC Characteristics (TA = –40 to +85 °C, VDD = 2.2 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit
LCD drive voltage VLCD VAC0 = 0 2.2 VDD V
LCD output voltage
deviation

Note 1

(common) VLCD2 = VLCD ¥ 1/3
LCD output voltage
deviation

Note 1

(segment)
Supply current

VODC IO = ±5 µAVLCD0 = VLCD 0 ±0.2 V

VLCD1 = VLCD ¥ 2/3

VODS IO = ±1 µA 2.2 V - VLCD - VDD 0 ±0.2 V

Note 2

IDD1 6.0 MHz

Note 3

VDD = 5.0 V ±10 %

crystal VDD = 3.0 V ±10 %

Note 4

Note 5

3.7 11.0 mA

0.73 2.2 mA

IDD2 oscillation HALT VDD = 5.0 V ±10 % 0.92 2.6 mA

IDD1

C1 = C2 = 22 pF

4.19 MHz
crystal VDD = 3.0 V ±10 %

mode VDD = 3.0 V ±10 % 0.30 0.9 mA

Note 3

VDD = 5.0 V ±10 %

Note 4

Note 5

2.7 8.0 mA

0.57 1.7 mA

IDD2 oscillation HALT VDD = 5.0 V ±10 % 0.90 2.5 mA

C1 = C2 = 22 pF

mode VDD = 3.0 V ±10 % 0.28 0.8 mA

IDD3 32.768 Low- VDD = 3.0 V ±10 % 42 126

Note 6

kHz
crystal
oscillation

voltage VDD = 2.5 V ±10 % 37 110

Note 7

mode

VDD = 3.0 V, TA = 25 °C 42 84

Low power

VDD = 3.0 V ±10 % 39 1 17

dissipation

VDD = 3.0 V, TA = 25 °C 39 78

Note 8

mode

IDD4 HALT Low- VDD = 3.0 V ±10 % 8.5 25

mode voltage V DD = 2.5 V ±10 % 5.8 17

Note 7

mode

VDD = 3.0 V, TA = 25 °C 8.5 17

Low power

VDD = 3.0 V ±10 % 3.5 12

dissipation

VDD = 3.0 V, TA = 25 °C 3.5 7

Note 8

mode

IDD5

XT1 = 0 V

Note 9

VDD = 5.0 V ±10 % 0.05 10

STOP mode VDD = 3.0 V ±10 % 0.02 5

TA = 25 °C 0.02 3

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

Notes 1. Voltage deviation is the difference between the ideal values (VLCDn ; n = 0, 1, 2) of the segment and common

outputs and the output voltage.

2. The current flowing through the internal pull-up resistor is not included.

3. Including the case when the subsystem clock oscillates.

4. When the device operates in high-speed mode with the processor clock control register (PCC) set to 0011.

5. When the device operates in low-speed mode with PCC set to 0000.

6. When the device operates on the subsystem clock, with the system clock control register (SCC) set to 1001

and oscillation of the main system clock stopped.

7. When the sub-oscillation control register (SOS) is set to 0000.

8. When the SOS is set to 0010.

9. When the SOS is set to 0011.

38

µ

Operation
guaranteed range

Supply voltage

V

DD

[V]

0123456

0.5

1

2

3

4

5

6

60

64

70

Cycle time t

CY

[µs]

tCY vs V

DD

(with main system clock)

AC Characteristics (TA = –40 to +85 °C, VDD = 2.2 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit
CPU clock cycle time
(minimum instruction with
execution time main system
= 1 machine cycle) clock clock is used 0.95 64

TI0, TI1, TI2 input frequency

TI0, TI1, TI2 high-/low-level
widths 1.8
Interrupt input high-/low-level
widths INT1, 2, 4 10

RESET low-level

Note 1

tCY Operation

Operation with subsystem 114 12 2 125
clock

fTI VDD = 2.7 to 5.5 V 0 1 MHz

tTIH, tTIL VDD = 2.7 to 5.5 V 0.48

tINTH, tINTL INT0 Note 2

KR0-7 10

width tRSL 10

When ceramic
or crystal is used
When external

VDD = 2.7 to 5.5 V
VDD = 2.2 to 5.5 V
VDD = 2.7 to 5.5 V

0.67 64

0.85 64

0.67 64

0 275 kHz

PD75P3018

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

Notes 1. The cycle time of the CPU clock

(F) is determined by the
oscillation frequency of the
connected resonator (and
external clock), the system clock
control register (SCC), and
processor clock control register
(PCC).
The figure on the right shows the
supply voltage V
t

CY characteristics when the

DD vs. cycle time

device operates with the main
system clock.

CY or 128/fX depending on the

2. 2t
setting of the interrupt mode
register (IM0).

Remark The shaded portion indicates the range when

the external clock is used.

39

µ

PD75P3018

Serial transfer operation

2-wire and 3-wire serial I/O modes (SCK ... internal clock output): (TA = –40 to +85 °C, VDD = 2.2 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

SCK cycle time tKCY1 VDD = 2.7 to 5.5 V 1300 ns

3800 ns

SCK high-/low-level widths tKL1, tKH1 VDD = 2.7 to 5.5 V

Note 1

SI

setup time (to SCK ↑)

tSIK1 VDD = 2.7 to 5.5 V 150 ns

t

KCY1

/2–50

t

KCY1

/2–150

500 ns

Note 1

SI

hold time (from SCK ↑)

tKSI1 VDD = 2.7 to 5.5 V 400 ns

600 ns
SCK Ø Æ SO
delay

Note 1

output

tKSO1 RL = 1 kΩ,

time CL = 100 pF 0 1000 ns

Note 2

VDD = 2.7 to 5.5 V 0 250 ns

2-wire and 3-wire serial I/O modes (SCK ... external clock input): (TA = –40 to +85 °C, VDD = 2.2 to 5.5 V)

ns
ns

Parameter Symbol Conditions MIN. TYP. MAX. Unit

SCK cycle time tKCY2 VDD = 2.7 to 5.5 V 800 ns

3200 ns

SCK high-/low-level widths tKL2, tKH2 VDD = 2.7 to 5.5 V 400 ns

1600 ns

Note 1

SI

setup time (to SCK ↑)

tSIK2 VDD = 2.7 to 5.5 V 100 ns

150 ns

Note 1

SI

hold time (from SCK ↑)

tKSI2 VDD = 2.7 to 5.5 V 400 ns

600 ns
SCK Ø Æ SO
delay

Note 1

output

tKSO2 RL = 1 kΩ,

time CL = 100 pF 0 1000 ns

Note 2

VDD = 2.7 to 5.5 V 0 300 ns

Notes1.In 2-wire serial I/O mode, read SB0 or SB1 instead.

2.R

L and CL respectively indicate the load resistance and load capacitance of the SO output line.

40

µ

PD75P3018

SBI mode (SCK ... internal clock output (master)): (TA = –40 to +85 °C, VDD = 2.2 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

SCK cycle time tKCY3 VDD = 2.7 to 5.5 V 1300 ns

3800 ns

SCK high-/low-level widths tKL3, tKH3 VDD = 2.7 to 5.5 V

SB0, 1 setup time
(to SCK ↑)
SB0, 1 hold time (from SCK ↑)
SCK Ø Æ SB0, 1 output
delay

time CL = 100 pF 0 1000 ns
SCK ↑ Æ SB0, 1 Ø
SB0, 1 Ø Æ SCK Ø
SB0, 1 low-level width tSBL tKCY3 ns
SB0, 1 high-level width tSBH tKCY3 ns

tSIK3 VDD = 2.7 to 5.5 V 150 ns

tKSI3 tKCY3/2 ns
tKSO3 RL = 1 kΩ,

tKSB tKCY3 ns
tSBK tKCY3 ns

Note

VDD = 2.7 to 5.5 V 0 250 ns

t

KCY3

/2–50

t

KCY3

/2–150

500 ns

ns
ns

SBI mode (SCK ... external clock input (slave)): (TA = –40 to +85 °C, VDD = 2.2 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

SCK cycle time tKCY4 VDD = 2.7 to 5.5 V 800 ns

3200 ns

SCK high-/low-level widths tKL4, tKH4 VDD = 2.7 to 5.5 V 400 ns

1600 ns
SB0, 1 setup time
(to SCK ↑)
SB0, 1 hold time (from SCK ↑)
SCK Ø Æ SB0, 1 output
delay

time CL = 100 pF 0 1000 ns
SCK ↑ Æ SB0, 1 Ø
SB0, 1 Ø Æ SCK Ø
SB0, 1 low-level width tSBL tKCY4 ns
SB0, 1 high-level width tSBH tKCY4 ns

tSIK4 VDD = 2.7 to 5.5 V 100 ns

150 ns
tKSI4 tKCY4/2 ns
tKSO4 RL = 1 kΩ,

tKSB tKCY4 ns
tSBK tKCY4 ns

Note

VDD = 2.7 to 5.5 V 0 300 ns

NoteRL and CL respectively indicate the load resistance and load capacitance of the SB0, 1 output line.

41

AC Timing Test Points (except X1 and XT1 inputs)

V

IH

V

IL

Test points

Clock Timing

t

XL

1/f

µ

PD75P3018

V

OH

V

OL

X

t

XH

X1 input

XT1 input

TI0, TI1, TI2 Timing

VDD–0.1 V

0.1 V

1/f

XT

t

XTL

t

XTH

VDD–0.1 V

0.1 V

42

TI0, TI1, TI2

1/f

TI

t

TIL

t

TIH

Serial Transfer Timing

3-wire Serial I/O Mode

SCK

t

KL1,2

t

SIK1,2

KCY1,2

t

t

KSI1,2

t

KH1,2

µ

PD75P3018

SI

SO

2-wire Serial I/O Mode

SCK

t

KSO1,2

t

KL1,2

t

SIK1,2

t

KCY1,2

Input data

Output data

t

KH1,2

t

KSI1,2

SB0, 1

t

KSO1,2

43

Serial Transfer Timing

Bus Release Signal Transfer

SCK

SB0, 1

Command Signal Transfer

µ

PD75P3018

t

KCY3, 4

t

KL3, 4

t

KSB

t

SBL

t

SBH

t

SBK

t

KCY3, 4

t

KH3, 4

t

KSO3, 4

t

SIK3, 4

t

KSI3, 4

SCK

SB0, 1

Interrupt Input Timing

INT0,1,2,4

KR0-7

RESET Input Timing

t

KL3, 4

t

KSB

t

INTL

t

SBK

t

INTH

t

KH3, 4

t

KSO3, 4

t

SIK3, 4

t

KSI3, 4

44

RESET

t

RSL

µ

PD75P3018

Data retention characteristics of data memory in STOP mode and at low supply voltage (TA = –40 to +85 °C)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Release signal setup time tSREL 0

µ

s
Oscillation stabilization tWAIT Released by RESET 215/fX ms
wait time

Note 1

Released by interrupt request Note 2 ms

Notes 1. The oscillation stabilization wait time is the time during which the CPU stops operating to prevent unstable

operation when oscillation is started.

2. Set by the basic interval timer mode register (BTM). (Refer to the table below.)

BTM3 BTM2 BTM1 BTM0

fX = 4.19 MHz fX = 6.0 MHz
–0002
–0112
–1012
–1112

20

/fX (approx. 250 ms) 220/fX (approx. 175 ms)

17

/fX (approx. 31.3 ms) 217/fX (approx. 21.8 ms)

15

/fX (approx. 7.81 ms) 215/fX (approx. 5.46 ms)

13

/fX (approx. 1.95 ms) 213/fX (approx. 1.37 ms)

Data Retention Timing (when STOP mode released by RESET)

STOP mode

Data retention mode

V

DD

STOP instruction execution

RESET

V

DDDR

Wait time

Internal reset operation

Oscillation stabilization wait time

t

SREL

Operation mode

t

WAIT

Data Retention Timing (standby release signal: when STOP mode released by interrupt signal)

Oscillation stabilization wait time

V

DD

STOP instruction execution

Standby release signal

(interrupt request)

STOP mode

Data retention mode

V

DDDR

tSREL

tWAIT

Operation mode

45

µ

PD75P3018

DC Programming Characteristics (TA = 25 ± 5 °C, VDD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V, VSS = 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Input voltage high VIH1 Except X1, X2 0.7 VDD VDD V

VIH2 X1, X2 VDD – 0.5 VDD V

Input voltage low VIL1 Except X1, X2 0 0.3 VDD V

VIL2 X1, X2 0 0.4 V
Input leakage current ILI VIN = VIL or VIH 10
Output voltage high VOH IOH = –1 mA VDD – 1.0 V
Output voltage low VOL IOL = 1.6 mA 0.4 V
VDD supply current IDD 30 mA
VPP supply current IPP MD0 = VIL, MD1 = VIH 30 mA

Cautions1.Ensure that VPP does not exceed +13.5 V including overshoot.

2.V

DD must be applied before VPP, and cut after VPP.

µ

A

AC Programming Characteristics (T

Parameter Symbol Note 1 Conditions MIN. TYP. MAX. Unit
Address setup time
MD1 setup time (to MD0Ø)tM1S tOES 2
Data setup time (to MD0Ø)tDS tDS 2
Address hold time
Data hold time (from MD0↑)tDH tDH 2
MD0↑ÆData output float delay time
VPP setup time (to MD3↑)tVPS tVPS 2
VDD setup time (to MD3↑)tVDS tVCS 2
Initial program pulse width tPW tPW 0.95 1.0 1.05 ms
Additional program pulse width tOPW tOPW 0.95 21.0 ms
MD0 setup time (to MD1↑)tM0S tCES 2
MD0ØÆData output delay time
MD1 hold time (from MD0↑)tM1H tOEH 2
MD1 recovery time (from MD0Ø)tM1R tOR 2
Program counter reset time tPCR —10
X1 input high-/low-level width tXH, tXL — 0.125
X1 input frequency fX — 4.19 MHz
Initial mode setting time tI —2
MD3 setup time (to MD1↑)tM3S —2
MD3 hold time (from MD1Ø)tM3H —2
MD3 setup time (to MD0Ø)tM3SR — Program memory read 2
Data output delay time from address
Data output hold time from address
MD3 hold time (from MD0↑)tM3HR — Program memory read 2
MD3ØÆData output float delay time

Note 2

(to MD0Ø)tAS tAS 2

Note 2

(from MD0↑)tAH tAH 2

A = 25 ± 5 °C, VDD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V, VSS = 0 V)

tDF tDF 0 130 ns

tDV tDV MD0 = MD1 = VIL 1

tM1H + tM1R ≥ 50 µs

Note 2

tDAD tACC Program memory read 2

Note 2

tHAD tOH Program memory read 0 130

tDFR — Program memory read 2

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

Notes1.Symbol of corresponding µPD27C256A

2.The internal address signal is incremented by 1 on the 4th rise of the X1 input, and is not connected to a pin.

46

Program Memory Write Timing

t

VPS

V

PP

PP

V

V

DD

t

VDS

VDD+1

V

DD

DD

V

X1

P40-P43
P50-P53

MD0

MD1

MD2

t

I

t

PCR

t

M3S

Data Input

t

DS

t

PW

t

M1S

t

t

M1H

µ

PD75P3018

t

XH

t

XL

Data Output

OH

t

M1R

t

DV

t

DF

t

M0S

Data Input Data Input

t

DS

t

OPW

t

DH

t

AH

t

AS

t

M3H

MD3

Program Memory Read Timing

V

PP

VDD+1

DD

P40-P43
P50-P53

MD0

MD1

PP

V

DD

DD

V

X1

t

I

V

V

t

t

VPS

VDS

t

XH

t

XL

t

HAD

t

DAD

Data Output Data Output

t

DV

t

M3HR

t

DFR

MD2

MD3

t

PCR

t

M3SR

47

10. PACKAGE DRAWINGS

80 PIN PLASTIC QFP ( 14)

µ

PD75P3018

A

B

60

61

F

80

1

G

M

IH

P

N

NOTE

Each lead centerline is located within 0.13
mm (0.005 inch) of its true position (T.P.) at
maximum material condition.

41

40

detail of lead end

C

D

S

Q

21

20

J

K

M

L

ITEM MILLIMETERS INCHES

A
B
C

D
F
G
H

I
J

K

L

M

N

17.2±0.4


14.0±0.2

14.0±0.2

17.2±0.4

0.8

0.8

0.30±0.10

0.13



0.65 (T.P.)


1.6±0.2

0.8±0.2

+0.10

0.15

–0.05

0.10

0.677±0.016

0.551

0.551

0.677±0.016

0.031

0.031

0.012

0.005

0.026 (T.P.)

0.063±0.008

0.031

0.006

0.004

P 2.7 0.106

Q

0.1±0.1

0.004±0.004

S 3.0 MAX. 0.119 MAX.

5°±5°



S80GC-65-3B9-3

+0.009

–0.008
+0.009

–0.008

+0.004

–0.005

+0.009

–0.008

+0.004

–0.003

48

80 PIN PLASTIC TQFP (FINE PITCH) ( 12)

A
B

µ

PD75P3018

60

61

F

80

1

G

H

M

I

41

40

21

20

J

K

P

N

L

NOTE

Each lead centerline is located within 0.10 mm (0.004 inch) of
its true position (T.P.) at maximum material condition.

detail of lead end

C

S

D

Q

R

M

ITEM MILLIMETERS INCHES

A 14.0±0.2 0.551

B 12.0±0.2 0.472

C 12.0±0.2 0.472

D 14.0±0.2 0.551
F

1.25

G 1.25

0.10

+0.05
–0.04

+0.055
–0.045

H 0.22 0.009±0.002

I

J 0.5 (T.P.)
K 1.0±0.2 0.039

L 0.5±0.2 0.020

M 0.145 0.006±0.002

N 0.10 0.004
P 1.05 0.041
Q 0.05±0.05
R5°±5° 5°±5°
S 1.27 MAX. 0.050 MAX.

+0.009
–0.008

+0.009
–0.008

+0.009
–0.008

+0.009
–0.008

0.049

0.049


0.004

0.020 (T.P.)
+0.009

–0.008
+0.008

–0.009



0.002±0.002

P80GK-50-BE9-4

49

11. RECOMMENDED SOLDERING CONDITIONS

*

Solder the µPD75P3018 under the following recommended conditions.
For the details on the recommended soldering conditions, refer to Information Document Semiconductor Device
Mounting Technology Manual (C10535E).
For the soldering methods and conditions other than those recommended, consult NEC.

Table 11-1. Soldering Conditions of Surface Mount Type

µ

PD75P3018

(1) µPD75P3018GC-3B9: 80-pin plastic QFP (14

Soldering Method Soldering Conditions Symbol

Infrared reflow Package peak temperature: 235 °C, Time: 30 seconds max. (210 °C min.), IR35-00-3

Number of times: 3 max.

VPS Package peak temperature: 215 °C, Time: 40 seconds max. (200 °C min.), VP15-00-3

Number of times: 3 max.

Wave soldering Solder temperature: 260 °C max., Time: 10 seconds max., WS60-00-1

Number of times: 1
Preheating temperature: 120 °C max. (package surface temperature)

Pin partial heating Pin temperature: 300 °C max., Time: 3 seconds max. (per side of device) —

¥ ¥

¥ 14 mm)

¥ ¥

Caution Do not use two or more soldering methods in combination (except the pin partial heating method).

(2) µPD75P3018GK-BE9: 80-pin plastic TQFP (fine pitch) (12

Soldering Method Soldering Conditions Symbol

Infrared reflow IR35-107-2

VPS VP15-107-2

Wave soldering WS60-107-1

Pin partial heating —

Package peak temperature: 235 °C, Time: 30 seconds max. (210 °C min.),
Number of times: 2 max., Exposure limit: 7 days
necessary at 125 °C for 10 hours.)

Package peak temperature: 215 °C, Time: 40 seconds max. (200 °C min.),
Number of times: 2 max., Exposure limit: 7 days
necessary at 125 °C for 10 hours.)

Solder temperature: 260 °C max., Time: 10 seconds max.,
Number of times: 1,
Preheating temperature: 120 °C max. (package surface temperature)
Exposure limit: 7 days
hours.)

Pin temperature: 300 °C max., Time: 3 seconds max. (per side of device)

Note

(After that, prebaking is necessary at 125 °C for 10

¥ ¥

¥ 12 mm)

¥ ¥

Note

Note

(After that, prebaking is

(After that, prebaking is

Note

The number of days for storage after the dry pack has been opened. The storage conditions are 25 °C, 65 % RH max.

Caution Do not use two or more soldering methods in combination (except the pin partial heating method).

50

APPENDIX AµPD75316B, 753017 AND 75P3018 FUNCTION LIST

µ

PD75P3018

Parameter

Program memory Mask ROM Mask ROM One-time PROM

Data memory 000H-3FFH (1024 ¥ 4 bits)
CPU 75X Standard 75XL CPU
Instruction When main system 0.95, 1.91, or 15.3 µs • 0.95, 1.91, 3.81, or 15.3 µs (at 4.19 MHz operation)

execution time clock is selected (at 4.19 MHz operation) • 0.67, 1.33, 2.67, or 10.7 µs (at 6.0 MHz operation)

When subsystem 122 µs (at 32.768 kHz operation)
clock is selected

Pin connection 29 to 32 P40 to P43 P40/D0 to P43/D3

34 to 37 P50 to P53 P50/D4 to P53/D7
44 P12/INT2 P12/INT2/TI1/TI2
47 P21 P21/PTO1
48 P22/PCL P22/PCL/PTO2
50 to 53 P30 to P33 P30/MD0 to P33/MD3
57 IC VPP

Stack SBS register None SBS.3 = 1; Mk I mode selection

Stack area 000H-0FFH n00H-nFFH (n = 0-3)
Subroutine call instruction

stack operation Mk II mode: 3-byte stack

Instruction BRA !addr1 Unavailable Mk I mode: unavailable

CALLA !addr1 Mk II mode: available
MOVT XA, @BCDE Available

MOVT XA, @BCXA
BR BCDE
BR BCXA

CALL !addr 3 machine cycles

CALLF !faddr 2 machine cycles
Mask option Yes None
Timer 3 channels: 5 channels:

µ

PD75316B

0000H-3F7FH 0000H-5FFFH 0000H-7FFFH

(16256 ¥ 8 bits) (24576 ¥ 8 bits) (32768 ¥ 8 bits)

2-byte stack Mk I mode: 2-byte stack

• Basic interval timer • Basic interval timer/watchdog timer: 1 channel
: 1 channel • 8-bit timer/event counter: 3 channels

• 8-bit timer/event counter (can be used as 16-bit timer/event counter)
: 1 channel • Watch timer: 1 channel

• Watch timer: 1 channel

µ

PD753017

SBS.3 = 0; Mk II mode selection

Mk I mode: 3 machine cycles, Mk II mode: 4 machine cycles
Mk I mode: 2 machine cycles, Mk II mode: 3 machine cycles

µ

PD75P3018

51

µ

PD75P3018

*

Parameter

Clock output (PCL) F, 524, 262, 65.5 kHz • F, 524, 262, 65.5 kHz

BUZ output (BUZ) 2 kHz • 2, 4, 32 kHz

Serial interface 3 modes are available

SOS register

Register bank selection register (RBS) None Yes
Standby release by INT0 No Yes
Vectored interrupt External: 3, Internal: 3 External: 3, Internal: 5
Supply voltage VDD = 2.0 to 6.0 V VDD = 2.2 to 5.5 V
Operating ambient temperature TA = –40 to +85 °C
Package • 80-pin plastic TQFP (fine pitch) (12 x 12 mm)

Feedback resistor cut flag
(SOS.0)

Sub-oscillator current None Provided
cut flag (SOS.1)

µ

PD75316B

(Main system clock: (Main system clock: at 4.19 MHz operation)
at 4.19 MHz operation) • F, 750, 375, 93.8 kHz

(Main system clock: (Main system clock: at 4.19 MHz operation or
at 4.19 MHz operation) subsystem clock: at 32.768 kHz operation)

• 3-wire serial I/O mode ... MSB/LSB can be selected for transfer top bit

• 2-wire serial I/O mode

• SBI mode
None Provided

• 80-pin plastic QFP (14 x 14 mm)

µ

PD753017

(Main system clock: at 6.0 MHz operation)

• 2.86, 5.72, 45.8 kHz
(Main system clock: at 6.0 MHz operation)

µ

PD75P3018

52

µ

PD75P3018

APPENDIX B DEVELOPMENT TOOLS

The following development tools have been provided for system development using the µPD75P3018. In the 75XL Series,
the relocatable assembler common to series is used in combination with the device file of each type.

RA75X relocatable assembler Host machine Part No. (name)

OS Supply medium

PC-9800 Series MS-DOS

IBM PC/AT
or compatible IBM PCs" 5" 2HC µS7B10RA75X

Device file Host machine Part No. (name)

PC-9800 Series MS-DOS 3.5" 2HD µS5A13DF753017

IBM PC/AT Refer to "OS for 3.5" 2HC µS7B13DF753017
or compatible IBM PCs" 5" 2HC µS7B10DF753017

TM

Refer to "OS for 3.5" 2HC µS7B13RA75X

OS Supply medium

TM

Ver.3.30 to 5" 2HD µS5A10RA75X

Note

Ver.6.2

Ver.3.30 to 5" 2HD µS5A10DF753017

Note

Ver.6.2

3.5" 2HD µS5A13RA75X

*

*

Note Ver. 5.00 or later includes a task swapping function, but this software is not able to use that function.

Remark Operation of the assembler and device file is guaranteed only when using the host machine and OS described

above.

53

*

*

µ

PD75P3018

PROM Write Tools

Hardware PG-1500 This is a PROM programmer that can program single-chip microcontroller with PROM in stand

alone mode or under control of host machine when connected with supplied accessory board
and optional programmer adapter.
It can also program typical PROMs in capacities ranging from 256 K to 4 M bits.

PA-75P316BGC This is a PROM programmer adapter for the µPD75P316BGC and µPD75P3018GC.

It can be used when connected to a PG-1500.

PA-75P316BGK This is a PROM programmer adapter for the µPD75P316BGK and µPD75P3018GK.

It can be used when connected to a PG-1500.

Software PG-1500 controller Connects PG-1500 to host machine with serial and parallel interface and controls PG-1500 on

host machine.
Host machine Part No. (name)

OS Supply medium

PC-9800 Series MS-DOS 3.5" 2HD µS5A13PG1500

Ver.3.30 to 5" 2HD µS5A10PG1500

Note

Ver.6.2
IBM PC/AT Refer to "OS for 3.5" 2HD µS7B13PG1500
or compatible IBM PCs" 5" 2HC µS7B10PG1500

Note Ver. 5.00 or later includes a task swapping function, but this software is not able to use that function.

Remark Operation of the PG-1500 controller is guaranteed only when using the host machine and OS described above.

54

µ

PD75P3018

Debugging Tools

In-circuit emulators (IE-75000-R and IE-75001-R) are provided as program debugging tools for the µPD75P3018.
Various system configurations using these in-circuit emulators are listed below.

Hardware IE-75000-R

IE-75001-R The IE-75001-R is an in-circuit emulator to be used for hardware and software debugging during

IE-75300-R-EM

EP-753018GC-R This is an emulation probe for the µPD75P3018GC.

EP-753018GK-R This is an emulation probe for the µPD75P3018GK.

Software IE control program This program can control the IE-75000-R or IE-75001-R on a host machine when connected to

Note 1

EV-9200GC-80 It includes a 80-pin conversion socket (EV-9200GC-80) to facilitate connections

EV-9500GK-80 It includes a 80-pin conversion adapter (EV-9500GK-80) to facilitate connections with target

The IE-75000-R is an in-circuit emulator to be used for hardware and software debugging during
development of application systems using the 75X or 75XL Series products.
For development of the µPD75P3018, the IE-75000-R is used with optional emulation board (IE­75300-R-EM) and emulation probe (EP-753018GC-R or EP-753018GK-R).
Highly efficient debugging can be performed when connected to host machine and PROM
programmer.
The IE-75000-R includes a connected emulation board (IE-75000-R-EM).

development of application systems using the 75X or 75XL Series products.
The IE-75001-R is used with optional emulation board (IE-75300-R-EM) and emulation probe
(EP-753018GC-R or EP-753018GK-R).
Highly efficient debugging can be performed when connected to host machine and PROM
programmer.

Note 2

This is an emulation board for evaluating application systems using the µPD75P3018.
It is used in combination with the IE-75000-R or IE-75001-R.

When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM.

with target system.

When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM.

system.

the IE-75000-R or IE-75001-R via an RS-232-C or Centronics interface.
Host machine Part No. (name)

OS Supply medium

PC-9800 Series MS-DOS 3.5" 2HD µS5A13IE75X

Ver.3.30 to 5" 2HD µS5A10IE75X

Note 3

Ver.6.2
IBM PC/AT Refer to "OS for 3.5" 2HC µS7B13IE75X
or compatible IBM PCs" 5" 2HC µS7B10IE75X

*

Notes 1. This is a maintenance product.

2. The IE-75300-R-EM is sold separately.

3. Ver. 5.00 or later includes a task swapping function, but this software is not able to use that function.

Remark Operation of the IE control program is guaranteed only when using the host machine and OS described above.

55

OS for IBM PCs

The following operating systems for the IBM PC are supported.

OS Version

PC DOS

*

MS-DOS Ver.5.0 to Ver.6.22

*
*

Caution Ver. 5.0 or later includes a task swapping function, but this software is not able to use that function.

IBM DOS

TM

TM

Ver.3.1 to Ver.6.3

5.0/V to 6.2/V
J5.02/V

µ

PD75P3018

56

µ

PD75P3018

APPENDIX C RELATED DOCUMENTS

The related documents indicated in this publication may include preliminary versions. However, preliminary versions are
not marked as such.

Device Related Documents

Document Name

µ

PD753012, 753016, 753017 Data Sheet IC-9016 U10140E

µ

PD75P3018 Data Sheet U10956J U10956E

µ

PD753017 User's Manual U11282J IEU-1425

µ

PD753017 Instruction Table IEM-5598 —

75XL Series Selection Guide U10453J U10453E

Japanese English

Development Tool Related Documents

Document Name

IE-75000-R/IE-75001-R User's Manual EEU-846 EEU-1416

Hardware

Software PG-1500 Controller User's Manual PC-9800 Series EEU-704 EEU-1291

IE-75300-R-EM User's Manual U11354J EEU-1493
EP-753017GC/GK-R User's Manual EEU-967 IEU-1495
PG-1500 User's Manual EEU-651 EEU-1335
RA75X Assembler Package Operation EEU-731 EEU-1346
User's Manual Language EEU-730 EEU-1363

(MS-DOS) base
IBM PC Series EEU-5008 U10540E

(PC DOS) base

Japanese English

Document No.

(This document)

Document No.

*

Other Related Documents

Document Name

IC Package Manual C10943X
Semiconductor Device Mounting Technology Manual C10535J C10535E
Quality Grades on NEC Semiconductor Devices IEI-620 IEI-1209
NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E
Electrostatic Discharge (ESD) Test MEM-539 —
Guide to Quality Assurance for Semiconductor Devices MEI-603 MEI-1202
Guide for Products Related to Microcomputer: Other Companies MEI-604 —

Japanese English

Document No.

Caution The above related documents are subject to change without notice. For design purpose, etc., be sure

to use the latest documents.

57

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction of

the gate oxide and ultimately degrade the device operation. Steps must be taken
to stop generation of static electricity as much as possible, and quickly dissipate
it once, when it has occurred. Environmental control must be adequate. When
it is dry, humidifier should be used. It is recommended to avoid using insulators
that easily build static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive
material. All test and measurement tools including work bench and floor should
be grounded. The operator should be grounded using wrist strap. Semiconductor
devices must not be touched with bare hands. Similar precautions need to be
taken for PW boards with semiconductor devices on it.

µ

PD75P3018

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input level
may be generated due to noise, etc., hence causing malfunction. CMOS devices
behave differently than Bipolar or NMOS devices. Input levels of CMOS devices
must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have
a possibility of being an output pin. All handling related to the unused pins must
be judged device by device and related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production

process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset function
have not yet been initialized. Hence, power-on does not guarantee out-pin
levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after
power-on for devices having reset function.

58

µ

PD75P3018

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

• Device availability

• Ordering information

• Product release schedule

• Availability of related technical literature

• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)

• Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

NEC Electronics Inc. (U.S.)

Mountain View, California
Tel: [phone]
Fax: [phone]

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: [phone]
Fax: [phone]

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel:[phone]
Fax: [phone]

NEC Electronics (France) S.A.

France
Tel:[phone]
Fax: [phone]

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel:[phone]
Fax: [phone]

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: [phone]
Fax: [phone]

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: [phone]
Fax: [phone]

NEC Electronics Italiana s.r.1.

Milano, Italy
Tel: [phone]
Fax: [phone]

NEC Electronics (France) S.A.

Spain Office
Madrid, Spain
Tel: [phone]
Fax: [phone]

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby Sweden
Tel: [phone]
Fax: [phone]

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130
Tel:[phone]
Fax: [phone]

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: [phone]
Fax: [phone]

NEC do Brasil S.A.

Sao Paulo-SP, Brasil
Tel: [phone]
Fax: [phone]

J96. 3

59

µ

PD75P3018

MS-DOS is a trademark of Microsoft Corporation.
IBM DOS, PC DOS, and PC/AT are trademarks of International Business Machines Corporation.

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.

No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.

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