The µPD63310 is an LSI that features two channels each of on-chip 16-bit ADC and DAC circuits for mutual conversion
between digital signals and audio signals (having a maximum signal bandwidth of 24 kHz).
The analog signal input block enables mixed input of four different stereo signals and one monaural signal, and the
µ
volume of each signal can be controlled before mixing. The
(mic amps) and gain is adjustable between 10 and 30 dB.
The analog signal output block enables mixed output of analog signals output by the DAC and four different stereo
analog signals, and the volume of each signal can be controlled before mixing.
The digital audio signal I/O block supports a serial interface for audio applications (two’s complement, MSB first).
A 6-bit parallel port are used for the various volume settings, with volume settings selectable (in 1.5-dB steps) from –
46.5 dB to 0 dB, as well as a mute setting.
PD63310 also features two on-chip microphone amplifiers
FEATURES
• Two channels each of ∆Σ type ADC and DAC
• On-chip mixing circuit in analog I/O block
• Low-noise mic amps for two channels on chip
• On-chip reference voltage power supply (1.4 V TYP.)
• ADC and DAC digital filter characteristics
Pass band ripple: ±0.1 dB (0 to 0.454 fs) for ADC and DAC
Stop band attenuation : 75 dB (0.546 fs or above) for ADC and DAC
• Sampling frequency (fs): 2 to 48 kHz (256-fs master clock is input from an external source)
• Low voltage operation: +3 to +5.5 V single power supply
• Wide operating ambient temperature: –20 to +80°C
• Low power consumption: 120 mW (when using 3-V power supply), 250 mW (when using 5-V power supply)
• 80-pin plastic TQFP
RECOMMENDED USES
• Speech recognition system, including car navigation system
1IN1RIR-channel analog audio signal input pin 1
2IN2RIR-channel analog audio signal input pin 2
3IN3RIR-channel analog audio signal input pin 3
4IN4RIR-channel analog audio signal input pin 4
5IN5IAnalog audio signal (monaural) input pin. This channel accepts audio input
which is input to both left and right channels on the chip.
6IN4LIL-channel analog audio signal input pin 4
7IN3LIL-channel analog audio signal input pin 3
8IN2LIL-channel analog audio signal input pin 2
9IN1LIL-channel analog audio signal input pin 1
10-15NC—No connection
16MICOLOL-channel mic amp output pin. If the L-channel mic amp is not being used,
connect this pin to MICNL pin.
17MICNLIL-channel mic amp inverting input pin. If the L-channel mic amp is not being
used, connect this pin to MICOL pin.
18MICPLIL-channel mic amp noninverting input pin. If the L-channel mic amp is not
being used, connect this pin to VXLO pin.
19RBWOOutput pin for signal that specifies the bus driver’s direction. Output is at
high level when DATA5 to DATA0 are input pins and is at low level when
DATA5 to DATA0 are output pins. If not used, leave unconnected.
20OEBOBus driver enable signal output pin. When data input to DATA5 to DATA0
is enabled, output is at low level. If not used, leave unconnected.
21, 22NC—No connection
23WBIInput pin for parallel interface’s data write signal. Used for input of low-level
signals when addresses are written to the volume setting register and when
data is written.
24RBIInput pin for parallel interface’s data read signal. Used for input of low-level
signals when data is read from the volume setting register.
25CSBIInput pin for parallel interface’s chip select signal. Active low. When the
input signal is at high level, DATA5 to DATA0 are set for high impedance.
26SELRIInput pin for signal that specifies the target register for parallel data input and
output. Specifies an address register when the input signal is at low level,
or a data register when the input signal is at high level.
27, 28TEST1, TEST2ITest mode setting pins. These pins set the test mode when at high level.
When not used (i.e., during normal operation mode), connect these pins to
GND.
29RSTBIReset signal input pin. A reset occurs when a low pulse (pulse width of 1/
(8 fs) or greater) is input after starting MCLK. The case when a reset is
necessary is not only power-on but also an occurrence of disturbance in
master clock due to changing fS (sampling frequency). When input is at low
level, power down mode is set to reduce power consumption.
30NC—No connection
(1/3)
4
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PD63310
(2/3)
Pin NumberPin NameI/OFunction
31MCLKIMaster clock input pin. Used for input of 256-fs clock (duty: 40 to 60%).
32LRCLKOSerial interface’s frame sync clock output pin.
Used for L channel data I/O when LRCLK = low level
Used for R channel data I/O when LRCLK = high level
33BCLKOSerial interface’s bit sync clock output pin.
Used for I/O of audio data from SI and SO in sync with BCLK. BCLK is
generated on-chip as MCLK divided by eight.
34SIISerial interface’s data input pin. Used for serial input (synchronized with
BCLK) of audio data (two’s complement, MSB first).
35NC—No connection
36SOOSerial interface’s data output pin. Used for serial output (synchronized with
BCLK) of audio data (two’s complement, MSB first).
37DVDD—Digital power supply pin. Used for input voltage range of +3 to +5.5 V.
38-40NC—No connection
41, 42DGND1, DGND2GDigital ground pins.
43-48DATA5-DATA0I/OParallel data I/O pins. Used for input/output of address data and volume
setting data.
49-53NC—No connection
54DACROR-channel DAC output pin. When this pin is used, the R-channel DAC output
can be monitored without attenuation regardless of the volume setting.
55OUTROR-channel analog audio output pin.
56DACLOL-channel DAC output pin. When this pin is used, the L-channel DAC output
can be monitored without attenuation regardless of the volume setting.
57OUTLOL-channel analog audio output pin.
58, 59AGND5, AGND4GAnalog ground pins.
60AVDD—Analog power supply pin. Used for input voltage range of +3 to +5.5 V.
61, 62NC—No connection
63VRRIIReference voltage input pin for R-channel DAC. This pin is usually connected
to VRRO pin.
64VRROOReference voltage output pin for R-channel DAC. Output is 1.4 V (TYP.).
Connects to analog GND via a bypass capacitor.
65VRLIIReference voltage input pin for L-channel DAC. This pin is usually connected
to VRLO pin.
66VRLOOReference voltage output pin for L-channel DAC. Output is 1.4 V (TYP.).
Connects to analog GND via a bypass capacitor.
67VXRIIReference voltage input pin for R-channel ADC. This pin is usually connected
to VXRO pin.
68VXROOReference voltage output pin for R-channel ADC. Output is 1.4 V (TYP.).
Connects to analog GND via a bypass capacitor.
69VXLIIReference voltage input pin for L-channel ADC. This pin is usually connected
to VXLO pin.
70NC—No connection
5
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PD63310
(3/3)
Pin NumberPin NameI/OFunction
71VXLOOReference voltage output pin for L-channel ADC. Output is 1.4 V (TYP.).
Connects to analog GND via a bypass capacitor.
72AGND3GAnalog ground pin.
73NC—No connection
74, 75AGND2, AGND1GAnalog ground pins.
76MICPRIR-channel mic amp noninverting input pin. If the R-channel mic amp is not
being used, connect this pin to VXRO pin.
77MICNRIR-channel mic amp inverting input pin. If the R-channel mic amp is not being
used, connect this pin to MICOR pin.
78MICOROR-channel mic amp output pin. If the R-channel mic amp is not being used,
connect this pin to MICNR pin.
79, 80NC—No connection
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PD63310
1. DESCRIPTION OF OPERATIONS
1.1 Analog Input Block
The analog input block enables signal input from two channels. Four different stereo signals (IN1 to IN4) and a
monaural signal (IN5) can be mixed and input via these channels. The volume can be adjusted for each analog signal,
and the sum of the volume settings is input to the ADC. A 6-bit signal is used to adjust the volume within an adjustment
range (in 1.5-dB steps) from –46.5 dB to 0 dB, plus a mute setting. A low-noise mic amp (variable gain width: 10 to 30
dB) is provided on-chip for mic input.
1.2 Analog Output Block
The analog output block enables signal output from two channels. Five different analog signals (IN1 to IN4 and DAC)
can be mixed and output via these channels. The volume can be adjusted for each analog signal, and the sum of the
volume settings is output (via OUTL and OUTR pins). A 6-bit signal is used to adjust the volume within an adjustment
range (in 1.5-dB steps) from –46.5 dB to 0 dB, plus a mute setting. The output from the DAC (via DACL and DACR pins)
can be monitored directly.
1.3 Digital Interface
A serial interface for audio is supported for input and output of digital audio data (two’s complement, MSB first).
BCLK and LRCLK are automatically generated on chip from the master clock that is supplied to MCLK pin from an
external source. BCLK and LRCLK are used by the ADC and DAC. In other words, the ADC’s and DAC’s sampling
frequency is determined based on the master clock and cannot be set independently of it.
A parallel interface is used for input and output of the 6-bit data used for volume adjustments. The target registers for
parallel data I/O are selected via the SELR pin. This pin selects an address register when at low level and a data register
when at high level.
OEB is output as the bus driver’s enable signal and RBW is output as the bus driver’s direction specification signal.
Use this pin as necessary. If it is not used, leave it unconnected.
When the clock (data) input to the MCLK and SI pins has been stopped, set these pins to either high level or low level
(if necessary, connect via a resistance to DV
DD or DGND).
(1) Serial interface
BCLK
LRCLK
SI, SO15 14 13 12
(2) Parallel interface
RB
WB
(I)
(I)
(I)
(O)
(O)
(I/O)DATA5-
CSB
OEB
RBW
DATA0
L-channel data
4321015141312
R-channel data
43210
LSBLSB
7
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PD63310
1.4 Volume Setting Register Addresses
After the power is turned on and a reset has been input, all volume settings are set to mute mode. Therefore, it may
be necessary to specify volume settings before inputting signals. Write data to the volume setting registers that correspond
to the analog input pins and analog output pins to be used.
Since the ADC’s full scale analog input signal amplitude voltage is 1.4 V (TYP.), it may be necessary to specify a
volume setting whereby the signal amplitude’s maximum voltage (after mixing) is no more than 1.4 V, especially when
several analog signals are input to the ADC after mixing.
The addresses of the various volume setting registers are specified via the 6-bit parallel data that is input from the
DATA5 to DATA0 pins during low-level input to the SELR pin. The volume setting registers corresponding to these
addresses are listed below.
0: IN1L control register
1: IN1R control register
2: IN2L control register
3: IN2R control register
4: IN3L control register
5: IN3R control register
6: IN4L control register
7: IN4R control register
8: IN5 control register
9: IN1L-OUTL control register
10 : IN1R-OUTR control register
1 1 : IN2L-OUTL control register
12 : IN2R-OUTR control register
13 : IN3L-OUTL control register
14 : IN3R-OUTR control register
15 : IN4L-OUTL control register
16 : IN4R-OUTR control register
17 : DACL-OUTL control register
18 : DACR-OUTR control register
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PD63310
1.5 Volume Setting Register Data (Command Types)
The data in the volume setting registers is written and read based on 6-bit parallel data that is input and output via the
DATA5 to DA T A0 pins when the SELR pin is set for high level input. The data (commands) in the various volume setting
registers are described below.
0:D5D4D3D2D1D0
D4 to D0 indicate the data used to control gain in the IN1L register’s input signal, with codes corresponding
to the gain levels listed in Table 1-1 below. When D5 is “1”, mute mode is set.
Table 1-1. Correspondence of Codes and Gain Levels
D5D4D3D2D1D0Gain
0000000 dB
000001–1.5 dB
000010–3.0 dB
|||||||
011110–45.0 dB
011111–46.5 dB
100000MUTE
1ЧЧЧЧЧMUTE
Note Default value
Remark × : Don’t care
Note
1:D5D4D3D2D1D0
D4 to D0 indicate the data used to control gain in the IN1R register’s input signal, with codes corresponding
to the gain levels listed in Table 1-1. Mute mode is set when D5 = 1.
2:D5D4D3D2D1D0
D4 to D0 indicate the data used to control gain in the IN2L register’s input signal, with codes corresponding
to the gain levels listed in Table 1-1. Mute mode is set when D5 = 1.
3:D5D4D3D2D1D0
D4 to D0 indicate the data used to control gain in the IN2R register’s input signal, with codes corresponding
to the gain levels listed in Table 1-1. Mute mode is set when D5 = 1.
4:D5D4D3D2D1D0
D4 to D0 indicate the data used to control gain in the IN3L register’s input signal, with codes corresponding
to the gain levels listed in Table 1-1. Mute mode is set when D5 = 1.
5:D5D4D3D2D1D0
D4 to D0 indicate the data used to control gain in the IN3R register’s input signal, with codes corresponding
to the gain levels listed in Table 1-1. Mute mode is set when D5 = 1.
6:D5D4D3D2D1D0
D4 to D0 indicate the data used to control gain in the IN4L register’s input signal, with codes corresponding
to the gain levels listed in Table 1-1. Mute mode is set when D5 = 1.
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