NEC UPD61P24CS, UPD61P24GS Datasheet

DATA SHEET

MOS INTEGRATED CIRCUIT

PD61P24

4-BIT SINGLE-CHIP MICROCONTROLLER

FOR REMOTE CONTROL TRANSMISSION

DESCRIPTION

The µPD61P24 is a 4-bit single-chip microcontroller for infrared remote controllers for TVs, VCRs, stereos, cassette

decks, air conditioners, etc.

As the

and for small-scale production of such systems.

The functions of the

manual before designing your system.

PD61P24 is user-programmable, it is ideal for evaluation of programs running in a µPD6124A or 6600A,

PD61P24 are described in detail in the following User’s Manual. Be sure to read this

PD612X Series User’s Manual: IEP-1083

FEATURES

•Transmitter for programmable infrared remote controller

•19 types of instructions

•Instruction execution time: 17.6 ramic resonator)

•On-chip one-time PROM: 1002 × 10 bits

•Data memory (RAM) capacity : 32 × 5 bits

•9-bit programmable timer: 1 channel

•I/O pins (K

•Input pins (K

CautionTo use the NEC transmission format, ask NEC to supply the custom code.

I/O): 8 pins

I): 4 pins

Do no use R0 when using a register as an operand of the branch instruction.

s (with 455-kHz ce-

•Serial input pins (S-IN): 1 pin

•Transmission-in-progress indication pin (S-OUT): 1 pin

•Transmit carrier frequency (REM)

OSC/12, fOSC/8

•Standby operation (HALT/STOP mode)

•Low power consumption

•Current consumption in STOP mode (T 1 µA MAX.

•Low-voltage operation: VDD = 2.2 to 5.5 V

A = 25°C)

DocumentNo. U12629EJ4V0DS00 (4th edition) Previous No. IC-2876 Date Published July 1997 N Printed in Japan

The information in this document is subject to change without notice.

The mark shows major revised points.

1997

ORDERING INFORMATION

Part Number Package

PD61P24CS 20-pin plastic shrink DIP (300 mil)

PD61P24GS 20-pin plastic SOP (300 mil)

PIN CONFIGURATION (Top View)

(1) Normal operating mode (2) PROM programming mode

PD61P24

I/O1

I/O0

S-IN

S-OUT

REM

OSC-OUT

OSC-IN

1 2 3 4 5 6 7 8 9

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

(Open) (Open)

(Open)

4 5 6

7 8

CLK

10(L) 11 MD3

20 19 18 17 16 15 14 13 12 MD2

Caution Round brackets ( ) indicate the pins not used in the PROM programming mode.

L : Connect each of these pins to GND via a resistor (470 Ω). Open: Leave these pins open.

D2 D3 D4 D5 D6 D7 MD0 MD1

BLOCK DIAGRAM

PD61P24

OSC

OSC-OUT

TIMER

(L)

MOD

TIMER

(H)

10 bits

ROM D.P.

PC(L)

PC(H)

CNTL

L H

1002 × 10 bits

M P X

ALU

One-Time

PROM

(L)

One-Time

PROM

(H)

ACC

S-INREMS-OUTOSC-IN

KEY

OUT(L)

ADD DEC

KEY

OUT(H)

I/O0-KI/O7

32 × 5 bits

RAM

M P X

RAM

KEY

K -K

I0 I3

CNTL

(L)

Watchdog

timer

function

ACK

(H)

1. PROGRAM COUNTER (PC) ……… 10 BITS

The program counter (PC) is a binary counter, which holds the address information for the program memory.

Figure 1-1. Program Counter Organization

PD61P24

PC7PC6PC5PC4PC3PC2PC1PC

Normally, the program counter contents are automatically incremented each time an instruction is executed,

according to the number of instruction bytes.

When executing a jump instruction (JMP0, JC, JF), the program counter indicates the jump destination. Immediate data or the data memory contents are loaded to all or some bits of the PC. When executing the call instruction (CALL0), the PC contents are incremented (+1) and saved into the stack

memory. Then, a value needed for each jump instruction will be loaded.

When executing the return instruction (RET), the stack memory contents are double incremented (+2) and loaded

into the PC.

When “all clear” is input or on reset, the PC contents are cleared to “000H”.

2. STACK POINTER (SP) ……… 2 BITS

This 2-bit register holds the start address information for the stack area. The stack area is shared with the data

memory.

The SP contents are incremented, when the call instruction (CALL0) is executed. They are decremented, when

the return instruction (RET) is executed.

The stack pointer is cleared to “00B” after reset or “all clear” is input, and indicates the highest address FH for

the data memory as the stack area.

The figure below shows the relationship for the stack pointer and the data memory area.

Data memory

RC R RE RF

(SP)

11B 10B

01B 00B

If the stack pointer overflows or underflows, it is determined that the CPU overflows, and the PC internal reset

signal will be generated.

3. PROGRAM MEMORY (ROM) ……… 1002 STEPS × 10 BITS

The program memory (ROM) is configured in 10 bits steps. It is addressed by the program counter. Program and table data are stored in the program memory.

Figure 3-1. Program Memory Map

000H

0FFH

100H

1FFH

200H

2FFH

300H

3E9H

3EAH

3FFH

Test program area

PD61P24

4. DATA MEMORY (RAM) ……… 32 WORDS × 5 BITS

The data memory is a RAM of 32 words × 5 bits. The data memory stores processing data. In some cases, the

data memory is processed in 8-bit units. R0 may be used as the data pointer for the ROM.

After power application, the RAM will be undefined. The RAM retains the previous data on reset.

Figure 4-1. Data Memory Organization

SP–3 SP–2 SP–1 SP–0

Caution Avoid using the RAM areas RD, RE, and RF in a CALL routine as much as possible because these

areas are also used as stack memory areas (to prevent program hang-up in case the value of the SP is destroyed due to some reason such as noise). When using these RAM areas as general-purpose RAM areas, be sure to include stack pointer checking in the main routine.

5. DATA POINTER (R0)

R0 (R10, R00) for the data memory can serve as the data pointer for the ROM. R0 specifies the low-order 8 bits in the ROM address. The high-order 2 bits in the ROM address are specified

by the control register.

Table referencing for ROM data can be easily executed by calling the ROM contents by setting the ROM address

to the data pointer.

On reset or “all clear” is input, it becomes undefined.

Figure 5-1. Data Pointer Organization

PD61P24

Control registers (P )

6. ACCUMULATOR (A) ……… 4 BITS

The accumulator (A) is a 4-bit register. The accumulator plays a major role in each operation. On reset or “all clear” is input, it becomes undefined.

Figure 6-1. Accumulator Organization

7. ARITHMETIC LOGIC UNIT (ALU) ……… 4 BITS

The arithmetic logic unit (ALU) is a 4-bit operation circuit, and executes simple operations, such as arithmetic

operations.

8. FLAGS

(1) Status flag

When the status for each pin is checked by the STTS instruction, if the condition coincides with the condition specified by the STTS instruction, the status flag (F) is set (to 1). On reset or “all clear” is input, it becomes undefined.

(2) Carry flag

When the INC (increment) instruction or the RL (rotate left) instruction is executed, if a carry is generated from the MSB for the accumulator, the carry flag (C) is set (to 1). The carry flag (C) is also set (to 1), if the contents for the accumulator are “FH”, when the SCAF instruction is executed. On reset or “all clear” is input, it becomes undefined.

PD61P24

9. SYSTEM CLOCK GENERATOR

The system clock generator consists of a resonator, which uses a ceramic resonator (400kHz to 500kHz).

Figure 9-1. System Clock Generator

OSC-IN

OSC-OUT

In the STOP mode (oscillation stop HALT instruction), the oscillator in the system clock generator stops its

operation, and the system clock ø is stopped.

STOP mode

System clock

PD61P24

10. TIMER

The timer block determines the transmission output pattern. The timer consists of 10 bits, of which 9 bits serve as the 9-bit down counter and the remaining 1 bit serves as the 1-bit latch, which determines the carrier output validity.

The 9-bit down counter is decremented (–1) every 8/f starting down count operation. Down counting stops after all of the 9 bits become 0. When down counting is stopped, the signal indicating that the timer operation has stopped, is output. If the CPU is at standby (HALT TIMER) for the timer operation completion, the standby (HALT) condition is released and the next instruction will be executed. If the next instruction again sets the value of the down counter, down counting continues without any error (the carrier output of the REM pin is not affected).

Set the down count time according to the following calculation; (set value (HEX) + 1) × 8/f to the timer is done by the timer manipulation instruction.

When the down counter is operating, the remote control transmission carrier can be output to the REM pin. Whether or not to output the carrier can be selected by the MSB for the timer register block. Set “1”, when outputting the carrier, or “0”, when not outputting the carrier.

If all the down counter bits become “0”, when outputting the carrier, the carrier output will be stopped. When not outputting the carrier, the REM pin output will become low level.

A signal in synchronization with the REM output is output to the S-OUT pin. However, the waveform for the SOUT pin is low, when the carrier is being output to the REM pin, or it is high, when the carrier is not being output to the REM pin.

If the HALT instruction, which initiates the oscillation stop mode, is executed when the down counter is operating, the oscillation stop mode is initiated after down counting is stopped (after 0).

Timer operation STOP/RUN is controlled by the control register (P

At reset (all clear) time, the REM pin goes low and S-OUT pin goes high. All 10 bits of the timer are cleared to 000H.

OSC(s) in synchronization with the machine cycle, after

OSC. Setting the value

1). (Refer to 13. CONTROL REGISTER (P1).)

Caution Because the timer clock is not synchronized with the carrier output, the pulse width may be

shortened at the beginning and end of the carrier output.

Figure 10-1. Timer Block Organization

Set by timer mainpulation instruction

MSB

fosc/8

S-OUT

REM

1/0

Clear

Carrier (fosc/12, fosc/8) Selected by control register

9-bit down counter

Zero detection circuit

D of control register P

(Timer RUN/STOP)

PD61P24

11. PIN FUNCTIONS

11.1 KI/O Pin (P0)

This is the 8-bit I/O pin for key-scan output. When the control register (P1) is set for the input port, the port can be used as an 8-bit input pin. When the port is set for the input mode, all of these pins are pulled down to the VSS level inside the LSI.

At reset (all cleared), the value of I/O mode and output latch becomes undefined.

Figure 11-1. K

I/O7

I/O6

I/O5

11.2 KI/O Pull-Down Resistor Configuration

Input/output selection

I/O Pin Organization

I/O4

I/O3

(P )

I/O1

Control register

I/O0

I/O2

P-ch

Output signal

Input signal

CMOS

Pull-down resistor

N-ch

When KI/O is set to the input mode, pull-down resistor R is turned on.

N-ch

11.3 KI Pin (P12)

This is the 4-bit pin for key input. All of these pins are pulled down to the VSS level by PLA data.

PD61P24

Figure 11-2. K

11.4 KI Pull-Down Resistor Configuration

I Pin Organization

P-ch

Pin Input signal

PLA KI pull-down

resistor switch

N-ch

Pull-down resistor

When the pull-down resistor switch is turned on (set 1) by PLA data, pull-down resistor R is turned on.

PD61P24

11.5 S-OUT Pin

By going low whenever the carrier frequency is output from the REM pin, the S-OUT pin indicates that communication is in progress.

The S-OUT pin is CMOS output.

The S-OUT pin goes high on reset.

11.6 S-IN Pin (D

0 bit of P1)

To input serial data, use the S-IN pin. When control register (P1) is set to serial input mode, the S-IN pin is connected as an input to the LSB of the accumulator; the S-IN pin is pulled down to the V

SS level within the LSI.

In this state, if the rotate-left accumulator instruction (RL A) is executed, the data on the S-IN pin is copied to the LSB of the accumulator.

If the control register is released from serial input mode, the S-IN pin goes into a high-impedance state, but no through current flows internally. When the RL A instruction is executed, the MSB is copied to the LSB.

At reset (all cleared), the S-IN pin goes into a high-impedance state.

Figure 11-3. Configuration of the S-IN Pin

Control register

S-IN

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