NEC PD78056FY, PD78058F-A, PD78058FY, PD78P058FY, PD78056F User Manual

User’s Manual

µ

PD78058F, 78058FY Subseries

8-Bit Single-Chip Microcontrollers

µ

PD78056F

µ

PD78058F

µ

PD78P058F

µ

PD78058F(A)

µ

PD78056FY

µ

PD78058FY

µ

PD78P058FY

µ

PD78058FY(A)

Document No. U12068EJ2V0UM00 (2nd edition)
Date Published April 1998 N CP (K)

©

Printed in Japan

1997

[MEMO]

2

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static
electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental
control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid
using insulators that easily build static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive material. All test and
measurement tools including work bench and floor should be grounded. The operator should be
grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar
precautions need to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input
levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each
unused pin should be connected to V
possibility of being an output pin. All handling related to the unused pins must be judged device
by device and related specifications governing the devices.

DD or GND with a resistor, if it is considered to have a

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until
the reset signal is received. Reset operation must be executed immediately after power-on for
devices having reset function.

FIP, EEPROM, and IEBus are trademarks of NEC Corporation.
MS-DOS, Windows, and WindowsNT are either registered trademarks or trademarks of Microsoft Corpo­ration in the United States and/or other countries.
IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation.
HP9000 Series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
Ethernet is a trademark of XEROX Corporation.
NEWS and NEWS-OS are trademarks of SONY Corporation.
OSF/Motif is a trademark of Open Software Foundation, Inc.
TRON is an abbreviation of The Realtime Operating System Nucleus.
ITRON is an abbreviation of Industrial TRON.

3

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without
governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country
other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.

The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.

Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these

components in an I

2

C system, provided that the system conforms to the I2C Standard Specification as defined

by Philips.

The information in this document is subject to change without notice.

No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated “quality assurance program“ for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.

M7 96.5

4

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

• Device availability

• Ordering information

• Product release schedule

• Availability of related technical literature

• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)

• Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: [phone]

800-366-9782

Fax: [phone]

800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: [phone]
Fax: [phone]

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: [phone]
Fax: [phone]

NEC Electronics Italiana s.r.1.

Milano, Italy
Tel: [phone]
Fax: [phone]

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel:[phone]
Fax: [phone]

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel:[phone]
Fax: [phone]

NEC Electronics (France) S.A.

Spain Office
Madrid, Spain
Tel: [phone]
Fax: [phone]

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: [phone]
Fax: [phone]

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel:[phone]
Fax: [phone]

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: [phone]
Fax: [phone]

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130
Tel:[phone]
Fax: [phone]

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: [phone]
Fax: [phone]

NEC do Brasil S.A.

Cumbica-Guarulhos-SP, Brasil
Tel: [phone]
Fax: [phone]

J98. 2

5

MAJOR REVISIONS IN THIS EDITION

Page Major Revision from Previous Edition

Throughout The following products have already been developed:

µ

PD78056FGC-×××-8BT, 78058FGC-×××-8BT, 78P058FGC-8BT, 78056FYGC-×××-8BT,

78058FYGC-×××-8BT

P133 to The block diagrams of the following ports were changed.
P137, P143 Figures 6-5 and 6-7 P20, P21, P23 to P26 Block Diagram, Figures 6-6 and 6-8 P22 and P27 Block

Diagram, Figure 6-9 P30 to P37 Block Diagram, Figure 6-16 P71 and P72 Block Diagram
P159 Table 7-2 Relationship between CPU Clock and Minimum Instruction Execution Time was added.
P230, P235 Figures 9-10 and 9-13 Square-Wave Output Operation Timing were added.
P295 Note related to operation controls when using the SBI mode of serial interface channel 0 was added.
P297 Note related to BSYE in Figure 16-5 Serial Bus Interface Control Register Format was changed.
P308 Cautions were added to 16.4.3 (2) (a) Bus release signal (REL), and (b) Command signal (CMD)
P435, P436 CSCK was deleted from Figure 19-1 Serial Interface Channel 2 Block Diagram, and Figure 19-2

Baud Rate Generator Block Diagram.
P438 Figure 19-3 Serial Operating Mode Register 2 Format was changed.
P440 Table 19-2 Serial Interface Channel 2 Operating Mode Settings (2) 3-wire serial I/O mode was

P459 Figure 19-10 Receive Error Timing was changed.
P468 19.4.4 Restrictions on using UART mode was added.
P565 APPENDIX A DIFFERENCES AMONG µPD78054, 78058F, AND 780058 SUBSERIES was added.
P567 APPENDIX B DEVELOPMENT TOOLS

P582 APPENDIX C EMBEDDED SOFTWARE

P591 APPENDIX E REVISION HISTORY was added.

changed.

Overall revision: Contents were adapted to correspond to in-circuit emulators IE-78K0-NS and

IE-78001-R-A

Overall revision: Fuzzy inference development support system was deleted.

The mark shows major revised points.

6

PREFACE

Readers This manual has been prepared for user engineers who want to understand the

functions of the µPD78058F and 78058FY Subseries and design and develop its
application systems and programs.
Affected versions are each of the versions in the following Subseries.

µ

PD78058F Subseries :µPD78056F, 78058F, 78P058F, 78058F(A)

µ

PD78058FY Subseries : µPD78056FY, 78058FY, 78P058FY, 78058FY(A)

Purpose This manual is intended for users to understand the functions described in the

Organization below.

µ

Organization The

PD78058F, 78058FY Subseries manual is organized by two volumes: this

manual and the instruction edition (common to the 78K/0 Series).

µ

PD78058F, 78058FY

Subseries
User’s Manual
(This Manual)

78K/0 Series

User’s Manual

Instructions

Pin functions CPU functions
Internal block functions Instruction set
Interrupt Explanation of each instruction
Other on-chip peripheral functions

7

How to Read This Manual Before reading this manual, you should have general knowledge of electric and logic

circuits and microcontrollers.

For persons who use this manual as the manual for the µPD78058F(A) and
78058FY(A),

µ

→ The

When you want to understand the functions in general:
→ Read this manual in the order of the contents.
To know the µPD78058F and 78058FY Subseries instruction function in detail:
→ Refer to the 78K/0 Series User's Manual: Instructions (U12326E)
How to interpret the register format:
→

To learn the function of a register whose register name is known:
→ Refer to APPENDIX D REGISTER INDEX.
To know the electrical specifications of the µPD78058F and 78058FY Subseries:
→ Refer to separately available Data Sheet.
To know the details regarding the functions of the µPD78058F and 78058FY
Subseries:
→ Refer to separately available Application Notes.

PD78058F and 78058FY differ from the µPD78058F(A) and 78058FY(A)
only in their quality grades. For products with (A), please change the readings
for the product name as follows.

µ

PD78058F → µPD78058F(A)

µ

PD78058FY → µPD78058FY(A)

For the circled bit number, the bit name is defined as a reserved word in
RA78K/

0, and in CC78K/0, already defined in the header file named sfrbit.h.

Caution Examples used in this manual are prepared for “Standard” product

quality grade products for general electronic equipment. If the

examples of use in this manual are utilized in applications where a

“Special” product quality grade is required, please study concern-

ing the quality grade of each part and each circuit that will actually

be used.

8

Chapter Organization This manual divides the descriptions for the µPD78058F and 78058FY Subseries into

different chapters as shown below. Read only the chapters related to the device you use.

Chapter
Chapter 1 Outline (µPD78058F Subseries) √ —
Chapter 2 Outline (µPD78058FY Subseries) — √
Chapter 3 Pin Function (µPD78058F Subseries) √ —
Chapter 4 Pin Function (µPD78058FY Subseries) — √
Chapter 5 CPU Architecture √√
Chapter 6 Port Functions √√
Chapter 7 Clock Generator √√
Chapter 8 16-Bit Timer/Event Counter √√
Chapter 9 8-Bit Timer/Event Counter √√
Chapter 10 Watch Timer √√
Chapter 11 Watchdog Timer √√
Chapter 12 Clock Output Control Circuit √√
Chapter 13 Buzzer Output Control Circuit √√
Chapter 14 A/D Converter √√
Chapter 15 D/A Converter √√
Chapter 16 Serial Interface Channel 0 √ —

(µPD78058F Subseries)

Chapter 17 Serial Interface Channel 0 — √

(µPD78058FY Subseries)
Chapter 18 Serial Interface Channel 1 √√
Chapter 19 Serial Interface Channel 2 √√
Chapter 20 Real-Time Output Port √√
Chapter 21 Interrupt and Test Functions √√
Chapter 22 External Device Expansion Function √√
Chapter 23 Standby Function √√
Chapter 24 Reset Function √√
Chapter 25 ROM Correction √√
Chapter 26µPD78P058F, µPD78P058FY √√
Chapter 27 Instruction Set √√

µ

PD78058F SubseriesµPD78058FY Subseries

9

Differences between µPD78058F and µPD78058FY Subseries:

The µPD78058F and µPD78058FY Subseries are different in the following functions
of the serial interface channel 0.

Modes of Serial Interface Channel 0µPD78058FµPD78058FY

Subseries Subseries

3-wire serial I/O mode √√
2-wire serial I/O mode √√
SBI (serial bus interface) mode √ —

I2C bus mode — √
√ : Supported
— : Not supported

Conventions Data significance : Higher digits on the left and lower digits on the right

Active low representations : ××× (overscore over pin or signal names)

Note : Footnotes for item marked with Note in the text
Caution : Information requiring particular attention
Remarks : Supplementary information

Numeral representations : Binary ... ×××× or ×××× B

Decimal ... ××××
Hexadecimal ... ××××H

10

Related Documents The related documents indicated in this publication may include preliminary

versions. However, preliminary versions are not marked as such.

Related Documents for µPD78058F Subseries

Document Name

µ

PD78056F, 78058F Data Sheet U11795J U11795E

µ

PD78P058F Data Sheet U11796J U11796E

µ

PD78058F(A) Data Sheet U12325J U12325E

µ

PD78058F, 78058FY Subseries User’s Manual U12068J This manual
78K/0 Series User’s Manual—Instruction U12326J U12326E
78K/0 Series Instruction Table U10903J —
78K/0 Series Instruction Set U10904J —
78K/0 Series Application Note Basic (III) U10182J U10182E

Document No.

Japanese English

Related Documents for µPD78058FY Subseries

Document Name

µ

PD78056FY, 78058FY Data Sheet U12142J U12142E

µ

PD78P058FY Data Sheet U12076J U12076E

µ

PD78058F, 78058FY Subseries User’s Manual U12068J This manual
78K/0 Series User’s Manual — Instructions U12326J U12326E

78K/0 Series Instruction Table U10903J —
78K/0 Series Instruction Set U10904J —
78K/0 Series Application Note Basic (III) U10182J U10182E

Document No.

Japanese English

Caution The above documents are subject to change without prior notice. Be sure to use the latest

document for designing.

11

Development Tool Documents (User’s Manuals)

Document Name

RA78K0 Assembler Package Operation U11802J U11802E

Assembly language U11801J U11801E

Structured assembler language U11789J U11789E
RA78K Series Structured Assembler Preprocessor U12323J EEU-1402
CC78K0 C Compiler Operation U11517J U11517E

Language U11518J U11518E
CC78K0 C Compiler Application Note Programming know-how U13034J EEA-1208
CC78K Series Library Source File U12322J —
PG-1500 PROM Programmer U11940J U11940E
PG-1500 Controller PC-9800 Series (MS-DOS™) Base EEU-704 EEU-1291
PG-1500 Controller IBM PC Series (PC DOS™) Base EEU-5008 U10540E
IE-78K0-NS To be prepared To be prepared
IE-78001-R-A To be prepared To be prepared
IE-780308-NS-EM1 To be prepared To be prepared
IE-78064-R-EM EEU-905 EEU-1443
IE-780308-R-EM U11362J U11362E
EP-78230 EEU-985 EEU-1515
EP-78054GK-R EEU-932 EEU-1468
SM78K0 System Simulator Windows™ Base Reference U10181J U10181E
SM78K Series System Simulator External component user U10092J U10092E

open interface specifications
ID78K0-NS Integrated Debugger U12900J To be prepared

ID78K0 Integrated Debugger EWS Base Reference U11151J —
ID78K0 Integrated Debugger PC Base Reference U11539J —
ID78K0 Integrated Debugger Windows Base Guide U11649J —

Document No.

Japanese English

Caution The above documents are subject to change without prior notice. Be sure to use the latest

document for designing.

12

Documents for Embedded Software (User’s Manual)

Document Name

78K/0 Series Real-Time OS Basics U11537J U11537E

Installation U11536J U11536E

OS for 78K/0 Series MX78K0 Basics U12257J U12257E

Document No.

Japanese English

Other Documents

Document Name

IC PACKAGE MANUAL C10943X
Semiconductor Device Mounting Technology Manual C10535J C10535E
Quality Grade on NEC Semiconductor Devices C11531J C11531E
Reliability Quality Control on NEC Semiconductor Devices C10983J C10983E

Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892J C11892E
Guide to Quality Assurance for Semiconductor Devices — MEI-1202
Microcontroller Related Product Guide — Third Party Manufacturers U11416J —

Document No.

Japanese English

Caution The above documents are subject to change without prior notice. Be sure to use the latest

document for designing.

13

[MEMO]

14

CONTENTS

CHAPTER 1 OUTLINE (µPD78058F SUBSERIES) ............................................................................. 35

1.1 Features .................................................................................................................................. 35

1.2 Applications ........................................................................................................................... 36

1.3 Ordering Information ............................................................................................................. 36

1.4 Quality Grade ......................................................................................................................... 37

1.5 Pin Configuration (Top View)................................................................................................ 38

1.6 78K/0 Series Expansion ........................................................................................................ 41

1.7 Block Diagram ........................................................................................................................ 43

1.8 Outline of Function ................................................................................................................ 44

1.9 Differences Between the µPD78058F and µPD78058F(A) .................................................. 45

1.10 Mask Options ......................................................................................................................... 46

CHAPTER 2 OUTLINE (µPD78058FY SUBSERIES) ........................................................................... 47

2.1 Features .................................................................................................................................. 47

2.2 Applications ........................................................................................................................... 48

2.3 Ordering Information ............................................................................................................. 48

2.4 Quality Grade ......................................................................................................................... 49

2.5 Pin Configuration (Top View)................................................................................................ 50

2.6 78K/0 Series Expansion ........................................................................................................ 53

2.7 Block Diagram ........................................................................................................................ 55

2.8 Outline of Function ................................................................................................................ 56

2.9 Differences Between the µPD78058FY and µPD78058FY(A) ............................................. 57

2.10 Mask Options ......................................................................................................................... 58

CHAPTER 3 PIN FUNCTION (µPD78058F SUBSERIES).................................................................... 59

3.1 Pin Function List .................................................................................................................... 59

3.1.1 Normal operating mode pins ........................................................................................................ 59

3.1.2 PROM programming mode pins (PROM versions only)............................................................... 64

3.2 Description of Pin Functions ................................................................................................ 65

3.2.1 P00 to P07 (Port 0) ...................................................................................................................... 65

3.2.2 P10 to P17 (Port 1) ...................................................................................................................... 66

3.2.3 P20 to P27 (Port 2) ...................................................................................................................... 66

3.2.4 P30 to P37 (Port 3) ...................................................................................................................... 67

3.2.5 P40 to P47 (Port 4) ...................................................................................................................... 68

3.2.6 P50 to P57 (Port 5) ...................................................................................................................... 68

3.2.7 P60 to P67 (Port 6) ...................................................................................................................... 68

3.2.8 P70 to P72 (Port 7) ...................................................................................................................... 69

3.2.9 P120 to P127 (Port 12) ................................................................................................................ 70

3.2.10 P130 and P131 (Port 13) ............................................................................................................. 70

3.2.11 AV

3.2.12 AVREF1........................................................................................................................................... 70

3.2.13 AV

REF0........................................................................................................................................... 70

DD ............................................................................................................................................. 71

15

3.2.14 AVSS.............................................................................................................................................. 71

3.2.15 RESET ......................................................................................................................................... 71

3.2.16 X1 and X2 .................................................................................................................................... 71

3.2.17 XT1 and XT2 ................................................................................................................................ 71

3.2.18 V

3.2.19 V

DD ............................................................................................................................................... 71

SS ................................................................................................................................................ 71

3.2.20 VPP (PROM versions only)............................................................................................................ 71

3.2.21 IC (Mask ROM version only) ........................................................................................................ 72

3.3 Input/output Circuits and Recommended Connection of Unused Pins ........................... 73

CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES) ................................................................. 77

4.1 Pin Function List .................................................................................................................... 77

4.1.1 Normal operating mode pins ........................................................................................................ 77

4.1.2 PROM programming mode pins (PROM versions only)............................................................... 82

4.2 Description of Pin Functions ................................................................................................ 83

4.2.1 P00 to P07 (Port 0) ...................................................................................................................... 83

4.2.2 P10 to P17 (Port 1) ...................................................................................................................... 84

4.2.3 P20 to P27 (Port 2) ...................................................................................................................... 84

4.2.4 P30 to P37 (Port 3) ...................................................................................................................... 85

4.2.5 P40 to P47 (Port 4) ...................................................................................................................... 86

4.2.6 P50 to P57 (Port 5) ...................................................................................................................... 86

4.2.7 P60 to P67 (Port 6) ...................................................................................................................... 86

4.2.8 P70 to P72 (Port 7) ...................................................................................................................... 87

4.2.9 P120 to P127 (Port 12) ................................................................................................................ 88

4.2.10 P130 and P131 (Port 13) ............................................................................................................. 88

4.2.11 AV

REF0........................................................................................................................................... 88

4.2.12 AVREF1........................................................................................................................................... 88

4.2.13 AVDD ............................................................................................................................................. 89

4.2.14 AV

SS.............................................................................................................................................. 89

4.2.15 RESET ......................................................................................................................................... 89

4.2.16 X1 and X2 .................................................................................................................................... 89

4.2.17 XT1 and XT2 ................................................................................................................................ 89

4.2.18 V

DD ............................................................................................................................................... 89

4.2.19 VSS ................................................................................................................................................ 89

4.2.20 V

PP (PROM versions only)............................................................................................................ 89

4.2.21 IC (Mask ROM version only) ........................................................................................................ 90

4.3 Input/output Circuits and Recommended Connection of Unused Pins ........................... 91

CHAPTER 5 CPU ARCHITECTURE.....................................................................................................95

5.1 Memory Spaces...................................................................................................................... 95

5.1.1 Internal program memory space .................................................................................................. 98

5.1.2 Internal data memory space......................................................................................................... 99

5.1.3 Special Function Register (SFR) area ......................................................................................... 99

5.1.4 External memory space ............................................................................................................... 99

5.1.5 Data memory addressing ............................................................................................................. 100

5.2 Processor Registers .............................................................................................................. 103

16

5.2.1 Control registers ........................................................................................................................... 103

5.2.2 General registers.......................................................................................................................... 106

5.2.3 Special Function Register (SFR).................................................................................................. 108

5.3 Instruction Address Addressing .......................................................................................... 112

5.3.1 Relative addressing...................................................................................................................... 112

5.3.2 Immediate addressing .................................................................................................................. 113

5.3.3 Table indirect addressing ............................................................................................................. 114

5.3.4 Register addressing ..................................................................................................................... 115

5.4 Operand Address Addressing .............................................................................................. 116

5.4.1 Implied addressing ....................................................................................................................... 116

5.4.2 Register addressing ..................................................................................................................... 117

5.4.3 Direct addressing ......................................................................................................................... 118

5.4.4 Short direct addressing ................................................................................................................ 119

5.4.5 Special-Function Register (SFR) addressing ............................................................................... 121

5.4.6 Register indirect addressing......................................................................................................... 122

5.4.7 Based addressing ........................................................................................................................ 123

5.4.8 Based indexed addressing ........................................................................................................... 124

5.4.9 Stack addressing.......................................................................................................................... 124

CHAPTER 6 PORT FUNCTIONS.......................................................................................................... 125

6.1 Port Functions........................................................................................................................ 125

6.2 Port Configuration ................................................................................................................. 130

6.2.1 Port 0............................................................................................................................................ 130

6.2.2 Port 1............................................................................................................................................ 132

6.2.3 Port 2 (µPD78058F Subseries) .................................................................................................... 133

µ

6.2.4 Port 2 (

6.2.5 Port 3............................................................................................................................................ 137

6.2.6 Port 4............................................................................................................................................ 138

6.2.7 Port 5............................................................................................................................................ 139

6.2.8 Port 6............................................................................................................................................ 140

6.2.9 Port 7............................................................................................................................................ 142

6.2.10 Port 12 .......................................................................................................................................... 144

6.2.11 Port 13.......................................................................................................................................... 145

PD78058FY Subseries).................................................................................................. 135

6.3 Port Function Control Registers .......................................................................................... 146

6.4 Port Function Operations...................................................................................................... 152

6.4.1 Writing to input/output port ........................................................................................................... 152

6.4.2 Reading from input/output port..................................................................................................... 152

6.4.3 Operations on input/output port.................................................................................................... 153

6.5 Selection of Mask Option ...................................................................................................... 153

CHAPTER 7 CLOCK GENERATOR ..................................................................................................... 155

7.1 Clock Generator Functions ................................................................................................... 155

7.2 Clock Generator Configuration ............................................................................................ 155

7.3 Clock Generator Control Register ........................................................................................ 157

7.4 System Clock Oscillator ........................................................................................................ 161

7.4.1 Main system clock oscillator......................................................................................................... 161

17

7.4.2 Subsystem clock oscillator ........................................................................................................... 162

7.4.3 Scaler ........................................................................................................................................... 164

7.4.4 When no subsystem clocks are used........................................................................................... 164

7.5 Clock Generator Operations ................................................................................................. 165

7.5.1 Main system clock operations ...................................................................................................... 166

7.5.2 Subsystem clock operations ........................................................................................................ 167

7.6 Changing System Clock and CPU Clock Settings .............................................................. 167

7.6.1 Time required for switchover between system clock and CPU clock ........................................... 167

7.6.2 System clock and CPU clock switching procedure ...................................................................... 169

CHAPTER 8 16-BIT TIMER/EVENT COUNTER................................................................................... 171

8.1 Overview of the µPD78058F and 78058FY Subseries On-Chip Timers............................. 171

8.2 16-Bit Timer/Event Counter Functions ................................................................................ 173

8.3 16-Bit Timer/Event Counter Configuration .......................................................................... 174

8.4 16-Bit Timer/Event Counter Control Registers ................................................................... 178

8.5 16-Bit Timer/Event Counter Operations............................................................................... 187

8.5.1 Interval timer operations............................................................................................................... 187

8.5.2 PWM output operations................................................................................................................ 189

8.5.3 PPG output operation................................................................................................................... 192

8.5.4 Pulse width measurement operations .......................................................................................... 193

8.5.5 External event counter operation ................................................................................................. 200

8.5.6 Square-wave output operation ..................................................................................................... 202

8.5.7 One-shot pulse output operation .................................................................................................. 204

8.6 16-Bit Timer/Event Counter Operating Precautions ........................................................... 208

CHAPTER 9 8-BIT TIMER/EVENT COUNTERS .................................................................................. 211

9.1 8-Bit Timer/Event Counter Function .................................................................................... 211

9.1.1 8-bit timer/event counter mode .................................................................................................... 211

9.1.2 16-bit timer/event counter mode .................................................................................................. 214

9.2 8-Bit Timer/Event Counter Configuration ............................................................................ 216

9.3 8-Bit Timer/Event Counter Control Registers ..................................................................... 220

9.4 8-Bit Timer/Event Counter Operation................................................................................... 225

9.4.1 8-bit timer/event counter mode .................................................................................................... 225

9.4.2 16-bit timer/event counter mode .................................................................................................. 230

9.5 Cautions on 8-Bit Timer/Event Counters ............................................................................. 236

CHAPTER 10 WATCH TIMER .............................................................................................................. 239

10.1 Watch Timer Functions ....................................................................................................... 239

10.2 Watch Timer Configuration................................................................................................. 240

10.3 Watch Timer Control Registers .......................................................................................... 240

10.4 Watch Timer Operations ..................................................................................................... 244

10.4.1 Watch timer operation ............................................................................................................. 244

10.4.2 Interval timer operation............................................................................................................ 244

18

CHAPTER 11 WATCHDOG TIMER ...................................................................................................... 245

11.1 Watchdog Timer Functions ................................................................................................ 245

11.2 Watchdog Timer Configuration .......................................................................................... 247

11.3 Watchdog Timer Control Registers ................................................................................... 248

11.4 Watchdog Timer Operations............................................................................................... 251

11.4.1 Watchdog timer operation ....................................................................................................... 251

11.4.2 Interval timer operation ............................................................................................................ 252

CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT......................................................................... 253

12.1 Clock Output Control Circuit Functions............................................................................ 253

12.2 Clock Output Control Circuit Configuration ..................................................................... 254

12.3 Clock Output Function Control Registers......................................................................... 254

CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT ....................................................................... 257

13.1 Buzzer Output Control Circuit Functions.......................................................................... 257

13.2 Buzzer Output Control Circuit Configuration ................................................................... 257

13.3 Buzzer Output Function Control Registers....................................................................... 258

CHAPTER 14 A/D CONVERTER .......................................................................................................... 261

14.1 A/D Converter Functions .................................................................................................... 261

14.2 A/D Converter Configuration .............................................................................................. 262

14.3 A/D Converter Control Registers ....................................................................................... 265

14.4 A/D Converter Operations................................................................................................... 269

14.4.1 Basic operations of A/D converter ........................................................................................... 269

14.4.2 Input voltage and conversion results ....................................................................................... 271

14.4.3 A/D converter operating mode ................................................................................................ 272

14.5 A/D Converter Cautions ...................................................................................................... 274

CHAPTER 15 D/A CONVERTER .......................................................................................................... 279

15.1 D/A Converter Functions .................................................................................................... 279

15.2 D/A Converter Configuration .............................................................................................. 280

15.3 D/A Converter Control Registers ....................................................................................... 282

15.4 Operations of D/A Converter .............................................................................................. 283

15.5 Cautions Related to D/A Converter.................................................................................... 284

CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES)................................... 285

16.1 Serial Interface Channel 0 Functions................................................................................. 286

16.2 Serial Interface Channel 0 Configuration .......................................................................... 288

16.3 Serial Interface Channel 0 Control Registers.................................................................... 292

16.4 Serial Interface Channel 0 Operations............................................................................... 299

16.4.1 Operation stop mode ............................................................................................................... 299

16.4.2 3-wire serial I/O mode operation ............................................................................................. 300

19

16.4.3 SBI mode operation.................................................................................................................305

16.4.4 2-wire serial I/O mode operation.............................................................................................331

16.4.5 SCK0/P27 pin output manipulation.........................................................................................336

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES).................................337

17.1 Serial Interface Channel 0 Functions.................................................................................338

17.2 Serial Interface Channel 0 Configuration..........................................................................340

17.3 Serial Interface Channel 0 Control Registers....................................................................345

17.4 Serial Interface Channel 0 Operations...............................................................................353

17.4.1 Operation stop mode...............................................................................................................353

17.4.2 3-wire serial I/O mode operation.............................................................................................354

17.4.3 2-wire serial I/O mode operation.............................................................................................358

2

17.4.4 I

17.4.5 Cautions on use of I

17.4.6 Restrictions in I2C bus mode...................................................................................................383

17.4.7 SCK0/SCL/P27 pin output manipulation.................................................................................385

C bus mode operation...........................................................................................................363

2

C bus mode............................................................................................380

CHAPTER 18 SERIAL INTERFACE CHANNEL 1...............................................................................387

18.1 Serial Interface Channel 1 Functions.................................................................................387

18.2 Serial Interface Channel 1 Configuration..........................................................................388

18.3 Serial Interface Channel 1 Control Registers....................................................................391

18.4 Serial Interface Channel 1 Operations...............................................................................399

18.4.1 Operation stop mode...............................................................................................................399

18.4.2 3-wire serial I/O mode operation.............................................................................................400

18.4.3 3-wire serial I/O mode operation with automatic transmit/receive function.............................403

CHAPTER 19 SERIAL INTERFACE CHANNEL 2...............................................................................433

19.1 Serial Interface Channel 2 Functions.................................................................................433

19.2 Serial Interface Channel 2 Configuration..........................................................................434

19.3 Serial Interface Channel 2 Control Registers....................................................................438

19.4 Serial Interface Channel 2 Operation.................................................................................446

19.4.1 Operation stop mode...............................................................................................................446

19.4.2 Asynchronous serial interface (UART) mode..........................................................................448

19.4.3 3-wire serial I/O mode.............................................................................................................461

19.4.4 Restrictions on using UART mode..........................................................................................468

CHAPTER 20 REAL-TIME OUTPUT PORT.........................................................................................471

20.1 Real-Time Output Port Functions......................................................................................471

20.2 Real-Time Output Port Configuration................................................................................472

20.3 Real-Time Output Port Control Registers.........................................................................474

CHAPTER 21 INTERRUPT AND TEST FUNCTIONS..........................................................................477

21.1 Interrupt Function Types....................................................................................................477

20

21.2 Interrupt Sources and Configuration................................................................................. 478

21.3 Interrupt Function Control Registers................................................................................. 482

21.4 Interrupt Servicing Operations........................................................................................... 491

21.4.1 Non-maskable interrupt acknowledge operation ..................................................................... 491

21.4.2 Maskable Interrupt request reception ...................................................................................... 494

21.4.3 Software interrupt request acknowledge operation ................................................................. 497

21.4.4 Multiple interrupt servicing....................................................................................................... 497

21.4.5 Interrupt request reserve ......................................................................................................... 501

21.5 Test Functions ..................................................................................................................... 502

21.5.1 Registers controlling the test function ..................................................................................... 502

21.5.2 Test input signal acknowledge operation................................................................................. 504

CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION ............................................................ 505

22.1 External Device Expansion Functions............................................................................... 505

22.2 External Device Expansion Function Control Register ................................................... 508

22.3 External Device Expansion Function Timing.................................................................... 510

CHAPTER 23 STANDBY FUNCTION................................................................................................... 515

23.1 Standby Function and Configuration ................................................................................ 515

23.1.1 Standby function...................................................................................................................... 515

23.1.2 Standby function control register ............................................................................................. 516

23.2 Standby Function Operations ............................................................................................ 517

23.2.1 HALT mode.............................................................................................................................. 517

23.2.2 STOP mode............................................................................................................................. 520

CHAPTER 24 RESET FUNCTION ........................................................................................................ 523

24.1 Reset Function..................................................................................................................... 523

CHAPTER 25 ROM CORRECTION ...................................................................................................... 527

25.1 ROM Correction Functions ................................................................................................. 527

25.2 ROM Correction Configuration........................................................................................... 527

25.3 ROM Correction Control Registers .................................................................................... 529

25.4 ROM Correction Application............................................................................................... 530

25.5 ROM Correction Example ................................................................................................... 533

25.6 Program Execution Flow..................................................................................................... 534

25.7 Cautions on ROM Correction ............................................................................................. 536

CHAPTER 26 µPD78P058F, 78P058FY ............................................................................................... 537

26.1 Memory Size Switching Register ....................................................................................... 538

26.2 Internal Expansion RAM Size Switching Register............................................................ 539

26.3 PROM Programming............................................................................................................ 540

26.3.1 Operating modes ..................................................................................................................... 540

26.3.2 PROM write procedure ............................................................................................................ 542

21

26.3.3 PROM read procedure............................................................................................................546

26.4 Screening of One-Time PROM Versions...........................................................................547

CHAPTER 27 INSTRUCTION SET.......................................................................................................549

27.1 Legends Used in Operation List.........................................................................................550

27.1.1 Operand identifiers and description methods..........................................................................550

27.1.2 Description of “operation” column...........................................................................................551

27.1.3 Description of “flag” column.....................................................................................................551

27.2 Operation List......................................................................................................................552

27.3 Instructions Listed by Addressing Type...........................................................................560

APPENDIX A DIFFERENCES AMONG µPD78054, 78058F, AND 780058 SUBSERIES ................... 565

APPENDIX B DEVELOPMENT TOOLS...............................................................................................567

B.1Language Processing Software...........................................................................................570

B.2PROM Programming Tool.....................................................................................................571

B.2.1 Hardware......................................................................................................................................571

B.2.2 Software.......................................................................................................................................571

B.3Debugging Tool......................................................................................................................572

B.3.1 Hardware......................................................................................................................................572

B.3.2 Software.......................................................................................................................................574

B.4OS for IBM PC........................................................................................................................576

B.5Upgrading Former In-circuit Emulators for 78K/0 Series to IE-78001-R-A.......................576

APPENDIX C EMBEDDED SOFTWARE..............................................................................................581

C.1Real-time OS...........................................................................................................................582

APPENDIX D REGISTER INDEX..........................................................................................................585

D.1Register Index........................................................................................................................585

APPENDIX E REVISION HISTORY......................................................................................................591

22

LIST OF FIGURES (1/8)

Figure No. Title Page

3-1 List of Pin Input/Output Circuit .......................................................................................................... 75

4-1 List of Pin Input/Output Circuit .......................................................................................................... 93

µ

5-1 Memory Map (

5-2 Memory Map (µPD78058F, 78058FY) .............................................................................................. 96

5-3 Memory Map (

5-4 Data Memory Addressing (µPD78056F, 78056FY)........................................................................... 100

5-5 Data Memory Addressing (µPD78058F, 78058FY)........................................................................... 101

5-6 Data Memory Addressing (

5-7 Program Counter Format .................................................................................................................. 103

5-8 Program Status Word Format ........................................................................................................... 103

5-9 Stack Pointer Format ........................................................................................................................ 105

5-10 Data to Be Saved to Stack Memory.................................................................................................. 105

5-11 Data to Be Reset from Stack Memory .............................................................................................. 105

5-12 General Register Configuration ........................................................................................................ 107

PD78056F, 78056FY) .............................................................................................. 95

µ

PD78P058F, µPD78P058FY) .................................................................................. 97

µ

PD78P058F, 78P058FY)...................................................................... 102

6-1 Port Types......................................................................................................................................... 125

6-2 P00 and P07 Block Diagram............................................................................................................. 131

6-3 P01 to P06 Block Diagram................................................................................................................ 131

6-4 P10 to P17 Block Diagram................................................................................................................ 132

6-5 P20, P21, P23 to P26 Block Diagram ............................................................................................... 133

6-6 P22 and P27 Block Diagram............................................................................................................. 134

6-7 P20, P21, P23 to P26 Block Diagram ............................................................................................... 135

6-8 P22 and P27 Block Diagram............................................................................................................. 136

6-9 P30 to P37 Block Diagram................................................................................................................ 137

6-10 P40 to P47 Block Diagram................................................................................................................ 138

6-11 Block Diagram of Falling Edge Detection Circuit .............................................................................. 138

6-12 P50 to P57 Block Diagram................................................................................................................ 139

6-13 P60 to P63 Block Diagram................................................................................................................ 141

6-14 P64 to P67 Block Diagram................................................................................................................ 141

6-15 P70 Block Diagram ........................................................................................................................... 142

6-16 P71 and P72 Block Diagram............................................................................................................. 143

6-17 P120 to P127 Block Diagram............................................................................................................ 144

6-18 P130 and P131 Block Diagram......................................................................................................... 145

6-19 Port Mode Register Format .............................................................................................................. 148

6-20 Pull-Up Resistor Option Register Format ......................................................................................... 149

6-21 Memory Expansion Mode Register Format ...................................................................................... 150

6-22 Key Return Mode Register Format ................................................................................................... 151

7-1 Block Diagram of Clock Generator ................................................................................................... 156

7-2 Subsystem Clock Feedback Resistor ............................................................................................... 157

7-3 Processor Clock Control Register Format ........................................................................................ 158

23

LIST OF FIGURES (2/8)

Figure No. Title Page

7-4 Oscillation Mode Selection Register Format..................................................................................... 159

7-5 Main System Clock Waveform due to Writing to OSMS ................................................................... 160

7-6 External Circuit of Main System Clock Oscillator.............................................................................. 161

7-7 External Circuit of Subsystem Clock Oscillator................................................................................. 162

7-8 Examples of Resonator with Incorrect Connection ........................................................................... 162

7-9 Main System Clock Stop Function .................................................................................................... 166

7-10 System Clock and CPU Clock Switching.......................................................................................... 169

8-1 16-Bit Timer/Event Counter Block Diagram ...................................................................................... 175

8-2 16-Bit Timer/Event Counter Output Control Circuit Block Diagram .................................................. 176

8-3 Timer Clock Selection Register 0 Format ......................................................................................... 179

8-4 16-Bit Timer Mode Control Register Format ..................................................................................... 181

8-5 Capture/Compare Control Register 0 Format ................................................................................... 182

8-6 16-Bit Timer Output Control Register Format ................................................................................... 183

8-7 Port Mode Register 3 Format ........................................................................................................... 184

8-8 External Interrupt Mode Register 0 Format ...................................................................................... 185

8-9 Sampling Clock Select Register Format ........................................................................................... 186

8-10 Control Register Settings for Interval Timer Operation ..................................................................... 187

8-11 Interval Timer Configuration Diagram ............................................................................................... 188

8-12 Interval T imer Operation Timings...................................................................................................... 188

8-13 Control Register Settings for PWM Output Operation ...................................................................... 190

8-14 Example of D/A Converter Configuration with PWM Output............................................................. 191

8-15 TV Tuner Application Circuit Example .............................................................................................. 191

8-16 Control Register Settings for PPG Output Operation ....................................................................... 192

8-17 Control Register Settings for Pulse Width Measurement with Free-Running Counter and

One Capture Register ....................................................................................................................... 193

8-18 Configuration Diagram for Pulse Width Measurement by Free-Running Counter............................ 194

8-19 Timing of Pulse Width Measurement Operation by Free-Running Counter and One Capture

Register (with Both Edges Specified) ............................................................................................... 194

8-20 Control Register Settings for Two Pulse Width Measurements with Free-Running Counter ............ 195

8-21 Timing of Pulse Width Measurement Operation with Free-Running Counter

(with Both Edges Specified).............................................................................................................. 196

8-22 Control Register Settings for Pulse Width Measurement with Free-Running Counter and

Two Capture Registers ..................................................................................................................... 197

8-23 Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture

Registers (with Rising Edge Specified)............................................................................................. 198

8-24 Control Register Settings for Pulse Width Measurement by Means of Restart ................................ 199

8-25 Timing of Pulse Width Measurement Operation by Means of Restart

(with Rising Edge Specified) ............................................................................................................. 199

8-26 Control Register Settings in External Event Counter Mode.............................................................. 200

8-27 External Event Counter Configuration Diagram................................................................................ 201

8-28 External Event Counter Operation Timings (with Rising Edge Specified) ........................................ 201

8-29 Control Register Settings in Square-Wave Output Mode ................................................................. 202

8-30 Square-Wave Output Operation Timing............................................................................................ 203

24

LIST OF FIGURES (3/8)

Figure No. Title Page

8-31 Control Register Settings for One-Shot Pulse Output Operation Using Software Trigger ................ 204

8-32 Timing of One-Shot Pulse Output Operation Using Software Trigger............................................... 205

8-33 Control Register Settings for One-Shot Pulse Output Operation Using External Trigger ................. 206

8-34 Timing of One-Shot Pulse Output Operation Using External Trigger (with Rising Edge Specified).. 207

8-35 16-Bit Timer Register Start Timing.................................................................................................... 208

8-36 Timings After Change of Compare Register during Timer Count Operation..................................... 208

8-37 Capture Register Data Retention Timing .......................................................................................... 209

8-38 Operation Timing of OVF0 Flag ........................................................................................................ 210

9-1 8-Bit Timer/Event Counter Block Diagram ........................................................................................ 217

9-2 Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 1 ............................................. 218

9-3 Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 2 ............................................. 218

9-4 Timer Clock Select Register 1 Format .............................................................................................. 221

9-5 8-Bit Timer Mode Control Register Format ....................................................................................... 222

9-6 8-Bit Timer Output Control Register Format ..................................................................................... 223

9-7 Port Mode Register 3 Format ........................................................................................................... 224

9-8 Interval Timer Operation Timings...................................................................................................... 225

9-9 External Event Counter Operation Timings (with Rising Edge Specified) ........................................ 228

9-10 Square-Wave Output Operation Timing............................................................................................ 230

9-11 Interval T imer Operation Timing........................................................................................................ 231

9-12 External Event Counter Operation Timings (with Rising Edge Specified) ........................................ 233

9-13 Square-Wave Output Operation Timing............................................................................................ 235

9-14 8-Bit Timer Registers Start Timing .................................................................................................... 236

9-15 Event Counter Operation Timing ...................................................................................................... 236

9-16 Timing After Compare Register Change During Timer Count Operation.......................................... 237

10-1 Watch Timer Block Diagram ............................................................................................................. 241

10-2 Timer Clock Select Register 2 Format .............................................................................................. 242

10-3 Watch Timer Mode Control Register Format .................................................................................... 243

11-1 Watchdog Timer Block Diagram ....................................................................................................... 247

11-2 Timer Clock Select Register 2 Format .............................................................................................. 249

11-3 Watchdog Timer Mode Register Format........................................................................................... 250

12-1 Remote Controlled Output Application Example............................................................................... 253

12-2 Clock Output Control Circuit Block Diagram..................................................................................... 254

12-3 Timer Clock Select Register 0 Format .............................................................................................. 255

12-4 Port Mode Register 3 Format ........................................................................................................... 256

13-1 Buzzer Output Control Circuit Block Diagram................................................................................... 257

13-2 Timer Clock Select Register 2 Format .............................................................................................. 259

13-3 Port Mode Register 3 Format ........................................................................................................... 260

25

LIST OF FIGURES (4/8)

Figure No. Title Page

14-1 A/D Converter Block Diagram........................................................................................................... 263

14-2 A/D Converter Mode Register Format .............................................................................................. 266

14-3 A/D Converter Input Select Register Format .................................................................................... 267

14-4 External Interrupt Mode Register 1 Format ...................................................................................... 268

14-5 A/D Converter Basic Operation ........................................................................................................ 270

14-6 Relationship Between Analog Input Voltage and A/D Conversion Result......................................... 271

14-7 A/D Conversion by Hardware Start................................................................................................... 272

14-8 A/D Conversion by Software Start .................................................................................................... 273

14-9 Example of Method of Reducing Current Consumption in Standby Mode ....................................... 274

14-10 Connection of Analog Input Pin ........................................................................................................ 275

14-11 A/D Conversion End Interrupt Request Generation Timing .............................................................. 276

14-12 Connection of AV

15-1 D/A Converter Block Diagram........................................................................................................... 280

15-2 D/A Converter Mode Register Format .............................................................................................. 282

15-3 Use Example of Buffer Amplifier ....................................................................................................... 284

DD Pin..................................................................................................................... 277

16-1 Serial Bus Interface (SBI) System Configuration Example............................................................... 287

16-2 Serial Interface Channel 0 Block Diagram........................................................................................ 289

16-3 Timer Clock Select Register 3 Format .............................................................................................. 293

16-4 Serial Operating Mode Register 0 Format ........................................................................................ 294

16-5 Serial Bus Interface Control Register Format ................................................................................... 296

16-6 Interrupt Timing Specify Register Format ......................................................................................... 298

16-7 3-Wire Serial I/O Mode Timings........................................................................................................ 303

16-8 RELT and CMDT Operations ............................................................................................................ 303

16-9 Circuit of Switching in Transfer Bit Order.......................................................................................... 304

16-10 Example of Serial Bus Configuration with SBI .................................................................................. 305

16-1 1 SBI Transfer Timings ........................................................................................................................ 307

16-12 Bus Release Signal .......................................................................................................................... 308

16-13 Command Signal .............................................................................................................................. 308

16-14 Addresses ......................................................................................................................................... 309

16-15 Slave Selection with Address............................................................................................................ 309

16-16 Commands........................................................................................................................................ 310

16-17 Data .................................................................................................................................................. 310

16-18 Acknowledge Signal ......................................................................................................................... 311

16-19 BUSY and READY Signals ............................................................................................................... 312

16-20 RELT, CMDT, RELD, and CMDD Operations (Master)..................................................................... 317

16-21 RELT and CMDD Operations (Slave) ............................................................................................... 317

16-22 ACKT Operation................................................................................................................................ 318

16-23 ACKE Operations ............................................................................................................................. 319

16-24 ACKD Operations ............................................................................................................................. 320

16-25 BSYE Operation ............................................................................................................................... 320

16-26 Pin Configuration .............................................................................................................................. 323

26

LIST OF FIGURES (5/8)

Figure No. Title Page

16-27 Address Transmission from Master Device to Slave Device (WUP = 1) .......................................... 325

16-28 Command Transmission from Master Device to Slave Device ......................................................... 326

16-29 Data Transmission from Master Device to Slave Device.................................................................. 327

16-30 Data Transmission from Slave Device to Master Device.................................................................. 328

16-31 Serial Bus Configuration Example Using 2-Wire Serial I/O Mode .................................................... 331

16-32 2-Wire Serial I/O Mode Timings ........................................................................................................ 334

16-33 RELT and CMDT Operations ............................................................................................................ 335

16-34 SCK0/P27 Pin Configuration ............................................................................................................ 336

2

17-1 Serial Bus Configuration Example Using I

17-2 Serial Interface Channel 0 Block Diagram........................................................................................ 341

17-3 Timer Clock Select Register 3 Format .............................................................................................. 346

17-4 Serial Operating Mode Register 0 Format ........................................................................................ 348

17-5 Serial Bus Interface Control Register Format ................................................................................... 349

17-6 Interrupt Timing Specify Register Format ......................................................................................... 351

17-7 3-Wire Serial I/O Mode Timings........................................................................................................ 356

17-8 RELT and CMDT Operations ............................................................................................................ 356

17-9 Circuit of Switching in Transfer Bit Order.......................................................................................... 357

17-10 Serial Bus Configuration Example Using 2-Wire Serial I/O Mode .................................................... 358

17-11 2-Wire Serial I/O Mode Timings........................................................................................................ 361

17-12 RELT and CMDT Operations ............................................................................................................ 362

17-13 Example of Serial Bus Configuration Using I

17-14 I2C Bus Serial Data Transfer Timing ................................................................................................. 364

17-15 Start Condition .................................................................................................................................. 365

17-16 Address ............................................................................................................................................. 365

17-17 Transfer Direction Specification ........................................................................................................ 365

17-18 Acknowledge Signal ......................................................................................................................... 366

17-19 Stop Condition .................................................................................................................................. 366

17-20 Wait Signal ........................................................................................................................................ 367

17-21 Pin Configuration .............................................................................................................................. 372

17-22 Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait)............. 374

17-23 Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait)............. 377

17-24 Start Condition Output ...................................................................................................................... 380

17-25 Slave Wait Release (Transmission) .................................................................................................. 381

17-26 Slave Wait Release (Reception) ....................................................................................................... 382

17-27 SCK0/SCL/P27 Pin Configuration .................................................................................................... 385

17-28 SCK0/SCL/P27 Pin Configuration .................................................................................................... 385

17-29 Logic Circuit of SCL Signal ............................................................................................................... 386

C Bus............................................................................. 339

2

C Bus......................................................................... 363

18-1 Serial Interface Channel 1 Block Diagram........................................................................................ 389

18-2 Timer Clock Select Register 3 Format .............................................................................................. 392

18-3 Serial Operating Mode Register 1 Format ........................................................................................ 393

18-4 Automatic Data Transmit/Receive Control Register Format ............................................................. 394

27

LIST OF FIGURES (6/8)

Figure No. Title Page

18-5 Automatic Data Transmit/Receive Interval Specify Register Format ................................................ 395

18-6 3-Wire Serial I/O Mode Timings........................................................................................................ 401

18-7 Circuit of Switching in Transfer Bit Order.......................................................................................... 402

18-8 Basic Transmission/Reception Mode Operation Timings ................................................................. 411

18-9 Basic Transmission/Reception Mode Flowchart ............................................................................... 412

18-10 Internal Buffer RAM Operation in 6-Byte Transmission/Reception (in Basic Transmit/Receive

Mode)................................................................................................................................................ 413

18-11 Basic Transmission Mode Operation Timings................................................................................... 415

18-12 Basic Transmission Mode Flowchart ................................................................................................ 416

18-13 Internal Buffer RAM Operation in 6-Byte Transmission (in Basic Transmit Mode) ........................... 417

18-14 Repeat Transmission Mode Operation Timing.................................................................................. 419

18-15 Repeat Transmission Mode Flowchart ............................................................................................. 420

18-16 Internal Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmit Mode)......................... 421

18-17 Automatic Transmission/Reception Suspension and Restart ........................................................... 423

18-18 System Configuration When the Busy Control Option Is Used ......................................................... 424

18-19 Operation Timings When Using Busy Control Option (BUSY0 = 0).................................................. 425

18-20 Busy Signal and Wait Cancel (When BUSY0 = 0) ............................................................................ 426

18-21 Operation Timings When Using Busy & Strobe Control Option (BUSY0 = 0)................................... 427

18-22 Operation Timing of the Bit Slippage Detection Function Through the Busy Signal

(When BUSY0 = 1) ........................................................................................................................... 428

18-23 Automatic Transmit/Receive Interval Time ....................................................................................... 429

18-24 Operation Timing with Automatic Data Transmit/Receive Function Performed by Internal Clock .... 430

19-1 Serial Interface Channel 2 Block Diagram........................................................................................ 435

19-2 Baud Rate Generator Block Diagram ............................................................................................... 436

19-3 Serial Operating Mode Register 2 Format ........................................................................................ 438

19-4 Asynchronous Serial Interface Mode Register Format ..................................................................... 439

19-5 Asynchronous Serial Interface Status Register Format.................................................................... 441

19-6 Baud Rate Generator Control Register Format ................................................................................ 442

19-7 Asynchronous Serial Interface Transmit/Receive Data Format ........................................................ 455

19-8 Asynchronous Serial Interface Transmission Completion Interrupt Request Generation Timing ..... 457

19-9 Asynchronous Serial Interface Reception Completion Interrupt Request Generation Timing .......... 458

19-10 Receive Error Timing ........................................................................................................................ 459

19-11 Receive Buffer Register (RXB) Status and Receive Completion Interrupt Request (INTSR)

Generation When Receiving Is Terminated ...................................................................................... 460

19-12 3-Wire Serial I/O Mode Timing.......................................................................................................... 466

19-13 Circuit of Switching in Transfer Bit Order .......................................................................................... 467

19-14 Receive Completion Interrupt Request Generation Timing (When ISRM = 1).................................. 468

19-15 Period that Reading Receive Buffer Register Is Prohibited .............................................................. 469

20-1 Real-time Output Port Block Diagram............................................................................................... 472

20-2 Real-time Output Buffer Register Configuration ............................................................................... 473

20-3 Port Mode Register 12 Format ......................................................................................................... 474

28

LIST OF FIGURES (7/8)

Figure No. Title Page

20-4 Real-time Output Port Mode Register Format .................................................................................. 474

20-5 Real-time Output Port Control Register Format................................................................................ 475

21-1 Basic Configuration of Interrupt Function ......................................................................................... 480

21-2 Interrupt Request Flag Register Format ........................................................................................... 483

21-3 Interrupt Mask Flag Register Format ................................................................................................ 484

21-4 Priority Specify Flag Register Format ............................................................................................... 485

21-5 External Interrupt Mode Register 0 Format ...................................................................................... 486

21-6 External Interrupt Mode Register 1 Format ...................................................................................... 487

21-7 Sampling Clock Select Register Format ........................................................................................... 488

21-8 Noise Elimination Circuit Input/Output Timing (During Rising Edge Detection)................................ 489

21-9 Program Status Word Format........................................................................................................... 490

21-10 Flowchart from the Time a Non-maskable Interrupt Request Is Generated Until It Is Received ...... 492

21-11 Non-Maskable Interrupt Request Acknowledge Timing .................................................................... 492

21-12 Non-Maskable Interrupt Request Acknowledge Operation ............................................................... 493

21-13 Interrupt Request Acknowledge Processing Algorithm ..................................................................... 495

21-14 Interrupt Request Acknowledge Timing (Minimum Time) ................................................................. 496

21-15 Interrupt Request Acknowledge Timing (Maximum Time) ................................................................ 496

21-16 Multiple Interrupt Example ................................................................................................................ 499

21-17 Interrupt Request Hold ...................................................................................................................... 501

21-18 Basic Configuration of Test Function ................................................................................................ 502

21-19 Format of Interrupt Request Flag Register 1L .................................................................................. 503

21-20 Format of Interrupt Mask Flag Register 1L ....................................................................................... 503

21-21 Key Return Mode Register Format ................................................................................................... 504

22-1 Memory Map When Using External Device Expansion Function ..................................................... 506

22-2 Memory Expansion Mode Register Format ...................................................................................... 508

22-3 Memory Size Switching Register Format.......................................................................................... 509

22-4 Instruction Fetch from External Memory........................................................................................... 511

22-5 External Memory Read Timing ......................................................................................................... 512

22-6 External Memory Write Timing.......................................................................................................... 513

22-7 External Memory Read Modify Write Timing..................................................................................... 514

23-1 Oscillation Stabilization Time Select Register Format ...................................................................... 516

23-2 HALT Mode Clear upon Interrupt Request Generation ..................................................................... 518

23-3 HALT Mode Release by RESET Input .............................................................................................. 519

23-4 STOP Mode Release by Interrupt Request Generation.................................................................... 521

23-5 Release by STOP Mode RESET Input ............................................................................................. 522

24-1 Block Diagram of Reset Function ..................................................................................................... 523

24-2 Timing of Reset Input by RESET Input ............................................................................................. 524

24-3 Timing of Reset due to Watchdog Timer Overflow............................................................................ 524

24-4 Timing of Reset Input in STOP Mode by RESET Input..................................................................... 524

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LIST OF FIGURES (8/8)

Figure No. Title Page

25-1 Block Diagram of ROM Correction ................................................................................................... 527

25-2 Correction Address Registers 0 and 1 Format.................................................................................. 528

25-3 Correction Control Register Format.................................................................................................. 529

25-4 Storing Example to EEPROM (When One Place Is Corrected)........................................................ 530

25-5 Connecting Example with EEPROM (Using 2-Wire Serial I/O Mode) .............................................. 530

25-6 Initialization Routine.......................................................................................................................... 531

25-7 ROM Correction Operation ............................................................................................................... 532

25-8 ROM Correction Example................................................................................................................. 533

25-9 Program Transition Diagram (When One Place Is Corrected).......................................................... 534

25-10 Program Transition Diagram (When Two Places Are Corrected)...................................................... 535

26-1 Memory Size Switching Register Format.......................................................................................... 538

26-2 Internal Expansion RAM Size Switching Register Format................................................................ 539

26-3 Page Program Mode Flowchart ........................................................................................................ 542

26-4 Page Program Mode Timing ............................................................................................................. 543

26-5 Byte Program Mode Flowchart ......................................................................................................... 544

26-6 Byte Program Mode Timing .............................................................................................................. 545

26-7 PROM Read Timing.......................................................................................................................... 546

B-1 Development Tool Configuration....................................................................................................... 568

B-2 EV-9200GC-80 Drawings (For Reference Only)............................................................................... 577

B-3 EV-9200GC-80 Footprints (For Reference Only).............................................................................. 578

B-4 TGK-080SDW Drawings (For Reference) (unit: mm) ....................................................................... 579

30