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and operator control. Since implementation by customers of each product may vary, the
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This service and reference manual contains the technical information necessary to set up,
maintain, troubleshoot, and repair the NEC Image® P90E and Image P100E computer
systems. It also provides hardware and interface information for users who need an
overview of the computer system design. The manual is written for NEC-trained customer
engineers, system analysts, service center personnel, and dealers.
The manual is organized as follows:
Section 1, Technical Information, provides an overview of the computer features,
hardware design, interface ports and internal devices.
Section 2, Setup and Operation, takes the user from unpacking to setup and operation.
Included is a description of the system configuration, system password, and the computer’s
jumper settings, including the factory default settings.
Section 3, Options, provides the user with installation and troubleshooting information for
each specific option.
Section 4, Troubleshooting and Repair, includes a list of NEC service information and
telephone numbers that provide access to the NEC Bulletin Board System (BBS),
FastFacts, and Technical Information Bulletins. Included are maintenance, troubleshooting,
and disassembly and reassembly information along with an illustrated parts breakdown.
Appendix A, Specifications, provides specifications for the system unit, power supply,
diskette drives, hard disk drives, and CD-ROM reader.
Appendix B, Connector Pin Assignments, provides a list of the system board internal
connector pin assignments and a list of external pin assignments for the keyboard/mouse,
serial, parallel, video, PCI IDE, and SCSI-2 ports.
Abbreviations
xvii
AampereACalternating currentATadvanced technology
(IBM PC)
BBSBulletin Board SystemBCDbinary-coded decimalBCUBIOS Customized UtilityBIOSbasic input/output systembitbinary digitBUUBIOS Upgrade Utilitybpibits per inchbpsbits per secondCcapacitanceCcentigradeCachehigh-speed buffer storageCAMconstantly addressable memoryCAScolumn address strobeCD-ROM compact disk-ROMCGcharacter generatorCGAColor Graphics AdapterCGBColor Graphics BoardCHchannelclkclockcmcentimeterCMOScomplementary metal oxide
DMACDMA controllerDOSdisk operating systemDRAMdynamic RAMDTEdata terminal equipmentECCerror checking and correctionEGAEnhanced Graphics AdapterEISAExtended Industry Standard
IMAImage Memory Accessin.inchIPBillustrated parts breakdownIRRInterrupt Request registerISAIndustry Standard Architecture
xviii Abbreviations
ISRIn Service registerI/Oinput/outputIPCintegrated peripheral controlleripsinches per secondIRQinterrupt requestKkilo (1024)kkilo (1000)KBkilobytekgkilogramkHzkilohertzlbpoundLEDlight-emitting diodeLSBleast-significant bitLSIlarge-scale integrationMmegamAmilliampsmaxmaximumMBmegabyteMDAMonochrome Display AdapterMFMmodified frequency
modulation
MHzmegahertzmmmillimetermsmillisecondMSBmost-significant bitNASCNational Authorized Service
Center
PIOprogrammable input/outputpixelpicture elementPLCCplastic lead chip carrierPLLphase lock loopp-ppeak-to-peakPPIprogrammable peripheral
interface
PPBPCI-to-PCI BridgePROMprogrammable ROMQFPquad flat packRAMrandom-access memoryRAMDAC RAM digital-to-analogRASrow address strobeRGBred green blueRGBIred green blue intensityROMread-only memoryrpmrevolutions per minuteRreadR/Wread/writeSslaveSCSISmall Computer System
Interface
SGsignal groundSIMMsingle inline memory moduleSVGASuper Video Graphics ArraySWswitch
TACTechnical Assistance CenterNCnot connectedNMINon-maskable InterruptnsnanosecondNSRC National Service Response
This section provides an overview of the Image® P90E and Image P100E enhanced
minitower computers. These computers use Intel® Pentium™ microprocessors in a
PCI/EISA bus architecture designed for workstation environments. Basic hardware
includes a system unit, keyboard, and mouse. External interface connectors are located in
the rear of the system unit and are identified in Section 2, Setup and Operation. Section 2
also provides system configuration switch settings and jumper settings for all hardware.
Appendix A provides system specifications.
SYSTEM UNIT
The system unit chassis provides an enclosure for the system board, power supply, six
storage device slots, and five-expansion-slots.
The storage device slots accommodate a standard 3 1/2-inch diskette drive, plus two
internal 3 1/2-inch slots configured as follows:
n one 3 1/2-inch x 1.0-inch device bay
n one 3 1/2-inch x 1.6 inch device bay
In addition, the system unit supports three 5 1/4-inch accessible storage devices (1.6-inch
height).
System configurations are available with a 3 1/2-inch diskette drive only or a 3 1/2-inch
diskette drive, internal 3 1/2-inch hard disk drive, and an Intelligent Device Electronics
(IDE) CD-ROM reader (leaving two 5 1/4-inch accessible storage device bays and one
internal 3 1/2-inch slot available for optional devices). A system unit is shown in Figure
Section 1-1.
All hard disk configurations come with an IDE CD-ROM reader and support both the
SCSI-2 Peripheral Component Interconnect (PCI) or enhanced IDE device interface for fast
data storage and retrieval.
1-2 Technical Information
System Unit
Mouse
Power Cord
Keyboard
Figure Section 1-1 Image P90E and Image P100E System Unit Components
System Board
The system board contains the computer’s processing and peripheral control circuitry, as
well as the sockets for connecting memory and peripheral devices. Features of the system
board are listed as follows.
n Pentium™ 90-MHz (Image P90E) or 100-MHz (Image P100E) processor
n support for dual processor option
Technical Information 1-3
nsupport for memory expansion board containing a minimum of 16 megabytes
(MB) of dynamic random access memory (DRAM) in single processor
configurations
memory expandable to a maximum of 256 MB of DRAM using either
1-MB x 36 bit, 2-MB x 36 bit, 4-MB x 36 bit, or 8-MB x 36 bit, 70 ns
SIMMs mounted in the 8-slot memory expansion board (see Section 3 for
memory expansion procedures)
supports base and extended memory
n 16-kilobyte (KB) primary cache (8 KB data and 8 KB instructions) integrated on
the Pentium processor
n 256-KB synchronous secondary cache in single processor configurations
n high bandwidth PCI local bus
supports burst modes that send large chunks of data across the bus, allowing
fast displays of high-resolution images
eliminates data bottlenecks
maintains maximum performance at high clock speeds
provides clear upgrade path to future technologies
n Integrated 32-bit bit-block-transfers (BitBLT) graphics accelerator that uses the
PCI local bus
supports 640 x 480 and 800 x 600 resolutions with 16.8 million colors (24-bit
True Color), and 1024 x 768 resolution with 256 colors
2-MB of 45 ns video dynamic RAM (VRAM) (eight 256K x 8 chips soldered
on the system board)
supports a linear frame buffer with full PCI burst write support
1-4 Technical Information
none Small Computer System Interface (SCSI) connector supporting up to five
internal and 7 external devices (hard disk drives, tape back-up drives, and CD
ROM readers) using the PCI local bus Fast SCSI-2 host adapter
supports a synchronous data transfer rate of 10 MB per second, which is
twice as fast as the regular SCSI
supports asynchronous data transfer rates up to 5 MB per second
supports the common command set (CSS) for compatibility
supports a command queuing feature that enhances multi-tasking
performance and helps reduce bottlenecks in I/O operations
n two fast PCI-bus enhanced IDE interface connectors (both connectors will
operate two devices)
one primary IDE connector, used by the hard disk drive
one secondary IDE connector, used by the IDE CD-ROM reader
supports up to 11-MB per second 32-bit wide data transfers on the high-
performance PCI local bus
n high-performance EISA bus with full bus mastering capability
supports 33-MB per second burst mode data transfer rate, increasing the
speed of I/O operations (which is very important for configurations with
multiple storage devices)
supports up to four EISA devices installed in system board’s EISA expansion
slots
allows maximum system throughput by distributing the workload to
intelligent subsystems, creating balanced system performance where no one
subsystem impedes the activity of another
supports downward compatibility with any installed Industry Standard
Architecture (ISA) hardware
n diskette drive interface controlling one or two diskette drives
n expansion board slots providing three EISA/ISA expansion slots, one PCI-bus
expansion slot, and one shared EISA or PCI-bus expansion slot
n system I/O controller integrating, on one chip, the controller functions for the
system’s two serial ports, bidirectional parallel port, and diskette drives
Technical Information 1-5
nexternal connectors providing an interface for the following external devices:
video graphics array (VGA)-compatible monitor
personal system/2 (PS/2®)-style mouse
PS/2-style keyboard
PS/2, Enhanced Parallel Port (EPP) and enhanced capabilities port (ECP) are
supported for the parallel printer
two buffered serial ports
Table Section 1-1 lists the major chips on the system board. See Section 2, Setup and
Operation, for a description of the system board's switches and jumpers. See Appendix B,
Connector Pin Assignments, for a list of the system board connectors.
Table Section 1-1 System Board Chips
Chip Description
Intel Pentium 90- or 100-MHz processor
28F020 256k x 8 flash ROM
Intel Neptune II PCI/EISA Chip Set
S82434NX PCI cache and memory controller (PCMC)
S82433NX Local bus accelerators (LBXs)
S82375SB PCI - EISA bridge component (PCEB)
S82374SB EISA system component (ESC)
Tseng
W32P
PCI0640 CMD PCI IDE interface controller
STG1703 SYNDAC
FDC37C665 Standard MicroSystems System I/O controller
N87C42 Keyboard controller
AIC-7850 Adaptec SCSI-2 controller
PCI video graphics controller
1-6 Technical Information
Chipset
The Image P90E and Image P100E computers use the Intel Neptune II chipset, which
consists of the PCI cache and memory controller (PCMC), two local bus accelerators
(LBXs), the PCI EISA bridge component (PCEB), and the EISA system component (ESC).
Together these five chips control the cache memory, the EISA bus, the BIOS Flash ROM,
the keyboard controller, and the I/O controller. The chipset also contains several I/O ports
that control many aspects of the computer’s hardware operation.
PCI Cache and Memory Controller (PCMC)
The PCMC provides cache control, system memory control, and PCI bus control. An
integrated cache controller supports 256 KB of synchronous SRAM. The PCMC supports
up to 256 MBs of cacheable system memory. The PCI controller enhances system memory
performance by allowing for concurrency between the CPU bus and the PCI bus. For
further details, refer to the Intel Neptune II PCMC and LBX Component Specification.
Local Bus Accelerators (LBXs)
Two LBXs are used to interface the Host bus to the PCI bus and the system memory data
bus. The LBXs provide the following five buffers to increase performance.
n CPU to memory posted write buffer
n PCI to memory posted write buffer
n Memory to PCI read buffer
n CPU to PCI posted write buffer
n CPU to PCI read prefetch buffer
For further details, refer to the Intel Neptune II PCMC and LBX Component Specification.
Technical Information 1-7
PCI-EISA Bridge Component (PCEB)
The PCEB is one of the two chips that connect the PCI bus to to the EISA bus. The PCEB
translates bus protocols from EISA to PCI and vice versa. Extensive buffering of both the
PCI and EISA interface allows for concurrent operations. Address decoding is provided for
both PCI and EISA. For further details, refer to the Intel PCI–EISA Bridge (PCEB)Component Specification.
EISA System Component (ESC)
The ESC interfaces the PCI bus to the EISA bus. The ESC supplements the PCEB by
implementing such system functions as the Timer/ Counter, DMA and interrupt controllers,
and EISA subsystem control functions (such as the Bus Controller and Bus Arbiter).
Interrupt level assignments are provided later in this section (see “Interrupt Controller”).
For further details, refer to the Intel EISA System Component (ESC) Specification.
Bus Architecture
The interconnection of the major system components via the address and data buses is
shown in Figure Section 1-2. The number range next to each bus arrow indicates the bits
on the bus the arrow represents. Major buses include the host bus, system memory bus, the
PCI bus, the EISA bus, and the XD bus. The function of these buses is described in the
following subsections.
1-8 Technical Information
Figure Section 1-2 Component Block Diagram
Host Bus
The host bus consists of a 32-bit address bus (A<31..0>), a 64-bit data bus (D<63..0>), and
control circuitry. The host bus interfaces the processor to the PCI cache and memory
controller (PCMC), the local bus accelerators (LBXs), and the secondary (L2) cache. Host
bus cycles are initiated by ADS* signals from the processor and terminated by BRDY*
signal from the PCMC. All host bus cycles are monitored by the PCMC and directed to the
cache, system memory, or the PCI bus.
Technical Information 1-9
PCI Bus
The PCI bus consists of a multiplexed address and data bus (AD<31..0>) and control
circuitry. The PCI bus allows industry-standard PCI option boards to interface to the
system. The PCMC and LBXs link the PCI bus to the host bus, and PCI EISA bridge
component (PCEB) links the PCI bus to the EISA bus. PCI is a high bandwidth bus that is
processor independent. The on-board video, IDE, and SCSI controllers are on the PCI bus.
EISA Bus
The EISA bus consists of an address bus (SA<19..0>, LA<31..24>*, and <LA23..2>), a 32bit data bus (SD<31..0>), and control circuitry. The EISA bus is controlled by the PCEB
and EISA System component (ESC) and provides connection to industry standard
EISA/ISA option boards.
XD Bus
The XD bus (XD<7..0>) is an 8 bit data bus that provides connection to the keyboard
controller, ROM BIOS, and real-time clock (RTC). The XD bus is a buffered version of the
low order 8 bits of the EISA data bus (SD<31..0>). In the Neptune chipset, a distinction is
made between on-board and off-board peripherals. In general, on-board means that access
is expected to occur via the XD bus instead of the EISA bus. In this case, the access still
occurs on the EISA bus, but if the access is a read (I/O or memory), the ESC enables the
XD bus peripheral to drive the lower 8 bits of the EISA data bus (SD<7..0>).
System Memory Bus
The system memory bus consists of 11 bits of row/column addresses (MA<10..0>) that are
buffered to address banks 0, 1, 2, and 3. Each bank consists of two SIMMs. The PCMC
drives the system memory bus and memory control signals, which causes the data to be
driven to/from the LBXs (MD<63..0>).
Processor
The Image P90 system uses a 64-bit, 90-MHz Pentium microprocessor with a 60-MHz
external clock speed. The Image P100E uses a 64-bit, 100-MHz Pentium microprocessor
with a 66-MHz external clock speed. The technology package used for the microprocessor
is the 296-pin, staggered-pin-grid array (SPGA. The processor has 16 KB of write-back
internal cache, 8 KB for instructions and 8 KB for data. Also integrated into the processor
is a math coprocessor for complex calculations and processing tasks.
To use the Pentium processor’s power, the system features an optimized 64-bit memory
interface and complementary 256-KB secondary cache.
The Pentium processor is compatible with all 8-, 16-, and 32-bit software written for the
Intel386™, Intel486™, and Pentium processors.
1-10 Technical Information
The dual processor upgrade option is installed in a 320-pin PGA, zero-insertion-force (ZIF)
socket on the system board.
Secondary Cache
The 16-KB primary cache (8 KB data and 8 KB instruction) is integrated into the
processor. The system board also provides 256 KB of 9-ns, synchronous secondary cache
memory that is external to the processor. Cache memory improves read performance by
holding copies of code and data that are frequently requested from the system memory by
the processor. Cache memory is not considered part of the expansion memory.
The cache is connected directly to the processor address bus (direct mapped) and uses
physical addresses (32-bit line size). A bus feature known as Burst enables fast cache fills.
Memory areas (pages) can be designated as cacheable or non-cacheable by software. The
cache can also be enabled and disabled by software.
The write strategy of the secondary cache is write-back for single processor systems and
write-through for dual processor systems. If the write is a cache hit, an external bus cycle is
generated and information is written to the cache. Any area of memory can be cached in the
system. Non-cacheable portions of memory are defined by software. The cache can be
cleared by software instructions.
Flash ROM
Machine language programs known as the system's basic input/output system (BIOS) are
stored in a 256K x 8 Flash ROM chip (28F020 PLCC) mounted on the system board. The
system BIOS, EISA extensions, PCI extensions, Automatic Configuration Unit (ACU)
loader, and Video BIOS reside in the upper 64K of the ROM area. The lower 64K of ROM
includes the SCSI BIOS and ACU code.
The flash ROM allows the BIOS to be upgraded with the BIOS Update utility without
removing the ROM (see Section 4, Maintenance and Troubleshooting). The BIOS can only
be reprogrammed by powering on the system with the BIOS Update utility diskette in
drive A.
The BIOS programs execute the Power-On Self-Test (POST), initialize the processor
controllers, and interact with the display, diskette drives, hard disks, communication
devices, and peripherals. The system BIOS also contains the Setup program and provides
VGA controller support. The ROM BIOS is always copied into RAM (shadowing) for
maximum performance.
System BIOS is located between E0000h-FFFFFh and supports shadowing and shadowed
memory. System BIOS is write protected and automatically enabled.
The video BIOS is combined with the system BIOS and is located between C0000h and
C7FFFh. The system memory map is shown in Table Section 1-2.
Technical Information 1-11
Table Section 1-2 System Memory Map
Memory Space Size Function
000000-07FFFF 512 KB Conventional base memory
080000-09FBFF 127 KB Extended conventional base memory
09FC00-09FFFF 1 KB Extended BIOS Data (movable by EMM386, QEMM and 386
max)
0A0000-0BFFFF 128 KB On-board video memory
0C0000-0C7FFF 32 KB On-board video BIOS
0C8000-0DFFFF 128 KB Open to EISA and PCI bus*
**E0000-FFFFF 128 KB System BIOS
100000- On-Board 255 MB Extended system memory
* On-board Adaptec PCI SCSI-2 bus may use 10 to 32 KB of this area
** Detail map of E0000-FFFFF:
E0000 - E324Favailable, not used
***E3250 - E477FSetup
E4780 - E536FBIOS string table
E5370 - EC5B6 Plug and Play code
EC5B7 - FFFFF remainder of BIOS
** Subject to change without notice
*** May be reclaimed for DOS UMB’s (include E000 - E4FF)
Flash ROM supports the reprogramming of the system and built-in video BIOS. The Flash
part can be accessed in 128K granularity for ROM reads and 64K granularity for flashing.
NEC Port 0C12h bits 6 and 7 map each of the four 64K byte chunks of the ROM to the
FXXXX range. ACU access is controlled by the system BIOS code and is generally not
accessible in ISA space. Table Section 1-3 shows how to access the different areas of the
Flash ROM by using bits 6 and 7 (RPG0 – 1) from NEC proprietary port 0C12h (see “NEC
Proprietary Ports” later in this section).
Table Section 1-3 Flash ROM Selection Bits
RPG0 RPG1 Selection
0 0 Highest 64 KB accessible at FXXXX
0 1 Third 64 KB accessible at FXXXX
1 0 Second 64 KB accessible at FXXXX
1 1 Lowest 64 KB accessible at FXXXX
1-12 Technical Information
Flash ROM programming is supported only in the 0F0000h – 0FFFFh area. The system
and Video BIOS area of the Flash ROM (upper 64 KB) can be erased, programmed, and
verified normally with the RPG0 bit set low (to 0). To erase, program, and verify the SCSI
BIOS and ACU area (lower 64 bits) the RPG0 bit must be set high (to 1). This allows
access to the lower 64 KB of the Flash ROM via the 0F000h to 0FFFFFh area.
To upgrade the BIOS, see Section 4, Maintenance and Troubleshooting, for BIOS upgrade
information.
On-Board Peripherals
The following subsections describe the computer’s on-board peripheral control circuitry.
The peripherals interface with the computer through either the PCI or EISA buses.
SCSI Circuitry
The SCSI circuitry is controlled by the Adaptec AIC-7850 PCI bus to SCSI bus controller.
SCSI bus connectivity allows connection to SCSI-compatible peripherals, such as highcapacity floppy drives, tape drives, and CD-ROMs. The AIC-7850 can support data
transfer rates of up to 10 MBs per second. For further information, refer to the AdaptecAIC-7850 data manual.
IDE Controller
The CMD PCIO640B IDE controller supports up to four IDE hard disks. The PCIO640B
supports both primary and secondary IDE devices. Automatic sensing of EISA hard disk
controllers is provided. If the BIOS senses an EISA hard disk controller, the on-board IDE
interface is disabled. For further information, refer to the CMD PCIO640B data manual.
Video Circuitry
The Tseng W32P PCI graphics accelerator features a graphical user interface (GUI)
accelerator and advanced features for the developing imaging and multimedia markets. For
further information, refer to the Tseng W32P data manual.
EISA SRAM
A 6264LP 8Kx8 static RAM is used to configure the EISA bus. This SRAM receives its
power from the bq4287 real-time clock (RTC), which uses a lithium battery. The 6264LP
is located on the EISA bus.
Technical Information 1-13
Real-Time Clock (RTC)
The computer uses a Benchmarq bq4287 RTC module with non-volatile RAM control. The
bq4287 resides on the XD bus and provides a time-of-day clock and a 100-year calendar
with alarm features and battery operation. The battery life is approximately 6 years when
driving an SRAM that draws 2 microamperes when off and the computer is off 2/3 of the
day. For further information, refer to the Benchmarq bq4287 data sheet.
System I/O Controller
The computer uses the SMC FDC37C665 I/O system I/O controller to provide a floppy
disk controller, a digital data separator, two 16550 compatible UARTS, and an enhanced
bidirectional parallel port. The computer supports extended capabilities port (ECP),
enhanced parallel port (EPP), and ZIPPY protocols.
The I/O controller provides control for up to two diskette/tape drives. The following
devices are supported:
n 5 1/4-inch 360 KB diskette drive
n 5 1/4-inch 1.2 MB diskette drive
n 3 1/2-inch, 720 KB diskette drive
n 3 1/2-inch, 1.44 MB diskette drive
n 3 1/2-inch 2.88 MB diskette drive
The capacity of 3 1/2 inch diskette drives is sensed automatically. The existence of an
EISA floppy controller is also automatically sensed. If the BIOS detects an EISA floppy
controller, the on-board floppy controller is disabled. The on-board floppy controller can
also be disabled via Setup (for diskless workstations). However, if there is no bootable
device available, the system BIOS will attempt to boot from the built-in floppy even if the
on-board floppy controller is disabled via Setup. This provides a bootable system in the
event that the CMOS is corrupted.
I/O Mapping
The processor communicates with I/O devices by I/O mapping. There are a large number of
I/O ports implemented in the system associated with the keyboard controller, system I/O
controller, and Neptune II chipset. The hexadecimal (hex) addresses of I/O devices used by
the Image P90E and Image P100E are listed in Table Section 1-4. For a description of the
chipset configuration registers, see the following subsection.
The I/O ports implemented by the system I/O controller are not listed. Refer to the SMCFDC37C665 data sheets for a detailed description of the system I/O controller ports. In
addition, keyboard controller registers (with the exception of the keyboard status register)
are documented in the NEC PS/2 Style Keyboard Controller release notes.