NEC 2SK3386-Z, 2SK3386 Datasheet
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
SWITCHING
N-CHANNEL POWER MOS FET
INDUSTRIAL USE
2SK3386
DESCRIPTION
The 2SK3386 is N-Channel MOS Field Effect Transistor
designed for high current switching applications.
FEATURES
• Low On-state Resistance
★
★
DS(on)1
R
DS(on)2
R
• Low C
= 21 mΩ MAX. (VGS = 10 V, ID = 17 A)
= 36 mΩ MAX. (VGS = 4.0 V, ID = 17 A)
iss
iss
: C
= 2100 pF TYP.
• Built-in Gate Protection Diode
• TO-251/TO-252 package
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C)
Drain to Source Voltage V
Gate to Source Voltage V
Drain Current (DC) I
★
Drain Current (Pulse)
★
Total Power Dissipation (T
Total Power Dissipation (T
Note1
C
= 25°C) P
A
= 25°C) P
Channel Temperature T
Storage Temperature T
★
Single Avalanche Current
★
Single Avalanche Energy
Note2
Note2
DSS
GSS
D(DC)
D(pulse)
I
AS
I
E
stg
AS
ORDERING INFORMATION
PART NUMBER PACKAGE
2SK3386
2SK3386-Z
60 V
±20 V
±34 A
±120 A
T
T
ch
40 W
1.0 W
150 °C
–55 to +150 °C
28 A
78 mJ
TO-251
TO-252
(TO-251)
(TO-252)
Notes 1.
2.
PW ≤ 10
Starting Tch = 25 °C, RG = 25 Ω, VGS = 20 V → 0 V
µ
s, Duty cycle ≤ 1 %
THERMAL RESISTANCE
★
Channel to Case R
Channel to Ambient R
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. D14471EJ1V0DS00 (1st edition)
Date Published January 2000 NS CP(K)
Printed in Japan
th(ch-C)
th(ch-A)
3.13 °C/W
125 °C/W
The mark ★ shows major revised points.
©
1999,2000
★
ELECTRICAL CHARACTERISTICS (TA = 25 °C)
CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
2SK3386
Drain to Source On-state Resi stance R
Gate to Source Cut-off Voltage V
DS(on)1VGS
DS(on)2VGS
R
GS(off)VDS
= 10 V, ID = 17 A 17 21 m
= 4.0 V, ID = 17 A 25 36 m
= 10 V, ID = 1 mA 1.5 2.0 2. 5 V
Forward Transfer Admittance | yfs |VDS = 10 V, ID = 17 A 10 19 S
Drain Leakage Current I
Gate to Source Leakage Current I
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Turn-on Delay Time t
Rise Time t
Turn-off Delay Time t
Fall Time t
Total Gate Charge Q
Gate to Source Charge Q
Gate to Drain Charge Q
Body Diode Forward Voltage V
Reverse Recovery Time t
Reverse Recovery Charge Q
DSS
VDS = 60 V, VGS = 0 V 10
GSS
VGS = ±20 V, VDS = 0 V ±10
iss
VDS = 10 V 2100 pF
oss
VGS = 0 V 340 pF
rss
f = 1 MHz 170 pF
d(on)ID
d(off)
F(S-D)IF
= 17 A 32 ns
r
GS(on)
V
= 10 V 310 ns
VDD = 30 V 98 ns
f
RG = 10
G
ID = 34 A 39 nC
GS
VDD = 48 V 7.0 nC
GD
V
Ω
GS(on)
= 10 V 12 nC
100 ns
= 34 A, VGS = 0 V 0.87 V
rr
IF = 34 A, VGS = 0 V 46 ns
rr
di/dt = 100 A/µs84nC
Ω
Ω
A
µ
A
µ
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
L
V
DD
PG.
RG = 25 Ω
50 Ω
VGS = 20 → 0 V
BV
DSS
I
AS
V
I
D
V
DD
DS
Starting T
ch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
PG.
IG = 2 mA
50 Ω
R
L
V
DD
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
L
R
G
PG.
GS
V
0
τ = 1 s
Duty Cycle ≤ 1 %
R
V
DD
τ
µ
GS
V
Wave Form
I
D
Wave Form
V
GS
10 %
0
90 %
I
D
10 %
0
t
d(on)
r
t
on
t
90 %
V
GS
(on)
90 %
I
D
10 %
t
d(off)
t
f
t
off
2
Data Sheet
D14471EJ1V0DS00
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