NEC 2SK3360 Datasheet
PRELIMINARY DATA SHEET
MOS FIELD EFFECT TRANSISTOR
SWITCHING
N-CHANNEL POWER MOS FET
INDUSTRIAL USE
2SK3360
DESCRIPTION
The 2SK3360 is N-Channel MOS Field Effect Transistor
designed for high current switching application.
FEATURES
• Low on-state resistance
DS(on)1
R
★
★
★
• Low C
= 30 mΩ MAX. (VGS = 10 V, ID = 18 A)
DS(on)2
R
= 40 mΩ MAX. (VGS = 4.5 V, ID = 18 A)
iss
iss
: C
= 3200 pF TYP.
• Built-in gate protection diode
• Isolated TO-220 package
ABSOLUTE MAXIMUM RATI NGS (TA = 25°C)
Drain to Source Voltage V
Gate to Source Voltage V
Gate to Source Voltage V
★
Drain Current (DC) I
Drain Current (pulse)
★
Total Power Dissipation (T
Total Power Dissipation (T
Note1
C
= 25°C) P
A
= 25°C) P
Channel Temperature T
Storage Temperature T
Single Avalanche Current
★
Single Avalanche Energy
★
Note2
Note2
DSS
GSS(AC)
GSS(DC)
D(DC)
D(pulse)
I
AS
I
E
stg
AS
ORDERING INFORMATION
PART NUMBER PACKAGE
2SK3360 Isolated TO-220
(Isolated TO-220)
100 V
±20 V
+20, –10 V
±35 A
±140 A
T
T
ch
35 W
2.0 W
150 °C
–55 to +150 °C
35 A
122 mJ
Notes 1.
PW ≤ 10 µs, Duty Cycle ≤ 1 %
2.
Starting Tch = 25 °C, RG = 25 Ω, VGS = 20 V→0 V
THERMAL RESISTANCE
Channel to Case R
Channel to Ambient R
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. D14331EJ1V0DS00 (1st edition)
Date Published April 2000 NS CP(K)
Printed in Japan
The mark
th(ch-C)
th(ch-A)
★★★★
shows major revised points.
3.57 °C/W
62.5 °C/W
©
1999
★
ELECTRICAL CHARACTERISTICS (TA = 25 °C)
CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
2SK3360
Drain to Source On-state Resi stance R
Gate to Source Cut-off Voltage V
DS(on)1VGS
DS(on)2VGS
R
GS(off)VDS
= 10 V, ID = 18 A 20 30 m
= 4.5 V, ID = 18 A 28 40 m
= 10 V, ID = 250
A 1.5 2.0 2.5 V
µ
Forward Transfer Admittance | yfs |VDS = 10 V, ID = 18 A 13 28 S
Drain Leakage Current I
Gate to Source Leakage Current I
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Turn-on Delay Time t
Rise Time t
Turn-off Delay Time t
Fall Time t
Total Gate Charge Q
Gate to Source Charge Q
Gate to Drain Charge Q
Body Diode Forward Voltage V
Reverse Recovery Time t
Reverse Recovery Charge Q
DSS
VDS = 100 V, VGS = 0 V 10
GSS
VGS = ±20 V, VDS = 0 V
iss
VDS = 10 V 3200 pF
oss
VGS = 0 V 640 pF
rss
f = 1 MHz 360 pF
d(on)ID
d(off)
GS
GD
F(S-D)IF
rr
= 18 A 35 ns
r
GS(on)
V
= 10 V 220 ns
VDD = 50 V 220 ns
f
RG = 10
Ω
G
ID = 35 A 84 nC
190 ns
VDD = 80 V 11 nC
GS(on)
V
= 10 V 31 nC
= 35 A, VGS = 0 V 0.96 V
IF = 35 A, VGS = 0 V 150 ns
rr
di/dt = 100 A /
s 800 nC
µ
10
±
Ω
Ω
A
µ
A
µ
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
L
V
DD
PG.
RG = 25 Ω
50 Ω
VGS = 20 → 0 V
BV
DSS
I
AS
V
I
D
V
DD
DS
Starting T
ch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
PG.
IG = 2 mA
50 Ω
R
L
V
DD
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
L
R
G
PG.
GS
V
0
τ = 1 s
Duty Cycle ≤ 1 %
R
V
DD
τ
µ
GS
V
Wave Form
I
D
Wave Form
V
GS
10 %
0
90 %
I
D
10 %
0
t
d(on)
r
t
on
t
90 %
V
GS
(on)
90 %
I
D
10 %
t
d(off)
t
f
t
off
2
Preliminary Data Sheet D14331EJ1V0DS00
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