NEC 2SK3359-Z, 2SK3359-S, 2SK3359 Datasheet
PRELIMINARY DATA SHEET
MOS FIELD EFFECT TRANSISTOR
SWITCHING
N-CHANNEL POWER MOS FET
INDUSTRIAL USE
2SK3359
DESCRIPTION
The 2SK3359 is N-Channel MOS Field Effect Transistor
designed for high current switching applications.
FEATURES
• Low on-state resistance
DS(on)1
R
= 20 mΩ MAX. (VGS = 10 V, ID = 35 A)
DS(on)2
R
★
★
• Low C
= 28 mΩ MAX. (VGS = 4.5 V, ID = 30 A)
iss
iss
: C
= 4900 pF TYP.
• Built-in gate protection diode
ABSOLUTE MAXIMUM RATI NGS (TA = 25 °C)
Drain to Source Voltage (VGS = 0 V) V
Gate to Source Voltage (V
Gate to Source Voltage (V
DS
= 0 V) V
DS
= 0 V) V
Drain Current (DC) I
Drain Current (Pulse)
Total Power Dissipation (T
Total Power Dissipation (T
Note1
C
= 25°C) P
A
= 25°C) P
Channel Temperature T
Storage Temperature T
Single Avalanche Current
Single Avalanche Energy
Note2
Note2
DSS
GSS(AC)
GSS(DC)
D(DC)
D(pulse)
I
T
T
ch
stg
AS
I
AS
E
ORDERING INFORMATION
PART NUMBER PACKAGE
2SK3359 TO-220AB
2SK3359-S TO-262
2SK3359-Z TO-220SMD
100 V
±20 V
+20, −10 V
±70 A
±280 A
100 W
1.5 W
150 °C
–55 to +150 °C
50 A
250 mJ
(TO-220AB)
(TO-262)
Notes 1.
2.
PW ≤ 10
Starting Tch = 25 °C, RG = 25 Ω, VGS = 20 V → 0 V
µ
s, Duty cycle ≤ 1 %
THERMAL RESISTANCE
Channel to Case R
Channel to Ambient R
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. D14323EJ1V0DS00 (1st edition)
Date Published April 2000 NS CP(K)
Printed in Japan
th(ch-C)
th(ch-A)
The mark
1.25 °C/W
83.3 °C/W
★★★★
shows major revised points.
(TO-220SMD)
©
1999
ELECTRICAL CHARACTERISTICS (TA = 25 °C)
CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
2SK3359
Drain to Source On-state Resi stance R
★
★
Gate to Source Cut-off Voltage V
DS(on)1VGS
DS(on)2VGS
R
GS(off)VDS
= 10 V, ID = 35 A1420m
= 4.5 V, ID = 30 A1928m
= 10 V, ID = 250
A 1.5 2.0 2.5 V
µ
Forward Transfer Admittance | yfs |VDS = 10 V, ID = 35 A 23 47 S
Drain Leakage Current I
Gate to Source Leakage Current I
★
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Turn-on Delay Time t
Rise Time t
Turn-off Delay Time t
Fall Time t
Total Gate Charge Q
★
Gate to Source Charge Q
Gate to Drain Charge Q
★
Body Diode Forward Voltage V
Reverse Recovery Time t
Reverse Recovery Charge Q
DSS
VDS = 100 V, VGS = 0 V10
GSS
VGS = ±20 V, VDS = 0 V
iss
VDS = 10 V 4900 pF
oss
VGS = 0 V 990 pF
rss
f = 1 MHz 580 pF
d(on)ID
r
d(off)
f
GS
GD
F(S-D)IF
rr
= 35 A58ns
GS(on)
V
= 10 V 400 ns
VDD = 50 V 340 ns
RG = 10
Ω
G
ID = 70 A 130 nC
340 ns
VDD = 80 V14nC
GS(on)
V
= 10 V50nC
= 70 A, VGS = 0 V1.0V
IF = 70 A, VGS = 0 V 170 ns
rr
di/dt = 100 A /
s 920 nC
µ
Ω
Ω
A
µ
10
±
A
µ
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
L
V
DD
PG.
RG = 25 Ω
50 Ω
VGS = 20 → 0 V
BV
DSS
I
AS
V
I
D
V
DD
DS
Starting T
ch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
PG.
IG = 2 mA
50 Ω
R
L
V
DD
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
L
R
G
PG.
GS
V
0
τ = 1 s
Duty Cycle ≤ 1 %
R
V
DD
τ
µ
GS
V
Wave Form
I
D
Wave Form
V
GS
10 %
0
90 %
I
D
10 %
0
t
d(on)
r
t
on
t
90 %
V
GS
(on)
90 %
I
D
10 %
t
d(off)
t
f
t
off
2
Preliminary Data Sheet D14323EJ1V0DS00
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