NEC 2SK3354-Z, 2SK3354-S, 2SK3354 Datasheet
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
SWITCHING
N-CHANNEL POWER MOS FET
INDUSTRIAL USE
2SK3354
DESCRIPTION
The 2SK3354 is N-channel MOS Field Effect Transistor
designed for high current switching applications.
FEATURES
•Super low on-state resistance:
DS(on)1
= 8.0 mΩ MAX. (VGS = 10 V, ID = 42 A)
R
★
DS(on)2
★
★
•Low C
= 12 mΩ MAX. (VGS = 4 V, ID = 42 A)
R
iss
iss
: C
= 6300 pF TYP.
•Built-in gate protection diode
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage V
Gate to Source Voltage V
Drain Current (DC) I
Drain Current (pulse)
Total Power Dissipation (T
Total Power Dissipation (T
Channel Temperature T
Storage Temperature T
★
Single Avalanche Current
★
Single Avalanche Energy
Note1
C
= 25°C) P
A
= 25°C) P
Note2
Note2
DSS
GSS(AC)
D(DC)
D(pulse)
I
stg
AS
I
AS
E
T
T
ch
ORDERING INFORMATION
PART NUMBER PACKAGE
60 V
20 V
±
83 A
±
332 A
±
100 W
1.5 W
150 °C
–55 to +150 °C
55 A
302 mJ
2SK3354
2SK3354-S
2SK3354-Z
TO-220AB
TO-262
TO-220SMD
Notes 1.
★
PW ≤ 10
2.
Starting Tch = 25 °C, RG = 25 Ω, VGS = 20 V → 0 V
µ
s, Duty cycle ≤ 1 %
THERMAL RESISTANCE
Channel to Case Rth(ch-C) 1.25
Channel to Ambient Rth(ch-A) 83.3
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. D14131EJ1V0DS00 (1st edition)
Date Published June 1999 NS CP(K)
Printed in Japan
The mark ★ shows major revised points.
C/W
°
C/W
°
©
1999
★
ELECTRICAL CHARACTERISTICS (TA = 25 °C)
CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
2SK3354
Drain to Source On-state Resi stance R
Gate to Source Cut-off Voltage V
DS(on)1VGS
DS(on)2VGS
R
GS(off)VDS
= 10 V, ID = 42 A6.38.0m
= 4 V, ID = 42 A8.012m
Ω
Ω
= 10 V, ID = 1 mA 1.5 2.0 2.5 V
Forward Transfer Admittance | yfs |VDS = 10 V, ID = 42 A3559S
Drain Leakage Current I
Gate to Source Leakage Current I
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Turn-on Delay Time t
Rise Time t
Turn-off Delay Time t
Fall Time t
Total Gate Charge Q
Gate to Source Charge Q
Gate to Drain Charge Q
Body Diode Forward Voltage V
Reverse Recovery Time t
Reverse Recovery Charge Q
DSS
VDS = 60 V, VGS = 0 V10
GSS
VGS = ±20 V, VDS = 0 V
iss
VDS = 10 V, VGS = 0 V, f = 1 MHz 6300 pF
oss
rss
d(on)ID
d(off)
GS
GD
F(S-D)IF
rr
= 42 A, V
r
RG = 10
f
G
ID = 83 A , VDD = 48 V, VGS = 10 V 106 nC
= 83 A, VGS = 0 V1.0V
IF = 83 A, VGS = 0 V, 55 ns
rr
di/dt = 100 A/µs 100 nC
GS(on)
= 10 V, VDD = 30 V, 100 ns
Ω
1000 pF
1500 ns
±
490 pF
300 ns
440 ns
20 nC
30 nC
10
A
µ
A
µ
TEST CIRCUIT 1 AVALANCHE CAPABILITY
VGS = 20 → 0 V
PG.
V
R
G
DD
= 25 Ω
50 Ω
I
D
D.U.T.
I
AS
BV
DSS
V
DS
Starting T
L
DD
V
ch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
I
G
PG.
= 2 mA
50 Ω
R
L
V
DD
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
R
PG.
V
GS
0
τ
τ = 1 µs
Duty Cycle ≤ 1 %
G
R
G
= 10 Ω
V
V
GS
Wave Form
I
D
Wave Form
GS
10 %
0
I
D
0
%
90
10 %10
t
d(on)
trt
t
on
V
GS(on)
I
D
d(off)tf
90
%
%
90
%
t
off
R
L
V
DD
2
Data Sheet D14131EJ1V0DS00
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