NEC 2SK3225-Z, 2SK3225 Datasheet
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
SWITCHING
N-CHANNEL POWER MOS FET
INDUSTRIAL USE
2SK3225
DESCRIPTION
This product is N-Channel MOS Field Effect Transistor
designed for high current switching applications.
FEATURES
• Low On-State Resistance
DS(on)1
R
= 18 mΩ MAX. (VGS = 10 V, ID = 17 A)
DS(on)2
R
= 27 mΩ MAX. (VGS = 4.0 V, ID = 17 A)
iss
• Low C
iss
: C
= 2100 pF TYP.
• Built-in Gate Protection Diode
• TO-251/TO-252 package
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C)
Drain to Source Voltage V
Gate to Source Voltage V
Gate to Source Voltage V
Drain Current (DC) I
Drain Current (Pulse)
Total Power Dissipation (T
Total Power Dissipation (T
Note
C
= 25°C) P
A
= 25°C) P
Channel Temperature T
Storage Temperature T
DSS
GSS(AC)
GSS(DC)
D(DC)
D(pulse)
I
T
T
ch
stg
ORDERING INFORMATION
PART NUMBER PACKAGE
2SK3225
2SK3225-Z
60 V
±20 V
+20, −10 V
±34 A
±136 A
40 W
2.0 W
150 °C
–55 to +150 °C
TO-251
TO-252
Note
PW ≤ 10
µ
s, Duty cycle ≤ 1 %
THERMAL RESISTANCE
Channel to Case R
Channel to Ambient R
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. D13798EJ1V0DS00 (1st edition)
Date Published May 1999 NS CP(K)
Printed in Japan
th(ch-C)
th(ch-A)
3.13 °C/W
125 °C/W
©
1998,1999
ELECTRICAL CHARACTERISTICS (TA = 25 °C)
CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
2SK3225
Drain to Source On-state Resi stance R
Gate to Source Cut-off Voltage V
DS(on)1VGS
DS(on)2VGS
R
GS(off)VDS
= 10 V, ID = 17 A 13 18 m
= 4.0 V, ID = 17 A 18 27 m
= 10 V, ID = 1 mA 1.0 1.5 2.0 V
Forward Transfer Admittance | yfs |VDS = 10 V, ID = 17 A 13 27 S
Drain Leakage Current I
Gate to Source Leakage Current I
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Turn-on Delay Time t
Rise Time t
Turn-off Delay Time t
Fall Time t
Total Gate Charge Q
Gate to Source Charge Q
Gate to Drain Charge Q
Body Diode Forward Voltage V
Reverse Recovery Time t
Reverse Recovery Charge Q
DSS
VDS = 60 V, VGS = 0 V 10
GSS
VGS = ±20 V, VDS = 0 V ±10
iss
VDS = 10 V 2100 pF
oss
VGS = 0 V 550 pF
rss
f = 1 MHz 220 pF
d(on)ID
d(off)
F(S-D)IF
= 17 A 32 ns
r
GS(on)
V
= 10 V 300 ns
VDD = 30 V 110 ns
f
RG = 10
G
ID = 34 A 45 nC
GS
VDD = 48 V 7 nC
GD
V
Ω
GS(on)
= 10 V 13 nC
140 ns
= 34 A, VGS = 0 V 0.94 V
rr
If = 34 A, VGS = 0 V 60 ns
rr
di/dt = 100 A/µs95nC
Ω
Ω
A
µ
A
µ
TEST CIRCUIT 1 AVALANCHE CAPABILITY
VGS = 20 → 0 V
PG.
V
R
G
DD
= 25 Ω
50 Ω
I
D
D.U.T.
I
AS
BV
DSS
V
DS
Starting T
L
DD
V
ch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
I
G
PG.
= 2 mA
50 Ω
R
L
V
DD
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
R
PG.
V
GS
0
τ
τ = 1 µs
Duty Cycle ≤ 1 %
G
R
G
= 10 Ω
V
V
GS
Wave Form
I
D
Wave Form
GS
10 %
0
I
D
0
%
90
10 %10
t
d(on)
trt
t
on
V
GS(on)
I
D
d(off)tf
90
%
%
90
%
t
off
R
L
V
DD
2
Data Sheet
D13798EJ1V0DS00
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