NEC 2SK3204 Datasheet
N-CHANNEL POWER MOS FET
DESCRIPTION
The 2SK3204 is N-Channel MOS Field Effect Transistor
designed for high current switching applications.
••••
FEATURES
• Low on-state resistance :
DS(on)1
R
R
• Low C
• Built-in gate protection diode.
= 34 mΩ (MAX.) (VGS = 10 V, ID = 8 A)
DS(on)2
= 50 mΩ (MAX.) (VGS = 4 V, ID = 8 A)
iss : Ciss
= 940 pF (TYP.)
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
SWITCHING
INDUSTRIAL USE
••••
ORDERING INFORMATION
2SK3204
PART NUMBER PACKAGE
2SK3204 MP-10
ABSOLUTE MAX IMUM RATINGS (TA = 25 °C)
Drain to Source Voltage V
Gate to Source Voltage V
Gate to Source Voltage V
Drain Current (DC) I
Drain Current (pulse)
Total Power Dissipation (T
Note1
A
= 25 °C) P
Channel Temperature T
Storage Temperature T
••••
Single Avalanche Current
Single Avalanche Energy
••••
Notes 1.
PW ≤ 10
2.
Starting Tch = 25 °C, RG = 25 Ω, VGS = 20 V→0 V
Note2
Note2
µ
s, Duty Cycle ≤ 1 %
THERMAL RESISTANCE
Channel to Ambient Rth
DSS
GSS(AC)
GSS(DC)
D(DC)
D(pulse)
I
T
ch
stg
AS
I
AS
E
(ch-A)
60 V
±20 V
+20, −10 V
±15 A
±45 A
1.8 W
150 °C
−55 to +150 °C
15 A
22.5 mJ
69.4 °C/W
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. D13796EJ1V0DS00 (1st edition)
Date Published April 1999 NS CP (K)
Printed in Japan
The mark
••••
shows major revised points.
©
1998, 1999
••••
ELECTRICAL CHARACTERISTICS (TA = 25 °C)
PARAMATERS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Drain to Source On-state Resistance
Gate to Source Cut-off Voltage V
R
DS(on)2VGS
R
GS(off)VDS
= 10 V, ID = 8 A 25 34 m
= 4 V, ID = 8 A 35 50 m
= 10 V, ID = 1 mA 1.0 1.5 2.0 V
DS(on)1VGS
Forward Transfer Admittance | yfs |VDS = 10 V, ID = 8 A 8.0 14 S
Drain Leakage Current I
Gate to Source Leakage Current I
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Turn-on Delay Time t
Rise Time t
Turn-off Delay Time t
Fall Time t
Total Gate Charge Q
Gate to Source Charge Q
Gate to Drain Charge Q
Body Diode Forward Voltage V
Reverse Recovery Time t
Reverse Recovery Charge Q
DSS
VDS = 60 V, VGS = 0 V 10
GSS
VGS = ±20 V, VDS = 0 V ±10
iss
VDS = 10 V, VGS = 0 V, f = 1 MHz
oss
rss
d(on)
ID = 8 A, V
RG = 10
r
d(off)
f
G
ID = 15 A, VDD = 48 V, V
GS
GD
F(S-D)IF
rr
= 15 A, VGS = 0 V 0.92 V
IF = 15 A, VGS = 0 V,
di/dt = 100 A/
rr
Ω
GS(on)
= 10 V, V
s
µ
DD
GS(on)
= 30 V,
= 10 V
940 pF
290 pF
120 pF
17 ns
150 ns
58 ns
52 ns
25 nC
2.9 nC
7.5 nC
45 ns
81 nC
2SK3204
Ω
Ω
A
µ
A
µ
•••••
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
V
DS
Starting T
L
DD
V
ch
R
G
= 25 Ω
PG.
VGS = 20 → 0 V
I
V
DD
••••
TEST CIRCUIT 3 GATE CHARGE
D
50 Ω
I
BV
DSS
AS
•
••
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
R
R
G
G
= 10 Ω
PG.
V
GS
0
τ
τ = 1 µs
Duty Cycle ≤ 1 %
V
R
L
V
Wave Form
V
DD
I
Wave Form
GS
GS
D
10 %
0
I
D
90
%
10 %10
0
t
d(on)
trt
t
on
D.U.T.
G
= 2 mA
PG.
I
50 Ω
R
L
V
DD
GS(on)
V
I
D
d(off)tf
%
90
90
%
%
t
off
2
Data sheet D13796EJ1V0DS00
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