Datasheet 2SK3108 Datasheet (NEC)

DATA SHEET

MOS FIELD EFFECT TRANSISTOR

SWITCHING

N-CHANNEL POWER MOS FET

INDUSTRIAL USE

DESCRIPTION

The 2SK3108 is N channel MOS FET device that features a low on-state resistance and excellent switching characteristics, and designed for high voltage applications such as DC/DC converter.

FEATURES

•Gate voltage rating ±30 V

•Low on-state resistance

DS(on)

= 0.4 Ω MAX. (VGS = 10 V, ID = 4.0 A)

R

•Low input capacitance

iss

C

= 400 pF TYP. (VDS = 10 V, VGS = 0 V)

•Avalanche capability rated

•Built-in gate protection diode

•Isolated TO-220 package

2SK3108

ORDERING INFORMATION

PART NUMBER PACKAGE

2SK3108 Isolated TO-220

ABSOLUTE MAXIMUM RATING (TA = 25°C)

Drain to Source Voltage (VGS = 0 V) V Gate to Source Voltage (VDS = 0 V) V

C

Drain Current(DC) (T Drain Current(pulse) Total Power Dissipation (T Total Power Dissipation (T

= 25°C) I

Note1

A

= 25°C) P

C

= 25°C) P

Channel Temperature T Storage Temperature T Single Avalanche Current Single Avalanche Energy

Note1.

2.

PW ≤ 10

Starting T

µ

ch

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

Note2

s, Duty Cycle ≤ 1%

= 25°C, VDD = 100 V, RG = 25 Ω , VGS = 20 V→0 V

DSS

GSS

D(DC)

D(pulse)

I

T1

T2

ch

stg

AS

I

AS

E

200 V

±30 V

±8.0 A

±24 A

2.0 W 25 W

150 °C

−55 to +150 °C

8.0 A 51 mJ

Document No. D13331EJ1V0DS00 (1st edition) Date Published January 2000 NS CP (K) Printed in Japan

The mark ★ shows major revised point s.

©

1998,2000

ELECTRICAL CHARACTERISTICS (TA = 25°C)

Characteristics Symbol Test Conditions MIN. TYP. MAX. Unit

2SK3108

Drain Leakage Current I Gate Leakage Current I Gate to Source Cut-off Voltage Forward Transfer Admittance | yfs |V Drain to Source On-state Resistance R Input Capacitance C Output Capacitance C Reverse Transfer Capacitance C Turn-on Delay Time t Rise Time t Turn-off Delay Time t Fall Time t

★

Total Gate Charge Q Gate to Source Charge Q Gate to Drain Charge Q Diode Forward Voltage V Reverse Recovery Time t Reverse Recovery Charge Q

DSS

GSS

GS(off)

V

d(on)

r

d(off)

f

F(S-D)

rr

DS(on)

iss

oss

rss

G

GS

GD

rr

VDS = 200 V, VGS = 0 V 100 VGS = ±30 V, VDS = 0 V ±10 VDS = 10 V, ID = 1 mA 2.5 4.5 V

DS

VGS = 10 V, ID = 4.0 A 0.32 0.4 VDS = 10 V 400 pF VGS = 0 V 110 pF f = 1 MHz 55 pF VDD = 100 V, ID = 4.0 A 12 ns

GS(on)

V RG = 10 Ω

VDD = 160 V 18 nC VGS = 10 V 3.5 nC ID = 8.0 A 10 nC IF = 8.0 A, VGS = 0 V 1.0 V IF = 8.0 A, VGS = 0 V 250 ns di/dt = 50 A/µs

µ µ

= 10 V, ID = 4.0 A 1.5 S

= 10 V 25 ns

40 ns 20 ns

1.0

µ

A A

Ω

C

TEST CIRCUIT 1 AVALANCHE CAPABILITY

PG.

VGS = 20 → 0 V

V

G

R

DD

= 25 Ω

50 Ω

I

D

D.U.T.

I

AS

BV

DSS

V

DS

Starting T

L

DD

V

ch

TEST CIRCUIT 3 GATE CHARGE

D.U.T.

G

= 2 mA

PG.

I

50 Ω

R

L

V

DD

TEST CIRCUIT 2 SWITCHING TIME

D.U.T.

R

PG.

V

GS

0

τ

τ = 1 µs

Duty Cycle ≤ 1 %

G

V

R

L

V

Wave Form

V

DD

I

Wave Form

GS

D

10 %

0

I

D

10 %10

0

t

d(on)

V

90

%

I

D

trt

t

on

GS(on)

d(off)tf

t

off

%

90

%

2

Data Sheet D13331EJ1V0DS00

GATE TO SOURCE CUT-OFF VOLTAGE vs. CHANNEL TEMPERATURE

T

ch

- Channel Temperature - ˚C

V

GS(off)

- Gate to Source Cut-off Voltage - V

V

DS

= 10 V

I

D

= 1 mA

− 50

50

100

0 150

5.0

4.5

4.0

3.5

3.0

2.5

2.0

− 25 25 75

125

★

TYPICAL CHARACTERISTICS (TA = 25°C)

2SK3108

DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE

30

25

20

15

10

- Drain Current - A

D

I

5

0

68

2

4

V

DS -

Drain to Source Voltage - V

10

1214

V

GS

= 30 V

V

1618

GS

2022

= 10 V

Pulsed

24

26

28

30

FORWARD TRANSFER CHARACTERISTICS

100

10

1

0.1 T

ch

5

67

=125˚C 75˚C 25˚C

-25˚C

910

8

Tch = 75˚C

Tch = 125˚C

- Drain Current - A

D

I

0.01

0.001 0

2

34

1

GS -

V

FORWARD TRANSFER ADMITTANCE vs. DRAIN CURRENT

10

VDS =10 V Pulsed

Tch = -25˚C

1

Tch = 25˚C

Gate to Source Voltage - V

0.1

1112

Pulsed

VDS = 10 V

131415

16

DRAIN TO SOURCE ON-STATE RESISTANCE vs. GATE TO SOURCE VOLTAGE

1.0

0.8

0.6

0.4

0.2

- Drain to Source On-state Resistance - Ω

0

DS(on)

R

24

6

GS

- Gate to Source Voltage - V

V

I

D

810

=

8.0 A

4.0 A

1.6 A

12 14

Pulsed

16 18 20

0.01

|yfs| - Forward Transfer Admittance - s

0.01

1.0

0.8

0.6

0.4

0.2

- Drain to Source On-state Resistance - Ω

0

0.1

DS(on)

R

0.1 I

DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT

D

- Drain Current - A

I

1

D- Drain Current - A

V

GS

= 10 V

1

10

V

GS

100

Pulsed

= 30 V

100

Data Sheet D13331EJ1V0DS00

3

DRAIN TO SOURCE ON-STATE RESISTANCE vs. CHANNEL TEMPERATURE

1.2

1.0 ID = 8.0 A

0.8

0.6

0.4

0.2

- Drain to Source On-state Resistance - Ω

DS(on)

R

0

− 50

0 150− 25 25 75 125

T

ch

- Channel Temperature - ˚C

CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE

50

100

10000

ID = 4.0 A

GS

= 10 V

V Pulsed

VGS = 0 V f = 1 MHz

SOURCE TO DRAIN DIODE FORWARD VOLTAGE

100

10

V

GS

= 10 V

1

- Diode Forward Current - A

SD

I

0.1

0.0

0.2 V

0.6 0.8 1.4

0.4

SD

- Source to Drain Voltage - V

SWITCHING CHARACTERISTICS

1000

V

GS

= 0 V

1.0 1.2

2SK3108

Pulsed

1.6

t

r

1000

- Capacitance - pF

rss

100

, C

oss

, C

iss

C

10

0.1

1 10 100

DS

- Drain to Source Voltage - V

V

REVERSE RECOVERY TIME vs. DRAIN CURRENT

1000

100

10

trr - Reverse Recovery Time - ns

1

0.1 I

D - Drain Current - A

C

iss

C

oss

C

rss

1000

µ

di/dt = 50A / V

GS = 0 V

s

1 10 100

100

- Switching Time - ns

f

10

, t

d(off)

, t

r

, t

d(on)

t

1

0.1

1 10 100

D

- Drain Current - A

I

DYNAMIC INPUT/OUTPUT CHARACTERISTICS

200

150

V

DD

= 160 V 100 V 40 V

100

V

DD

50

- Drain to Source Voltage - V

DS

V

0

= 160 V 100 V 40 V

5101520

Q

G

- Gate Charge - nC

t

f

t

d(off)

t

d(on)

V

DD

= 100 V

GS

= 10 V

V R

G

= 10 Ω

ID = 8.0 A

16 14

12 10 8 6

- Gate to Source Voltage - V

4

GS

V

2 0

4

Data Sheet D13331EJ1V0DS00

DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA

T

C

- Case Temperature - ˚C

dT - Percentage of Rated Power - %

0

20 40 60 80 100 120 140 160

20

40

60

80

100

0

TOTAL POWER DISSIPATION vs. CASE TEMPERATURE

T

C

- Case Temperature - ˚C

P

T

- Total Power Dissipation - W

0

20 40 60 80 100 120 140 160

40

30

20

10

0

FORWARD BIAS SAFE OPERATING AREA

100

2SK3108

DS(on)

10

1

- Drain Current - A

D

I

0.1

R

I

D(DC)

TC = 25 ˚C Single Pulse

1

V

DS -

I

D(pulse)

PW = 10

Limited

Power Dissipation Limited

3 ms

10 ms

100 ms

1 ms

100

µs

10 100 1000

Drain to Source Voltage - V

TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH

1 000

100

10

1

Rth(ch-A) = 62.5˚C/W

Rth(ch-C) = 5˚C/W

(t) - Transient Thermal Resistance - ˚C/W

th

r

0.1

0.01 10

Single Pulse

µ

100

µ

1 m 10 m 100 m 1 10 100 1 000

PW - Pulse Width - s

Data Sheet D13331EJ1V0DS00

5

2SK3108

SINGLE AVALANCHE ENERGY vs. INDUCTIVE LOAD

L

- Inductive Load - mH

I

AS

- Single Avalanche Energy - A

0.1

1

10

100

10

1

0.01

VDD = 100 V VGS = 20 V 0 V RG = 25 Ω Starting T

ch

= 25˚C

IAS = 8.0 A

E

AS

= 51 mJ

SINGLE AVALANCHE ENERGY DERATING FACTOR

Starting T

ch

- Starting Channel Temperature - ˚C

Energy Defrating Factor - %

50

75

100

80

60

40

20

0

25

VDD = 100 V VGS = 20 V 0 V RG = 25 Ω I

AS

8.0 A

125 150

6

Data Sheet D13331EJ1V0DS00

PACKAGE DRAWING(Unit : mm)

Isolated TO-220 (MP-45F)

2SK3108

10.0±0.3

3.2±0.2

φ

3±0.1

15.0±0.3

4±0.2

0.7±0.1 1.3±0.2

1.5±0.2

2.54 TYP.2.54 TYP.

123

4.5±0.2

12.0±0.213.5 MIN.

0.65±0.1

1.Gate

2.Drain

3.Source

2.7±0.2

2.5±0.1

EQUIVALENT CIRCUIT

Drain

Body

Gate

Gate Protection Diode

Source

Diode

The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device.

Data Sheet D13331EJ1V0DS00

7

2SK3108

• The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

• No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document.

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• Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information.

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M7 98. 8