National Semiconductor USBN9603 Technical data
- May 1998
June 2003
Revision 1.3
USBN9603/USBN9604 Universal Serial Bus
Full Speed Node Controller with Enhanced DMA Support
USBN9603/USBN9604 Universal Serial Bus Full Speed Node Controller with Enhanced DMA Support
General Description
The USBN9603/4 are integrated, USB Node controllers.
Other than the reset mechanism for the clock generation circuit, these two devices are identical. All references to “the
device” in this document refer to both devices, unless otherwise noted.
The device provides enhanced DMA support with many automatic data handling features. It is compatible with USB
specification versions 1.0 and 1.1, and is an advanced version of the USBN9602.
The device integrates the required USB transceiver with a
3.3V regulator, a Serial Interface Engine (SIE), USB endpoint (EP) FIFOs, a versatile 8-bit parallel interface, a clock
generator and a MICROWIRE/PLUS™ interface. Seven
endpoint pipes are supported: one for the mandatory control endpoint and six to support interrupt, bulk and isochronous endpoints. Each endpoint pipe has a dedicated FIFO,
8 bytes for the control endpoint and 64 bytes for the other
endpoints. The 8-bit parallel interface supports multiplexed
and non-multiplexed style CPU address/data buses. A programmable interrupt output scheme allows device configuration for different interrupt signaling requirements.
Block Diagram
CS RD WR
A0/ALE D7-0/AD7-0
Outstanding Features
●
Low EMI, low standby current, 24 MHz oscillator
●
Advanced DMA mechanism
●
Fully static HALT mode with asynchronous wake-up
for bus powered operation
●
5V or 3.3V operation
●
Improved input range 3.3V signal voltage regulator
●
All unidirectional FIFOs are 64 bytes
●
Power-up reset and startup delay counter simplify system design
●
Simple programming model controlled by external controller
●
Available in two packages
— USBN9603/4SLB: small footprint for new designs
and portable applications
— USBN9603/4-28M: standard package, pin-to-pin
compatible with USBN9602-28M
INTR
MODE1-0
Microcontroller Interface
Endpoint/Control FIFOs
Serial Interface Engine (SIE)
Media Access Controller (MAC)
Physical Layer Interface (PHY)
Transceiver
D+ D-
National Semiconductor is a registered trademark of National Semiconductor Corporation.
All other brand or product names are trademarks or registered trademarks of their respective holders.
Upstream Port
VReg
24 MHz
Oscillator
Clock
Generator
Clock
Recovery
USB Event
Detect
RESET
V
CC
GND
XIN
XOUT
CLKOUT
V3.3
AGND
© National Semiconductor Corporation, 2003
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Features
●
Full-speed USB node device
●
Integrated USB transceiver
●
Supports 24 MHz oscillator circuit with internal 48
MHz clock generation circuit
●
Programmable clock generator
●
Serial Interface Engine (SIE) consisting of Physical
Layer Interface (PHY) and Media Access Controller
USBN9603/USBN9604
(MAC), USB Specification 1.0 and 1.1 compliant
●
Control/Status register file
●
USB Function Controller with seven FIFO-based Endpoints:
— One bidirectional Control Endpoint 0 (8 bytes)
— Three Transmit Endpoints (64 bytes each)
— Three Receive Endpoints (64 bytes each)
●
8-bit parallel interface with two selectable modes:
— Non-multiplexed
— Multiplexed (Intel compatible)
●
Enhanced DMA support
— Automatic DMA (ADMA) mode for fully CPU-inde-
pendent transfer of large bulk or ISO packets
— DMA controller, together with the ADMA logic, can
transfer a large block of data in 64-byte packets via
the USB
— Automatic Data PID toggling/checking and NAK
packet recovery (maximum 256x64 bytes of data =
16K bytes)
●
MICROWIRE/PLUS interface
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2
Table of Contents
1.0 Signal/Pin Connection and Description
1.1 CONNECTION DIAGRAMS ........................................................................................................6
1.2 DETAILED SIGNAL/PIN DESCRIPTIONS ..................................................................................7
1.2.1 Power Supply ................................................................................................................ 7
1.2.2 Oscillator, Clock and Reset........................................................................................... 7
1.2.3 USB Port .......................................................................................................................8
1.2.4 Microprocessor Interface............................................................................................... 8
Functional Overview
2.0
2.1 TRANSCEIVER .........................................................................................................................10
2.2 VOLTAGE REGULATOR (VREG) .............................................................................................10
2.3 SERIAL INTERFACE ENGINE (SIE) .........................................................................................10
2.4 ENDPOINT PIPE CONTROLLER (EPC) ...................................................................................12
2.5 MICROCONTROLLER INTERFACE .........................................................................................12
3.0 Parallel Interface
USBN9603/USBN9604
3.1 NON-MULTIPLEXED MODE .....................................................................................................13
3.1.1 Standard Access Mode ...............................................................................................14
3.1.2 Burst Mode ..................................................................................................................14
3.1.3 User Registers .............................................................................................................14
3.2 MULTIPLEXED MODE ..............................................................................................................15
4.0 Direct Memory Access (DMA) Support
4.1 STANDARD DMA MODE (DMA) ...............................................................................................16
4.2 AUTOMATIC DMA MODE (ADMA) ...........................................................................................17
5.0 MICROWIRE/PLUS Interface
5.1 OPERATING COMMANDS .......................................................................................................19
5.2 READ AND WRITE TIMING ......................................................................................................20
6.0 Functional Description
6.1 FUNCTIONAL STATES .............................................................................................................22
6.1.1 Line Condition Detection .............................................................................................22
6.1.2 Functional State Transition ..........................................................................................22
6.2 ENDPOINT OPERATION ..........................................................................................................24
6.2.1 Address Detection .......................................................................................................24
6.2.2 Transmit and Receive Endpoint FIFOs .......................................................................24
6.2.3 Programming Model ....................................................................................................28
6.3 POWER SAVING MODES ........................................................................................................28
6.4 CLOCK GENERATION ..............................................................................................................29
7.0 Register Set
7.1 CONTROL REGISTERS ...........................................................................................................30
7.1.1 Main Control Register (MCNTRL) ............................................................................... 30
3
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Table of Contents (Continued)
7.1.2 Clock Configuration Register (CCONF)...................................................................... 31
7.1.3 Revision Identifier (RID) ..............................................................................................31
7.1.4 Node Functional State Register (NFSR) ..................................................................... 32
7.1.5 Main Event Register (MAEV) .......................................................................................32
7.1.6 Main Mask Register (MAMSK) ....................................................................................33
7.1.7 Alternate Event Register (ALTEV).............................................................................. 33
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7.2 TRANSFER REGISTERS ..........................................................................................................36
7.1.8 Alternate Mask Register (ALTMSK) ............................................................................34
7.1.9 Transmit Event Register (TXEV) .................................................................................34
7.1.10 Transmit Mask Register (TXMSK) ...............................................................................35
7.1.11 Receive Event Register (RXEV) ................................................................................. 35
7.1.12 Receive Mask Register (RXMSK) ...............................................................................35
7.1.13 NAK Event Register (NAKEV) .................................................................................... 36
7.1.14 NAK Mask Register (NAKMSK) ...................................................................................36
7.2.1 FIFO Warning Event Register (FWEV) ....................................................................... 36
7.2.2 FIFO Warning Mask Register (FWMSK) .....................................................................37
7.2.3 Frame Number High Byte Register (FNH) .................................................................. 37
7.2.4 Frame Number Low Byte Register (FNL) ....................................................................37
7.2.5 Function Address Register (FAR) ................................................................................38
7.2.6 DMA Control Register (DMACNTRL).......................................................................... 38
7.2.7 DMA Event Register (DMAEV) ....................................................................................39
7.2.8 DMA Mask Register (DMAMSK) .................................................................................40
7.2.9 Mirror Register (MIR) ...................................................................................................41
7.2.10 DMA Count Register (DMACNT) .................................................................................41
7.2.11 DMA Error Register (DMAERR).................................................................................. 41
7.2.12 Wake-Up Register (WKUP) ........................................................................................ 42
7.2.13 Endpoint Control 0 Register (EPC0) ............................................................................43
7.2.14 Transmit Status 0 Register (TXS0) ............................................................................. 43
7.2.15 Transmit Command 0 Register (TXC0) ..................................................................... 44
7.2.16 Transmit Data 0 Register (TXD0) ................................................................................44
7.2.17 Receive Status 0 Register (RXS0) ..............................................................................44
7.2.18 Receive Command 0 Register (RXC0) ....................................................................... 45
7.2.19 Receive Data 0 Register (RXD0) ................................................................................ 45
7.2.20 Endpoint Control X Register (EPC1 to EPC6) .............................................................46
7.2.21 Transmit Status X Register (TXS1, TXS2, TXS3) .......................................................46
7.2.22 Transmit Command X Register (TXC1, TXC2, TXC3) ................................................47
7.2.23 Transmit Data X Register (TXD1, TXD2, TXD3) .........................................................48
7.2.24 Receive Status X Register (RXS1, RXS2, RXS3) .......................................................48
7.2.25 Receive Command X Register (RXC1, RXC2, RXC3) ................................................49
7.2.26 Receive Data X Register (RXD1, RXD2, RXD3) .........................................................50
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Table of Contents (Continued)
7.3 REGISTER MAP ........................................................................................................................50
Device Characteristics
8.0
8.1 ABSOLUTE MAXIMUM RATINGS ............................................................................................52
8.2 DC ELECTRICAL CHARACTERISTICS ...................................................................................52
8.3 AC ELECTRICAL CHARACTERISTICS ....................................................................................53
8.4 PARALLEL INTERFACE TIMING (MODE1-0 = 00B) ................................................................54
8.5 PARALLEL INTERFACE TIMING (MODE1-0 = 01B) ................................................................55
8.6 DMA SUPPORT TIMING ...........................................................................................................57
8.7 MICROWIRE INTERFACE TIMING (MODE1-0 = 10B) .............................................................58
8.8 RESET TIMING) ........................................................................................................................58
USBN9603/USBN9604
5
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1.0 Signal/Pin Connection and Description
1.1 CONNECTION DIAGRAMS
D2
27
USBN9603/USBN9604
28
D1
D0/SO
26
A0/ALE/SI
DACK
25
24
DRQ
23
INTR
22
D3
D4
D5
D6
D7
RESET
AGND
1
2
3
4
5
6
7
CS
RD
WR/SK
INTR
DRQ
DACK
A0/ALE/SI
D0/SO
D1
D2
D3
D4
D5
D6
28-Pin CSP
9
8
V3.3
10
D+
USBN9603/4SLB
1
2
3
4
5
6
7
28-Pin SO
8
9
10
11
12
13
14
21
WR/SK
20
RD
CS
19
CLKOUT
18
XOUT
17
XIN
16
MODEO
15
11
12
13
14
GND
V
CC
GND
28
27
26
25
24
23
22
21
20
19
18
17
16
15
MODE1
CLKOUT
XOUT
XIN
MODE0
MODE1
GND
Vcc
GND
D–
D+
V3.3
AGND
RESET
D7
D−
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USBN9603/4-28M
6
1.0 Signal/Pin Connection and Description (Continued)
1.2 DETAILED SIGNAL/PIN DESCRIPTIONS
1.2.1 Power Supply I/O Name Description
NA Vcc Digital Power Supply (V
level as GND and then raised to the required V
to be set to their reset values, the clock generator to be reset and stalls the CLKOUT output for
14
2
XIN clock cycles. During this time, no internal register is accessible.
NA GND Digital Power Supply (GND)
NA AGND Analog Power Supply (AGND)
). Power-on reset is detected when the input voltage is at the same
CC
level. The power-on reset causes all registers
cc
USBN9603/USBN9604
NA V3.3 Transceiver 3.3V Voltage Supply. This pin can be used as the internal 3.3V voltage regulator
output. The regulator is intended to power only the internal transceiver and one external pull-up.
An external 1 µF de-coupling capacitor is required on this pin. The voltage regulator output is disabled upon reset. When the internal voltage regulator is left disabled, this pin must be used as a
3.3V supply input for the internal transceiver. This is the case during 3.3V operation.
1.2.2 Oscillator, Clock and Reset I/O Name Description
NA XIN Crystal Oscillator Input. Input for internal 24 MHz crystal oscillator circuit. A 24 MHz funda-
mental crystal may be used.
NA XOUT Crystal Oscillator Output
O CLKOUT Clock Output. This programmable clock output may be disabled and configured for different
speeds via the Clock Configuration register. After a power-on reset and hardware reset (assertion of
In the USBN9604, a hardware reset causes CLKOUT to stall for 2
RESET), a4 MHz clock signal is output (there may be an initial phase discontinuity).
14
XIN clock cycles while the
internal DLL is synchronized to the external reference clock.
I RESET Reset. Activelow, assertion of RESETindicates a hardware reset, which causes all registers
in the device to revert to their reset values.
In the USBN9604, the hardware reset action is identical to a power-on reset. Signalconditioning is provided on this input to allow use of a simple, RC power-on reset circuit.
Oscillator Circuit
The XIN and XOUT pins may be connected to make a 24 MHz closed-loop, crystal-controlled oscillator. Alternately, an external 24 MHz clock source may be used as the input clock for the device. The internal crystal oscillator uses a 24 MHz
fundamental crystal. See Table 1 for typical component values and Figure 1 for the crystal circuit. For a specific crystal,
please consult the manufacturer for recommended component values.
If an external clock source is used, it is connected to XIN. XOUT should remain unconnected. Stray capacitance and inductance should be kept as low as possible in the oscillator circuit. Trace lengths should be minimized by positioning the crystal
and external components as close as possible to the XIN and XOUT pins.
Table 1. Approximate Component Values
Component Parameters Values Tolerance
Crystal Resonator Resonance Frequency 24 MHz 2500 ppm
Type AT-Cut
(max)
Maximum Serial Resistance 50 Ω
Maximum Shunt Capacitance 10 pF
Load Capacitance 20 pF
Resistor R1
1MΩ±5%
7
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1.0 Signal/Pin Connection and Description (Continued)
Component Parameters Values Tolerance
Resistor R2
Capacitor C1
Capacitor C2
USBN9603/USBN9604
External Elements
0 ΝΑ
15 pF ±20%
15 pF ±20%
Choose C1 and C2 capacitors (see Figure 1) to match the crystal’s load capacitance. The load capacitance C
the crystal is comprised of C1 in series with C2, and in parallel with the parasitic capacitance of the circuit. The parasitic
capacitance is caused by the chip package, board layout and socket (if any), and can vary from 0 to 8 pF. The rule of thumb
in choosing these capacitors is:
= (C1*C2)/(C1+C2)+C Parasitic
C
L
XIN
XTAL
C1
R1
XOUT
C2
R2
Figure 1. Typical Oscillator Circuit
“seen” by
L
1.2.3 USB Port I/O Name Description
I/O D+ USB D+ Upstream Port. This pin requires an external 1.5k pull-up to 3.3V to signal full speed
operation.
I/O D– USB D– Upstream Port
1.2.4 Microprocessor Interface I/O Name Description
I MODE1-0 Interface Mode. Each of these pins should be hard-wired to V
or GND to select the inter-
CC
face mode:
MODE1-0 = 00. Mode 0: Non-multiplexed parallel interface mode
MODE1-0 = 01. Mode 1: Multiplexed parallel interface mode
MODE1-0 = 10. Mode 2: MICROWIRE interface mode
MODE1-0 = 11. Mode 3: Reserved
Note: Mode 3 also selects the MICROWIRE interface mode in the USBN9602, but this mode
should be reserved to preserve compatibility with future devices.
I
DACK DMAAcknowledge. This active low signal is only used if DMA is enabled. If DMA is not used,
this pin must be tied to V
CC
.
O DRQ DMA Request. This pin is used for DMA request only if DMA is enabled.
O INTR Interrupt. The interrupt signal modes (active high, active low or open drain) can be config-
ured via the Main Control register. During reset, this signal is TRI-STATE
I
I
CS Chip Select. Active low chip select
RD Read. Active low read strobe, parallel interface
.
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1.0 Signal/Pin Connection and Description (Continued)
I WR Write. Active low write strobe, parallel interface
SK MICROWIRE Shift Clock. Mode 2
IA0A0 Address Bus Line. Mode 0, parallel interface
ALE Address Latch Enable. Mode 1, parallel interface
SI MICROWIRE Serial Input. Mode 2
I/O D0 Data Bus Line D0. Mode 0
AD0 Address/Data Bus LIne AD0. Mode 1
SO MICROWIRE Serial Output. Mode 2
I/O D1 Data Bus Line D1. Mode 0
AD1 Address/Data Bus Line AD1. Mode 1
I/O D2 Data Bus Line D2. Mode 0
AD2 Address/Data Bus Line AD2. Mode 1
I/O D3 Data Bus Line D3. Mode 0
AD3 Address/Data Bus Line AD3. Mode 1
I/O D4 Data Bus Line D4. Mode 0
USBN9603/USBN9604
AD4 Address/Data Bus Line AD4. Mode 1
I/O D5 Data Bus Line D5. Mode 0
AD5 Address/Data Bus Line AD5. Mode 1
I/O D6 Data Bus Line D6. Mode 0
AD6 Address/Data Bus Line AD6. Mode 1
I/O D7 Data Bus Line D7. Mode 0
AD7 Address/Data Bus Line AD7. Mode 1
9
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2.0 Functional Overview
The device is a Universal Serial Bus (USB) Node controller compatible with USB Specification, 1.0 and 1.1. It integrates onto
a single IC the required USB transceiver with a 3.3V regulator, the Serial Interface Engine (SIE), USB endpoint FIFOs, a
versatile (8-bit parallel or serial) interface and a clock generator. A total of seven endpoint pipes are supported: one bidirectional for the mandatory control EP0 and an additional six for unidirectional endpoints to support USB interrupt, bulk and
isochronous data transfers. The 8-bit parallel interface supports multiplexed and non-multiplexed style CPU address/data
buses. The synchronous serial MICROWIRE interface allows adapting to CPUs without external address/data buses. A programmable interrupt output scheme allows adapting to different interrupt signaling requirements.
Refer to Figure 2 for the major functional blocks, described in the following sections.
2.1 TRANSCEIVER
USBN9603/USBN9604
The device contains a high-speed transceiver which consists of three main functional blocks:
— Differential receiver
— Single-ended receiver with on-chip voltage reference
— Transmitter with on-chip current source.
This transceiver meets the performance requirements described in Chapter 7 of the USB Specification, Version 1.1.
To minimize signal skew, the differential output swings of the transmitter are well balanced. Slew-rate control is used on the
driver to minimize radiated noise and crosstalk. The drivers support TRI-STATE operation to allow bidirectional, half-duplex
operation of the transceiver.
The differential receiver operates over the complete common mode range, and has a delay guaranteed to be larger than
that of the single-ended receivers. This avoids potential glitches in the Serial Interface Engine (SIE) after single-ended zeros.
Single-ended receivers are present on each of the two data lines. These are required, in addition to the differential receiver, to
detect an absolute voltage with a switching threshold between 0.8V and 2.0V (TTL inputs). To increase V
glitching, a voltage reference sets the single-ended switching reference. An external 1.5 ± 5% KΩ resistor is required on D+ to
indicate that this is a high-speed node. This resistor should be tied to a voltage source between 3.0V and 3.6V, and referenced
to the local ground, such as the output provided on pin V3.3.
rejection, without
cc
2.2 VOLTAGE REGULATOR (VREG)
The voltage regulator provides 3.3V for the integrated transceiver from 5.0V device power or USB bus power. This output
can be used to supply power to the 1.5 KΩ pull-up resistor. This output must be decoupled with a 1 µF tantalum capacitor
to ground. It can be disabled under software control to allow using the device in a 3.3V system.
2.3 SERIAL INTERFACE ENGINE (SIE)
The SIE is comprised of physical (PHY) and Media Access Controller (MAC) modules. The PHY module includes the digitalclock recovery circuit, a digital glitch filter, End Of Packet (EOP) detection circuitry, and bit stuffing and unstuffing logic. The
MAC module includes packet formatting, CRC generation and checking, and endpoint address detection. It provides the
necessary control to give the NAK, ACK and STALL responses as determined by the Endpoint Pipe Controller (EPC) for the
specified endpoint pipe. The SIE is also responsible for detecting and reporting USB-specific events, such as NodeReset,
NodeSuspend and NodeResume. The module output signals to the transceiver are well matched (under 1 nS) to minimize
skew on the USB signals.
The USB specifications assign bit stuffing and unstuffing as the method to ensure adequate electrical transitions on the line
to enable clock recovery at the receiving end. The bit stuffing block ensures that whenever a string of consecutive 1’s is
encountered, a 0 is inserted after every sixth 1 in the data stream. The bit unstuffing logic reverses this process.
The clock recovery block uses the incoming NRZI data to extract a data clock (12 MHz) from a 48 MHz input clock. This
input clock is derived from a 24 MHz oscillator in conjunction with PLL circuitry (clock doubler). This clock is used in the data
recovery circuit. The output of this block is binary data (decoded from the NRZI stream) which can be appropriately sampled
using the extracted 12 MHz clock. The jitter performance and timing characteristics meet the requirements set forth in Chapter 7 of the USB Specification.
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10
2.0 Functional Overview (Continued)
USBN9603/USBN9604
D7-0/AD7-0/SO
A0/ALE/SI
CS RD WR/SK
Microcontroller Interface
(Parallel and Serial)
Endpoint/Control FIFOs
EP2
Endpoint0
EP1
DACK
EP6EP5
StatusControl
DRQ
RX
TX
INTR
MODE1-0
24 MHz
Oscillator
PLL
x 2
Clock
Generator
RESET
V
CC
GND
XIN
XOUT
CLKOUT
SIE
Media Access Controller (MAC)
Physical Layer Interface (PHY)
Transceiver
D+ D-
Figure 2. USBN9603/4 Block Diagram
Upstream Port
VReg
Clock
Recovery
USB Event
Detect
V3.3
AGND
11
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2.0 Functional Overview (Continued)
2.4 ENDPOINT PIPE CONTROLLER (EPC)
The EPC provides the interface for USB function endpoints. An endpoint is the ultimate source or sink of data. An endpoint
pipe facilitates the movement of data between USB and memory, and completes the path between the USB host and the
function endpoint. According to the USB specification, up to 31 such endpoints are supported at any given time. USB allows
a total of 16 unidirectional endpoints for receive and 16 for transmit. As the control endpoint 0 is always bidirectional, the
total number is 31. Seven endpoint pipes with the same function address are supported. See Figure 3 for a schematic diagram of EPC operation.
A USB function is a USB device that is able to transmit and receive information on the bus. A function may have one or more
configurations, each of which defines the interfaces that make up the device. Each interface, in turn, is composed of one or
USBN9603/USBN9604
more endpoints.
Each endpoint is an addressable entity on USB and is required to respond to IN and OUT tokens from the USB host (typically
a PC). IN tokens indicate that the host has requested to receive information from an endpoint, and OUT tokens indicate that
it is about to send information to an endpoint.
On detection of an IN token addressed to an endpoint, the endpoint pipe should respond with a data packet. If the endpoint
pipe is currently stalled, a STALL handshake packet is sent under software control. If the endpoint pipe is enabled but no
data is present, a NAK (Negative Acknowledgment) handshake packet is sent automatically. If the endpoint pipe is isochronous and enabled but no data is present, a bit stuff error followed by an end of packet is sent on the bus.
Similarly, on detection of an OUT token addressed to an endpoint, the endpoint pipe should receive a data packet sent by
the host and load it into the appropriate FIFO. If the endpoint pipe is stalled, a STALL handshake packet is sent. If the endpoint pipe is enabled but no buffer is present for data storage, a NAK handshake packet is sent. If the endpoint is isochronous and enabled but cannot handle the data, no handshake packet is sent.
A disabled endpoint does not respond to IN, OUT, or SETUP tokens.
The EPC maintains separate status and control information for each endpoint pipe.
For IN tokens, the EPC transfers data from the associated FIFO to the host. For OUT tokens, the EPC transfers data in the
opposite direction.
USB
USB SIE
Function
Address
Compare
EP0
EPB
EPC.
EPY
EPZ
Control Registers
FIFOs
Control Endpoint Pipe
EPA
Control Registers
FIFO
Receive Endpoint Pipes
EPX
Control Registers
FIFO
Transmit Endpoint Pipes
DMA
Controller
Microcontroller
Interface
Figure 3. EPC Operation
2.5 MICROCONTROLLER INTERFACE
The device can be connected to a CPU or microcontroller via the 8-bit parallel or MICROWIRE interface. The interface type
is selected by the input mode pins MODE0 and MODE1. In addition, a configurable interrupt output is provided. The interrupt
type can be configured to be either open-drain active-low or push-pull active high or low.
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3.0 Parallel Interface
The parallel interface allows the device to function as a CPU or microcontroller peripheral. This interface type and its addressing mode (multiplexed or non-multiplexed) is determined via device input pins MODE0 and MODE1.
3.1 NON-MULTIPLEXED MODE
Non-multiplexed mode uses the control pins
in Figure 4. This mode is selected by tying both the MODE1 and MODE0 pins to GND.
CS, RD, WR, the address pin A0 and the bidirectional data bus D7-0 as shown
USBN9603/USBN9604
CS
A0
WR
RD
D7-0
Figure 4. Non-Multiplexed Mode Block Diagram
The CPU has direct access to the DATA_IN, DATA_OUT and ADDR registers. Reading and writing data to the device can
be done either in standard access or burst mode. See Figure 5 for timing information.
DATA_IN
DATA_OUT
ADDR
0x00
Data In
Data Out
Address
0x3F
Register File
CS
A0
RD
WR
D7-0
OutInput
Write Address
Figure 5. Non-Multiplexed Mode Timing Diagram
Read Data Burst Read Data
13
Out
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3.0 Parallel Interface (Continued)
3.1.1 Standard Access Mode
The standard access sequence for non-multiplexed mode is to write the address to the ADDR register and then read or write
the data from/to the DATA_OUT/DATA_IN register. The DATA_OUT register is updated after writing to the ADDR register.
The ADDR register or the DATA_OUT/DATA_IN register is selected with the A0 input.
3.1.2 Burst Mode
In burst mode, the ADDR register is written once with the desired memory address of any of the on-chip registers. Then
consecutive reads/writes are performed to the DATA_IN/DATA_OUT register without previously writing a new address. The
content of the DATA_OUT register for read operations is updated once after every read or write.
USBN9603/USBN9604
3.1.3 User Registers
The following table gives an overview of the parallel interface registers in non-multiplexed mode.
The reserved bits return undefined data on read and should be written with 0.
A0 Access bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
0 Read DATA_OUT
0 Write DATA_IN
1 Read Reserved
1 Write Reserved ADDR5-0
Address Register (ADDR)
The ADDR register acts as a pointer to the internal memory. This register is write only and is cleared on reset.
Data Output Register (DATA_OUT)
The DATA_OUT register is updated with the contents of the memory register to which the ADDR register is pointing. Update
occurs under the following conditions:
1. After the ADDR register is written.
2. After a read from the DATA_OUT register.
3. After a write to the DATA_IN register.
This register is read only and holds undefined data after reset.
Data Input Register (DATA_IN)
The DATA_IN register holds the data written to the device address to which ADDR points. This register is write only and is
cleared on reset.
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3.0 Parallel Interface (Continued)
3.2 MULTIPLEXED MODE
Multiplexed mode uses the control pins
bus AD7-0 as shown in Figure 6. This mode is selected by tying MODE1 to GND and MODE0 to V
into the ADDR register when ALE is high. Data is output/input with the next active
accessible in this interface mode.
Figure 7 shows basic timing of the interface in Multiplexed mode.
CS, RD, WR, the address latch enable signal ALE and the bidirectional address data
RD or WR signal. All registers are directly
. Theaddress is latched
CC
USBN9603/USBN9604
CS
WR
RD
AD7-0
ALE
ALE
Data Out
EN
Figure 6. Multiplexed Mode Block Diagram
ADDR
Address
Data In
0x00
0x3F
Register File
CS
RD or WR
AD7-0
ADDR
Figure 7. Multiplexed Mode Basic Read/Write Timing
15
DATA
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4.0 Direct Memory Access (DMA) Support
The device supports DMA transfers with an external DMA controller from/to endpoints 1 to 6. This mode uses the device
pins DRQ and
with parallel interface mode (MODE1 must be grounded). The read or write address is generated internally and the state of
the A0/ALE pin is ignored during a DMA cycle.
The DMA support logic has a lower priority than the parallel interface.
comes active,
given time to issue a DMA request when data is received or transmitted.
Two different DMA modes are supported: standard and automatic.
4.1 STANDARD DMA MODE (DMA)
USBN9603/USBN9604
To enable DMA transfers in standard DMA mode, the following steps must be performed:
1. The local CPU programs the DMA controller for fly-by demand mode transfers. In this mode, transfers occur only when
the device requests them via the DRQ pin. The data is read/written from/to the device receive/transmit FIFO and written/read into/from local memory during the same bus transaction.
2. The DMA address counter is programmed to point to the destination memory block in the local shared memory, and the
Byte Count register is programmed with the number of bytes in the block to be transferred. If required the automatic error
handling should be enabled at this point along with the error handling counter. In addition the user needs to set the respective Endpoint enable bit.
3. The DMA Enable bit and DMA Source bits are set in the DMACNTRL register.
4. The USB host can now perform USB bulk or isochronous data transfers over the USB bus to the receive FIFO or from
the transmit FIFO in the device.
5. If the FIFOs warning limit is reached or the transmission/reception is completed, a DMA request/acknowledge sequence
is initiated for the predetermined number of bytes. The time at which a DMA request is issued depends on the selected
DMA mode (controlled by the DMOD bit in the DMACNTRL register), the current status of the endpoint FIFO, and the
FIFO warning enable bits. A DMA request can be issued immediately.
6. After the DMA controller has granted control of the bus, it drives a valid memory address and asserts
WR, thus transferring a byte from the receiveFIFO to memory, or from memory to the transmit FIFO. This process continues until the DMA byte count, within the DMA controller, reaches zero.
7. After the programmed amount of data is transferred, the firmware must do one of the following (depending on the transfer
direction and mode):
— Queue the new data for transmission by setting the TX_EN bit in the TXCx register.
— Set the End Of Packet marker by setting the TX_LAST bit in the TXCx register. Re-enable reception by setting the
RX_EN bit in the RXCx register.
— Check if the last byte of the packet was received (RX_LAST bit in the RXSx register).
The DMA transfer can be halted at any time by resetting the DMA Request Enable bit. If the DMA Request Enable bit is
cleared during the middle of a DMA cycle, the current cycle is completed before the DMA request is terminated.
See Figures 8 and 9 for the transmit and receive sequences using standard DMA mode.
DACK in addition to the parallel interface pins RD or WR and D7-0 data pins. DMA mode can only be used
CS must stay inactive during a DMA cycle. If CS be-
DACK is ignored and a regular read/write operation is performed. Only one endpoint can be enabled at any
DACK and RD or
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MIcrocontroller
Set up DMA
Figure 8. Transmit Operation in Standard DMA Mode
Microcontroller
Set up DMA
Transaction
Read FIFO
16
USB
DMA
DMA
Fill FIFO
Microcontroller
Enable RX
DMA
Fill FIFO
Microcontroller
Enable RX
Figure 9. Receive Operation in Standard DMA Mode
Microcontroller
Enable TX
USB
Transaction
time
time
4.0 Direct Memory Access (DMA) Support (Continued)
4.2 AUTOMATIC DMA MODE (ADMA)
The ADMA mode allows the CPU to transfer independently large bulk or isochronous data streams to or from the USB bus.
The application’s DMA controller, together with the ADMA logic, have the capability to split a large amount of data and transfer it in (FIFO size) packets via the USB. In addition, automatic error handling is performed in order to minimize firmware
intervention. The number of transferred data stream bytes must be of a modulo 64 size. The maximum amount of data is
restricted to 256*64 bytes = 16 Kbytes.
To enable an ADMA transfer, the following steps must be performed:
1. The local CPU programs the DMA controller for fly-by demand mode transfers. In this mode, transfers occur only in response to DMA request via the DRQ pin. The data is read/written from/to the receive/transmit FIFO and written/read into/from local memory during the same bus transaction.
2. The DMA address counter is programmed to point to the destination memory block in the local shared memory, and the
Byte Count register is programmed with the number of bytes in the block to be transferred. The DMA Count register must
be configured with the number of packets to be received or transmitted. Ifrequired, the Automatic Error Handling register
must also be configured at this time.
3. The ADMA enable bit must be set prior to, or at the same time as the DMA enable bit. The DMA enable bit must be
cleared before enabling ADMA mode.
4. The DMA Request Enable bit and DMA Source bits are set in the device.The respective endpoint Enable bit must also
be set.
5. The USB host can now perform USB bulk or isochronous data transfers over the USB bus to the receive FIFO or from
the transmit FIFO. Steps 5 to 7 of the normal DMA mode are perfromed automatically. The ADMA is stopped either when
the last packet is received or when the DMA Count register has reached the value zero.
See Figures 10 and 11 for the transmit and receive sequences using ADMA mode. See Figures 12 and 13 for the basic
DMA write timing and read timing.
USBN9603/USBN9604
Microcontroller
Set up ADMA
Microcontroller
Set up ADMA
DMA
Fill FIFO
Figure 10. Transmit Operation Using ADMA Mode
USB
Transaction
Figure 11. Receive Operation Using ADMA Mode
USB
Transaction
DMA
Read FIFO
DMA
Fill FIFO
USB
Transaction
USB
Transaction
DMA
Read FIFO
USB
Last
Transaction
DMA
Last
Read FIFO
time
time
17
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4.0 Direct Memory Access (DMA) Support (Continued)
DRQ
DACK
USBN9603/USBN9604
WR
D7-0
DRQ
DACK
RD
D7-0
Input
Figure 12. DMA Write to USBN9603/4
Output
Figure 13. DMA Read from USBN9603/4
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