NATIONAL SEMICONDUCTOR TP3410WG304, TP3410J304, TP3410J304-X Datasheet

TL/H/9151

TP3410 ISDN Basic Access Echo-Cancelling U Transceiver

September 1994

TP3410 ISDN Basic Access
Echo-Cancelling 2B1Q U Transceiver

General Description

The TP3410 is a complete monolithic transceiver for ISDN
Basic Access data transmission at either end of the U inter­face. Fully compatible with ANSI specification T1.601, it is
built on National’s advanced double-metal CMOS process,
and requires only a single

a

5V power supply. A total of
160 kbps full-duplex transmission on a single twisted-pair is
provided, with user-accessible channels including 2 ‘B’
channels, each at 64 kbps, 1 ‘D’ channel at 16 kbps, and an
additional 4 kbps for loop maintenance. 12 kbps of band­width is reserved for framing. 2B1Q Line coding is used, in
which pairs of binary bits are coded into 1 of 4 quantum
levels for transmission at 80k symbols/sec (hence 2 Binary/
1 Quaternary). To meet the very demanding specifications
for

k

1 in 10e7 Bit Error Rate even on long loops with cross­talk, the device includes 2 Adaptive Digital Signal Proces­sors, 2 Digital Phase-locked Loops and a controller for auto­matic activation.

The digital interface on the device can be programmed for
compatibility with either of two types of control interface for
chip control and access to all spare bits. In one mode a
Microwire serial control interface is used together with a
2B

a

D digital interface which is compatible with the Time-di­vision Multiplexed format of PCM Combo devices and back­planes. This mode allows independent time-slot assignment
for the 2 B channels and the D channel.

Alternatively, the GCI (General Circuit Interface) may be se­lected, in which the 2B

a

D data is multiplexed together with

control, spare bits and loop maintenance data on 4 pins.

Features

Y

2 ‘B’a‘D’ channel 160 kbps transceiver for LT and NT

Y

Meets ANSI T1.601 U.S. Standard

Y

2B1Q line coding with scrambler/descrambler

Y

Range exceeds 18 kft ofÝ26 AWG

Y l

70 dB adaptive echo-cancellation and equalization

Y

On-chip timing recovery, no precision external
components

Y

Direct connection to small line transformer

Y

Automatic activation controller

Y

Selectable digital interface formats:
Ð TDM with time-slot assigner up to 64 slots, plus

MICROWIRE

TM

control interface
Ð GCI (General Circuit Interface), or
Ð IDL (Inter-chip Digital Link)

Y

Backplane clock DPLL allows free-running XTAL

Y

Elastic data buffers meet Q.502 wander/jitter for Slave­slave mode on PBX Trunk Cards and DLC

Y

EOC and spare bits access with automatic validation

Y

Block error counter

Y

6 loopback test modes

Y

Singlea5V supply, 325 mW active power

Y

20 mW idle mode with line signal ‘‘wake-up’’ detector

Applications

Y

LT, NT-1, NT-2 Trunks, U-TE’s, Regenerators etc.

Y

Digital Loop Carrier

Y

POTS Pair-Gain Systems

Y

Easy Interface to:
Ð Line Card Backplanes
Ð ‘‘S’’ Interface Device TP3420A
Ð Codec/Filter Combos TP3054/7 and TP3075/6
Ð LAPD Processor MC68302, HPC16400
Ð HDLC Controller TP3451

ComboÉand TRI-STATEÉare registeredtrademarks of NationalSemiconductor Corporation.
MICROWIRE

TM

is a trademark of National Semiconductor Corporation.
The General Circuit Interface (G.C.I.) is an interface specification of the Group-of-Four Euro­pean Telecommunications Companies.

Block Diagram

TL/H/9151– 1

Note: Pin names show Microwire mode.

C

1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

Connection Diagrams

Pin Names for MICROWIRE Mode

TL/H/9151– 2

Top View

Pin Names for GCI Mode

TL/H/9151– 3

Top View

Order Number TP3410J

See NS Package Number J28A

Pin Descriptions

Pin

Symbol Description

No.

24 GNDA Negative power supply pins, which must

9 GNDD1 be connected together close to the de-

23 GNDD2 vice. All digital signals are referenced to

these pins, which are normally at the sys­tem 0V (Ground) potential.

5V

CC

A Positive power supply input for the analog

sections, which must be

a

5Vg5% and

must be directly connected to V

CC

D.

8VCCD Positive power supply input for the digital

section, which must be

a

5Vg5% and

must be directly connected to V

CC

A.

21 MCLK/ The 15.36 MHz Master Clock input, which

XTAL requires either a parallel resonance crystal

to be tied between this pin and XTAL2, or
a CMOS logic level clock input from a sta­ble source (a TTL Logic ‘‘1’’ level is not
suitable). This clock does not need to be
synchronized to the system clock (BCLK
and FS), see Section 5.1.

20 XTAL2 The output of the crystal oscillator, which

should be connected to one end of the
crystal, if used; otherwise this pin must be
left open-circuit. Not recommended to
drive additional logic.

10 TS

r/ This pin has 2 functions: in LT mode it is

SCLK an open-drain n-channel TS

r output, which
goes low only during the time-slots as­signed to the B1 and B2 channels at the
Br pin in order to enable the TRI-STATE
control of the backplane line-driver. In NT
mode it is a full CMOS 15.36 MHz syn­chronous clock output which is frequency­locked to the received line signal (unlike
the XTAL pins it is not free-running).

Pin

Symbol Description

No.

22 TSFS The Transmit Superframe Sync pin, which

indicates the start of each 12 ms transmit
superframe at the U Interface. In NT mode
this pin is always an output. In LT mode it
may be selected to be either an input or
CMOS output via Register CR2; when se­lected as an output the signal is a square­wave. Must be tied low if selected as input
yet not driven.

25 LSD

/RSFS This pin is an open-drain n-channel Line

Signal Detector output, which is normally
high-impedance and pulls low only when
the device is powered down and an incom­ing wake-up signal is detected from the
far-end. As an option this pin can be pro­grammed to be an output indicating the
start of the received superframe at the U
interface; an external pull-up resistor is re­quired.
The RSFS signal indicates the start of
each 12 ms receive superframe from the U
Interface and is available in NT and LT
modes. The Received Superframe Synch
clock output is accessible on pin 25 by
writing X’1C04 and X’100C (or X’100E)
during device initialization. See TP3410
users manual AN-913, Part II Section

4.18).

1Lo

a

Transmit 2B1Q signal differential outputs

4Lo

b

to the line transformer. When used with an
appropriate 1:1.5 step-up transformer and
the line coupling circuit recommended in
the Applications section, the line signal
conforms to the output specifications in
the ANSI standard.

2

Pin Descriptions (Continued)

PIN DESCRIPTIONS SPECIFIC TO MICROWIRE MODE
ONLY (MW

e

1)

Pin

Symbol Description

No.

2Li

a

Receive 2B1Q signal differential inputs

3Li

b

from the line transformer. For normal full­duplex operation, these pins should be
connected to the Lo

g

pins through the
recommended coupling circuit, as shown
in the Applications section.

28 MW The Microwire/GCI

Select pin, which must

be tied to V

CC

D to enable the Microwire
Interface with any of the data formats at
the Digital System Interface.

12 BCLK The Bit Clock pin, which determines the

data shift rate for ‘B’ and ‘D’ channel data
on the digital interface side of the device.
When Digital System Interface (DSI) Slave
mode is selected (see Digital Interfaces
section), BCLK is an input which may be
any multiple of 8 kHz from 256 kHz to

4.096 MHz. It need not be synchronous
with MCLK.

When DSI Master mode is selected, this
pin is a CMOS output clock at 256 kHz,
512 kHz, 1.536 MHz, 2.048 MHz or 2.56
MHz, depending on the selection in Com­mand Register 1. It is synchronous with
the data on Bx and Br.

6 FSa In DSI Slave mode, this pin is the Transmit

Frame Sync pulse input, requiring a posi­tive edge to indicate the start of the active
channel time for transmit B1 channel data
into Bx. In DSI Master mode, this pin is a
Frame Sync CMOS output pulse conform­ing with the selected Digital Interface for­mat.

7 FSb In DSI Slave mode, this pin is the Receive

Frame Sync pulse input, requiring a posi­tive edge to indicate the start of the active
channel time of the device for receive B
channel data out from Br (see DSI Format
section). In DSI Master mode this pin is a
Frame Sync CMOS output pulse conform­ing with the selected Digital Interface for­mat.

13 Bx The digital input for B and, if selected, D

channel data to be transmitted to the line;
must be synchronous with BCLK.

11 Br The TRI-STATE output for B and, if select-

ed, D channel data received from the line;
it is synchronous with BCLK.

18 CI The Microwire control channel data input.

19 CO The Microwire control channel TRI-STATE

output for status information. When not
enabled by CS

, this output is high-imped­ance.

*Crystal specifications: 15.36 MHzg50 ppm parallel resonant; R

S

s

20X.

Load with 33 pF to GND each side (

a

7 pF due to pin capacitance).

Pin

Symbol Description

No.

17 CCLK The Microwire control channel Clock input,

which may be asynchronous with BCLK.

27 CS

The Chip Select input, which enables the
Control channel data to be shifted in and
out when pulled low. When high, this pin
inhibits the Control interface.

26 INT

The Interrupt output, a latched open-drain
output signal which is normally high-im­pedance, and goes low to indicate a
change of status of the loop transmission
system. This latch is cleared when the
Status Register is read by the microproc­essor.

16 Dx When the D-port is enabled this pin is the

digital input for D channel data to be trans­mitted to the line clocked by DCLK or
BCLK, see Register CR2. When the D-port
is disabled via CR2, this pin must be tied to
GND.

15 Dr When the D-port is enabled this pin is the

TRI-STATE output for D channel data to
be received from the line clocked by DCLK
or BCLK, see Register CR2.

14 DCLK When the D-port is enabled, in DSI Slave

or Master mode, this is a 16 kHz clock
CMOS output for D channel data. When
the D-port is disabled or not used, this pin
must be left open-circuit.

PIN DESCRIPTIONS SPECIFIC TO GCI MODE ONLY
(MW

e

0)

Pin

Symbol Description

No.

28 MW The Microwire/GCI

select input, which
must be tied to GND to enable the GCI
mode at the Digital System Interface.

27 MO The GCI Master/Slave select input for the

clock direction. Connect this pin low to se­lect BCLK and FSa as inputs i.e., GCI
Slave; Selection of LT or NT mode must
be made in register CR2. When MO is con­nected high, NT Mode is automatically se­lected, and BCLK, FSa and FSb are out­puts, i.e., the GCI Master, see Section 8.

12 BCLK The Bit Clock pin, which controls the shift-

ing of data on the Bx and Br pins, at a rate
of 2 BCLK cycles per data bit. When GCI
Slave mode is selected (see Digital Inter­faces section), BCLK is an input which
may be any multiple of 16 kHz from
512 kHz to 6.144 MHz. It need not be syn­chronous with MCLK.

When GCI Master mode is selected, this
pin is a CMOS output clock at 512 kHz or

1.536 MHz, depending on the connection
of the S2/CLS pin. It is synchronous with
the data on Bx and Br.

3

Pin Descriptions (Continued)

Pin

Symbol Description

No.

13 Bx The digital input for multiplexed B, D and

control data clocked by BCLK at the rate
of 1 data bit per 2 BCLK cycles, and 32
data bits per 8 kHz frame defined by FSa.

11 Br The open-drain n-channel output for multi-

plexed B, D and control data clocked by
BCLK at the rate of 1 data bit per 2 BCLK
cycles, and 32 data bits per 8 kHz frame
defined by FSa. A pull-up resistor is re­quired to define the logical 1 state.

6 FSa In GCI Slave mode (MO connected low),

this pin is the 8 kHz Frame Sync pulse in­put, requiring a positive edge to indicate
the start of the GCI slot time for both
transmit and receive data at Bx and Br. In
GCI Master mode, this pin is the 8 kHz
Frame Sync CMOS output pulse.

Pin

Symbol Description

No.

17 S2/CLS In GCI Slave mode (MO

e

0):

19 S1 input pins S2, S1 and S0 together pro-

7 SO/FSb

(vide a 3-bit binary-coded select port for

the GCI channel number; S2 is the msb.
These pins must be connected either to
V

CC

D or GND to select the 1-of-8 GCI

slots which are available if BCLK

t

4.096

MHz is used.

In GCI Master mode (MO

e

1)
S2/CLS is the GCI Clock Select input.
Connect this pin high to select BCLK

e

1.536 MHz; connect CLS low to select
BCLK

e

512 kHz. SO/FSb is a Frame
Sync CMOS output pulse which identifies
the B2 channel.

18 ES1 While in GCI mode, the ES1, ES2 pins are
16 ES2

( local input pins. The status of the pins can

be accessed via the RXM56 register bits
5,6 corresponding to ES1, ES2.

15 LEC Latched External Control output, which is

the output of a latched bit in the TXM56
Register.

4

Functional Description

1.1 Power-On Initialization

When power is first applied, power-on reset circuitry initializ­es the TP3410 and puts it into the power-down state, in
which all the internal circuits including the Master oscillator
are inactive and in a low power state except for the Line­Signal Detect circuit; the line outputs Lo

a

/Lobare in a
high impedance state. All programmable registers and the
Activation Sequence Controller are reset.

All states in the Command Registers initialize as shown in
their respective code tables. The desired modes for all pro­grammable functions may be selected by writing to these
registers via the control channel (Microwire or Monitor chan­nel, as appropriate). Microwire is functional regardless of
whether the device is powered up or down, whereas the
GCI channel requires the BCLK to be running.

1.2 Power-Up/Power-Down Control

Before powering up the device, the Configuration Registers
should be programmed with the required modes.

In Microwire mode and GCI Slave mode, the device is pow­ered up and the MCLK started by writing the PUP command,
as described in the Activation section. In GCI Master mode,
there are 2 methods of powering up the device: the Bx data
input can be pulled low (local power-up command) or the
10 kHz wake-up tone may be received from the far-end.

The power-down state may be re-entered by writing a Pow­er-down command. In the power-down state, all pro­grammed register data is retained. Also, if the loop had
been successfully activated and deactivated, the adaptive
circuits are ‘‘frozen’’ and the coefficients in the Digital Signal
Processors are stored to enable rapid reactivation (‘‘warm­start’’).

1.3 Reset

A software reset command is provided to enable the clear­ing of the Activation sequencer without disconnecting the
power supply to the device, see the Activation section.

2.0 TRANSMISSION SECTION

2.1 Line Coding And Frame Format

For both directions of transmission, 2B1Q coding is used, as
illustrated in

Figure 1

. This coding rule requires that binary
data bits are grouped in pairs, and each pair is transmitted
as a symbol, the magnitude of which may be 1 out of 4
equally spaced voltage levels (a ‘‘Quat’’). There is no sym­bol value at 0V in this code, the relative quat magnitudes
being

g

1 (the ‘‘inner’’ levels) andg3 (the ‘‘outer’’ levels).
No redundacy is included in this code, and in the limit there
is no bound to the RDS, although scrambling controls the
RDS in a practical sense ( RDS is the Running Digital Sum,
which is the algebraic summation of all symbol values in a
transmission session).

The frame format used in the TP3410 follows the ANSI
standard, shown in Table I. Each complete frame consists
of 120 quats, with a line bit rate of 80 kq/s, giving a frame
duration of 1.5 ms. A 9 quat syncword defines the framing
boundary. Furthermore, a ‘‘superframe’’ consisting of 8
frames is defined in order to provide sub-channels within the
spare bits M1 to M6. Inversion of the syncword defines the
superframe boundary. Prior to transmission, all data, with
the exception of the syncword, is scrambled using a self­synchronizing scrambler to implement the specified 23rd-or­der polynomial. Descrambling is included in the receiver.

First Bit Second Bit

Quat

Pulse Amplitude

(Sign) (Magnitude) (Note 1)

10

a

3

a

2.5V

11

a

1

a

0.83V

01

b

1

b

0.83V

00

b

3

b

2.5V

Note 1: For isolated pulses into a 135X termination with recommended
transformer interface.

TL/H/9151– 25

FIGURE 1. 2B1Q Line-Coding Rule

5

Functional Description (Continued)

Framing 12x(2BaD) Overhead Bits (M1–M6)

Quat Positions 1–9 10–117 118s 118m 119s 119m 120s 120m

Bit Positions 1–18 19–234 235 236 237 238 239 240

Superframe

Ý

Basic Frame

Ý

Sync Word 2BaDM

1

M

2

M

3

M

4

M

5

M

6

1 1 ISW 2BaD eoca1eoca2eoca

3

act 1 1

2SW2B

a

D eocdmeoci1eoci

2

dea 1 febe

3SW2B

a

D eoci3eoci4eoci

5

1 crc

1

crc

2

4SW2B

a

D eoci6eoci7eoci

8

1 crc

3

crc

4

5SW2B

a

D eoca1eoca2eoca

3

1 crc

5

crc

6

6SW2B

a

D eocdmeoci1eoci

2

1 crc

7

crc

8

7SW2B

a

D eoci3eoci4eoci

5

uoa crc9crc

10

8SW2B

a

D eoci6eoci7eoci

8

aib crc

11

crc

12

2,3,... 1 ISW

(a) NetworkxNT

Framing 12x(2BaD) Overhead Bits (M1–M6)

Quat Positions 1–9 10–117 118s 118m 119s 119m 120s 120m

Bit Positions 1 –18 19–234 235 236 237 238 239 240

Superframe

Ý

Basic Frame

Ý

Sync Word 2BaDM

1

M

2

M

3

M

4

M

5

M

6

1 1 ISW 2BaD eoca1eoca2eoca

3

act 1 1

2SW2B

a

D eoc

dm

eoci1eoci

2

ps

1

1 febe

3SW2B

a

D eoci3eoci4eoci

5

ps

2

crc

1

crc

2

4SW2B

a

D eoci6eoci7eoci

8

ntm crc

3

crc

4

5SW2B

a

D eoca1eoca2eoca3cso crc

5

crc

6

6SW2B

a

D eoc

dm

eoci1eoci

2

1 crc

7

crc

8

7SW2B

a

D eoci3eoci4eoci

5

1 crc9crc

10

8SW2B

a

D eoci6eoci7eoci

8

1 crc

11

crc

12

2,3,... 1 ISW

(b) NTxNetwork

Note: 8c1.5 ms Basic Framese12 ms/Superframe. NT-to-Network superframe is offset from Network-to-NT superframe by 60g2 quats (about 0.75 ms). All

bits other than the Sync Word are scrambled.

Symbols & Abbreviations

act

e

start-up bit (e1 during start-up)

aib

e

alarm indication bit (e0 to indicate interrup­tion)

crc

e

cyclic redundacy check: covers 2BaDaM

4

1emost significant bit

2enext significant bit etc.

cso

e

cold-start-only bit (e1 to indicate cold-start­only)

dea

e

turn off bit (e0 to announce turn off)

eoc

e

embedded operations channel

aeaddress bits

dmedata/message indicator (0edata,

1

e

message)

ieinformation (data or message)

febe

e

far end block error bit (e0 for errored super­frame)

ntm

e

NT in test mode bit (e0 to indicate test mode)

ps1, ps2epower status bits (e0 to indicate power prob-

lems)

Quat

e

pair of bits forming quaternary symbol

s

e

sign bit (first in quat)

memagnitude bit (second in quat)

sai

e

S-activation-indication bit (e1 for S/T activity)

uoa

e

U-only-activation bit (e1 to activate S/T)

‘‘1’’

e

reserved bit for future standard (e1)

‘‘1*’’

e

network indicator bit (e1, reserved for network
use)

2B

aDe

user data, bits 19 – 234 in frame

M

e

M-channel, bits 235 –240 in frame

SW/ISWesynchronization word/inverted synchronization

word, bits 1 –18 in frame

TABLE I. 2B1Q Superframe Format and Overhead Bit Assignments

6

Functional Description (Continued)

2.2 Line Transmit Section

Data to be transmitted to the line consists of the customer’s
2B

a

D channel data and the data from the maintenance
processor, plus other ‘‘spare’’ bits in the overhead chan­nels. This data is multiplexed and scrambled prior to addi­tion of the syncword. A pulse waveform synthesizer then
drives the transmit filter, which in turn passes the line signal
to the line driver. The differential line-driver outputs, Lo

a

and Lob, are designed to drive a transformer through an
external termination circuit. A 1:1.5 transformer, designed
as shown in the Applications section, results in a signal am­plitude of nominally 2.5V pk on the line for single quats of
the outer (

g

3) levels. Note, however, that because of the
RDS accumulation of the 2B1Q line code, continuous ran­dom data will produce signal swings considerably greater
than this on the line. Short-circuit protection is included in
the output stage; overvoltage protection must be provided
externally.

2.3 Line Receive Section

The receive input signal should be derived from the trans­former by means of a coupling circuit as shown in the Appli­cations section. At the front-end of the receive section is a
continuous filter followed by a switched-capacitor low-pass
filter, which limits the noise bandwidth. A Hybrid Balance
Filter provides a degree of analog echo-cancellation in or­der to limit the dynamic range of the composite signal. An
A/D converter then samples the composite received signal
prior to the cancellation of the ‘‘echo’’ from the local trans­mitter by means of an adaptive digital transversal filter (i.e.,
the ‘‘echo-canceller’’). Following this, the attenuation and
distortion (inter-symbol interference) of the received signal
from the far-end, caused by the transmission line, are equal­ized by a second adaptive digital filter configured as a Deci­sion Feedback Equalizer (DFE), thereby restoring a ‘‘flat’’
channel response with maximum received eye opening over
a wide spread of cable attenuation characteristics.

From the received line signal, a Timing Recovery circuit
based on a DPLL (Digital Phase-Locked Loop) recovers a
low-jitter clock for optimum sampling of the received sym­bols. The MCLK input provides the reference clock for the
DPLL at 15.36 MHz. Received data is then detected, with
automatic correction for line signal polarity if necessary, and
a flywheel synchronization circuit searches for and locks
onto the frame and superframe syncwords. Frame lock will
be maintained until errored sync words are detected for

480 ms. If a loss-of-sync condition persists for 480 ms the
device will cease transmitting and go into a RESET state.

While the receiver is synchronized, data is descrambled us­ing the specified polynomial, and the individual channels de­multiplexed and passed to their respective processing cir­cuits.

Whenever the loop is deactivated, either powered up or
powered down, a Line Signal Detect circuit is enabled to
detect the presence of an incoming 10 kHz wake-up tone if
the far-end starts to activate the loop. The LSD circuit gen­erates an interrupt and, if the device is powered down, pulls
the LSD

pin low; either of these indicators may be used to
alert an external controller, which must respond with the
appropriate commands to initiate the activation sequence
(see the Activation section).

3.0 ACTIVATION CONTROL: OVERVIEW

The TP3410 contains an automatic sequencer for the com­plete control of the start-up activation sequence specified in
the ANSI standard. Both the ‘‘cold-start’’ and the fast
‘‘warm-start’’ are supported. Interaction with an external
controller requires only Activate Request and Deactivate
Request commands, with the option of inserting breakpoints
in the sequence for additional external control if desired.
Automatic control of the ‘‘act’’ and ‘‘dea’’ bits in the M4 bit
positions is provided, along with the specified 40 ms and
480 ms timers used during deactivation. A 15 second de­fault timer is also included, to prevent system lock-up in the
event of a failed activation attempt. Section 11 gives an
overview of the activation handshake between the TP3410
and the controller. See TP3410 User’s Manual AN-913 for
additional information.

4.0 MAINTENANCE FUNCTIONS: OVERVIEW

4.1 M Channel Processing

In each frame of the superframe there are 6 ‘‘Overhead’’
bits assigned to various control and maintenance functions
of the DSL. Some processing of these bits may be pro­grammed via the Command Registers, while interaction with
an external controller provides the flexibility to take full ad­vantage of the maintenance channels. New data written to
any of the overhead bit Transmit Registers is resynchroniz­ed internally to the next available complete superframe or
half-superframe, as appropriate. In addition, the SFS pin
may be used to indicate the start of each superframe in 1
direction, see

Figure 2

and Register CR2.

TL/H/9151– 26

FIGURE 2. Superframe Sync Pin Timing

7

Functional Description (Continued)

4.2 Embedded Operations Channel

The EOC channel consists of 2 complete 12-bit messages
per superframe, distributed through the M1, M2 and M3 bits
of each half-superframe as shown in Table I. Each message
is composed of 3 fields; a 3-bit address identifying the mes­sage destination, a 1-bit indicator for the data mode, i.e.,
encoded message or raw data, and an 8-bit information
byte. The Microwire port or GCI Monitor Channel provides
access to the complete 12 bits of every message in the TX
EOC and the RXEOC Registers. If one of the defined en­coded messages is received, e.g., Send Corrupted CRC,
then the appropriate Command Register instruction must be
written to the device to invoke the function.

4.3 M4 Bits

The M4 bit position of every frame is a transparent channel
in which are transmitted data bits loaded from the M4 Trans­mit Register TXM4, one byte per superframe. On the re­ceive side the M4 bits from one complete superframe are
sent to a checking circuit which holds each new M4 byte
and compares it against the previous M4 byte(s) for valida­tion prior to sending it to the RXM4 Receive Register; Regis­ter OPR provides several options for control of this valida­tion.

4.4 Spare M5 And M6 Bits

Overhead bits M5 and M6 in frame 1 (M51 and M61) and
M5 in frame 2 (M52) are transparently transmitted from the
Transmit M56 Spare Bit Register to the line. In the receive
direction, data from these bit positions is sent to a checking
circuit which holds the new M5/M6 spare bits and com­pares them against the previous M5/M6 bits for validation
prior to sending them to the Receive M56 Spare Bit Regis­ter; the OPR Register provides several options for control of
this validation.

4.5 CRC Circuit

In the transmit direction an on-chip crc calculation circuit
automatically generates a checksum of the 2B

aDa

M4 bits

using the polynomial x12

a

x11ax3ax2axa1. Once per
superframe the crc is transmitted in the specified M5 and
M6 bit positions (see Table I). In the receive direction a
checksum is again calculated on the same bits as they are
received and, at the end of the superframe, compared
against the crc transmitted with the data. The result of this
comparison generates a ‘‘Far End Block Error’’ bit (the febe
bit), which is transmitted back towards the other end of the
DSL in the next superframe. If there are no errors in a super­frame, febe is set

e

1, and if there is one or more errors

febe is set

e

0.

The TP3410 also includes a readable 8-bit Block Error
Counter BEC1, which is decremented by 1 each superframe
in which febe

e

0 or nebee0 is received. Section 10.5

describes the operation of this counter.

On first application of power, and after the software reset
(X’1880, X’1800), both the ECT1 as well as BEC1 are initial­ized to X’FF. See the Block Error Counter section for more
details.

5.0 DIGITAL INTERFACE: ALL FORMATS

5.1 Clocking

In LT applications (network end of the Loop), the Digital
System Interface (DSI) normally accepts BCLK and FS sig­nals from the network, requiring the selection of DSI or GCI
Slave mode in Register CR1. A Digital Phase-Locked Loop
(DPLL

Ý

2) on the TP3410 allows the MCLK frequency to be
plesiochronous (i.e. free-running) with respect to the net­work clocks, (BCLK and the 8 kHz FSa input). With a toler­ance on the MCLK oscillator of 15.36 MHz

g

100 ppm, the
lock-in range of DPLL2 allows the network clock frequency
to deviate up to

g

50 ppm from nominal.

In NT applications, when the device is in NT mode and is
slaved to loop timing recovered from the received line sig­nal, DSI or GCI Master mode should normally be selected.
In this case BCLK, FS and SCLK (15.36 MHz) signals are
outputs which are phase-locked to the recovered clock. A
slave-slave mode is also provided, however, in which the
Digital Interface data buffers on the TP3410 allow BCLK
and FSa/b to be input from an external source, which must
be frequency-locked (but may take an arbitrary phase) to
the received line signal; in this case DSI or GCI Slave mode
should be selected.

5.2 Data Buffers

The TP3410 buffers the 2B

a

D data at the Digital Interface
in elastic FIFOs, which are 3 frames deep in each direction.
When the Digital Interface is a timing slave these FIFOs
compensate for relative jitter and wander between the Digi­tal Interface clocks (BCLK and FSa/b) and bit and frame
timing at the Line Interface. Each buffer can absorb wander
up to 18 msin

t

10 secs without ‘‘slip’’, exceeding CCITT
recommendation Q.502. Excessive wander causes a con­trolled slip of one complete frame.

6.0 DIGITAL INTERFACE DATA FORMATS IN
MICROWIRE MODE (MW

e

1)

When the MW pin is tied high to enable the Microwire Port
for control and status, the Digital System Interface on the
TP3410 provides a choice of four multiplexed formats for
the B and D channel data, as shown in

Figure 3

. These
apply in both LT and NT modes of the device, and selection
is made via Register CR1. Selection of DSI Master or Slave
mode must also be made in CR1. Within each format there
is also an independent selection available to either multiplex
the D channel (Tx and Rx) data on the same pins as the B
channels, or via the separate D-channel access pins, DCLK,
Dx and Dr, see Section 6.3.

Format 1: In Format 1, the 2B

a

D data transfer is assigned
to the first 18 bits of the frame on the Bx and Br
pins. Channels are assigned as follows: B1 (8
bits), B2 (8 bits), D (2 bits), with the remaining
bits ignored until the next frame sync pulse.
When the D channel port is enabled (see CR2),
only the 2 B channels use the Bx and Br pins; the
D bits are assigned to the 17th and 18th bits of
the frame on the Dx and Dr pins.

Figure 3-1

shows this format in DSI Slave Mode, and

Figure

3-4

shows DSI Master Mode.

8

Functional Description (Continued)

Format 2: Format 2 is the IDL, in which the 2B

a

D data
transfer is assigned to the first 19 bits of the
frame on the Bx and Br pins. Channels are as­signed as follows: B1 (8 bits), D (1 bit), 1 bit ig­nored, B2 (8 bits), D (1 bit), with the remaining
bits ignored until the next frame sync pulse.

Fig-

ure 3-2

shows this format in DSI Slave Mode, and

Figure 3-5

shows DSI Master Mode.

Format 3: This format provides time-slot assignment capa-

bility for the B1 and B2 channels, which can be
independently assigned to any 8-bit wide time­slot from 64 (or less) on the Bx and Br pins; the
Transmit and Receive directions are also inde­pendently assignable. Also the D channel can be
assigned to any 2-bit wide time-slot from 256 (or
less) on the Bx and Br pins (D port disabled) or

on the Dx and Dr pins (see D-Channel Port sec­tion).

Figure 3-3

shows this format in DSI Slave

Mode, and

Figure 3-6

shows DSI Master Mode;

see also Section 6.2.

Format 4: This is similar to the GCI format for the 2B

a

D
channels, but excludes the Monitor channel and
C/I channel. Channels are assigned to the first
26 bits of each frame as follows: B1 (8 bits), B2
(8 bits), ignored (8 bits), D (2 bits). The remaining
bits in the frame are ignored until the next frame
sync pulse. The relationship between BCLK and
data is the same as in the GCI mode for GCI
Channel 0, see

Figure 7

(in DSI Master Mode,

BCLK

e

512 kHz and FSais a square wave out-

put).

TL/H/9151– 5

FSa defines B1 channel for Tx.
FSb defines B1 channel for Rx.

FIGURE 3-1. DSI Format 1: Slave Mode

TL/H/9151– 6

Delayed timing mode must be selected;
Time-slot immediate mode only (no TSA).

FIGURE 3-2. DSI Format 2 (IDL): Slave Mode

9

Functional Description (Continued)

TL/H/9151– 7

Transmit slots are numbered relative to FSa, and receive slots relative to FSb.
Shown with examples of offset frames and Time-slot Assignments.

FIGURE 3-3. DSI Format 3 (Time-Slot Assignment) : Slave Mode

TL/H/9151– 8

FSa defines B1 channel for Tx and Rx.
FSb defines B2 channel for Tx and Rx.

FIGURE 3-4. DSI Format 1: Master Mode

TL/H/9151– 9

FIGURE 3-5. DSI Format 2 (IDL): Master Mode

TL/H/9151– 10

Transmit and Receive slots are numbered relative to FSa.

FIGURE 3-6. DSI Format 3: Master Mode

10