National Semiconductor TP3094 Technical data

TP3094 COMBO®

TP3094 Quad PCM Codec/Filter

PDN3

AVCC1

VRO3

GXO3

VXI3

PDN2

PDN1

PDN0

A/µLaw

MCLK

GXO0

VRO0

AVCC0

PT1

PCMMode

TS

X

PT2

TST

FSR0

FSX0

DR

PT3

Quad PCM Codec/Filter

February 2000

General Description

The TP3094 is a monolithic PCM Codec and Fil­ter device implemented using a digital signal pro­cessing architecture. It provides four voice
channels, combining transmit bandpass and re­ceive low pass channel filters with companding A­law or m-law PCM encoders and decoders. The
device is fabricated using National’s advanced
CMOS process.

The device includes anti-aliasing filters and sig­ma-delta converters dedicated to each channel,
and by a common signal processing unit which
performs all the remaining filtering and process­ing for the four channels.

The TP3094 includes a flexible PCM digital inter­face, which allows the device to be connected to
PCM busses of different formats. It can also be
connected with other TP3094 devices in a cas­cade fashion, for a system with up to 128 POTS
interfaces (when a 2.048MHz PCM bus is used).

Features

•Handles four voice channels

•Complete Codec and Filter system including:

- Transmit and receive channel filters

- A-law or

•Power down mode for low power consumption

•Compatible to standard time division multi­plexed PCM bus

- 8 bit mode, frame signal from external reference

- 32 bit mode, internal TSA, with consecutive TS

•Up to 128 channels (32 devices) can be cas­caded

•Programmable functions (common for all 4
channels):

- A-law or µ-law

- Single MCLK clock,automatically selectable from

8.192MHz, 4.096MHz, 2.048MHz and

1.536/1.544MHz

- Digital and Analog loopback test modes

•Designed for CCITT and LSSGR applications

•Single +5V power supply

•44 lead PLCC surface mount package

•Maximize line card circuit density

•Use in Central Office, Loop Carrier, and PBX
equipment subscriber line and trunk cards

•Wide operating temperature range

85°C

µ-law companding encoder/decoder

-40°C to

Connection Diagram

6 5 4 3 2 1 44 43 42 41 40

NF

7
8

9
10
11
12
13
14
15
16
17

TP3094

18 19 20 21 22 23 24 25 26 27 28

Order Number TP3094V
See NS Package V44A

AGND1

VXI2
GXO2
VRO2

VRO1
GXO1

VXI1

AGND0

VXI0

NC

COMBO® and TRI-STATE® are registered trademarks of National Semiconductor Corporation

© 2000 National Semiconductor Corporation

39

DX
DGND

38
37

PT4

36

DVCC

35

FSX3

34

NC

33

FSR3

32

FSX2

31

FSR2

30

FSX1

29

FSR1

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Simplified Block Diagram

AVCC0

AGND0

AVCC1

AGND1

DVCC

DGND

NF

PT1

PT2

PT3

PT4

GXO0

VXI0-

VRO0

GXO1

VXI1-

VRO1

GXO2

VXI2-

VRO2

GXO3

VXI3-

VRO3

-

+

­+

-

+

-

+

ADC
DAC

ADC
DAC

ADC
DAC

ADC
DAC

Digital
Signal
Processor

Clock

Interface

PLL

Detection

PCM

Ref & Bias

MCLK

DX
DR

FSX0-3
FSR0-3

TSx
PCMMode

TST

A/u Law
PDN0-3

FIGURE 1. Simplified block diagram

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Pin Descriptions

MCLK (input)

Master and PCM bit clock input. Must be either

1.536MHz/1.544MHz, 2.048MHz, 4.096MHz or

8.192MHz. Its value is automatically detected in­ternally on power up with the valid frame sync in­put.

AVCC0, AVCC1

Positive supply pins for the analog circuitry.
AVCC0 is for channel 0 and channel 1. AVCC1
is for channel 2 and channel 3.
AVCC0=AVCC1=+5V ±5%. These two pins
should be connected together outside the device.

AGND0, AGND1

Analog ground. All analog signals are referenced
to AGND0 and AGND1. AGND0 is the analog
ground for channel 0 and channel 1. AGND1 is
the analog ground for channel 2 and channel 3.
These two pins should be connected together
outside the device.

DVCC

Positive supply for the digital circuitry.
DVCC=+5V ±5%.

DGND

Digital ground. All logic signals are referenced to
DGND. This ground has to be connected to the
ground of other digital devices at board level.

signed transmit time-slots (for all four channels).
DR (input)

Receive PCM data input. Serial PCM data is
shifted into the device on the falling edge of
MCLK during the assigned receive time-slot.

FSX0, FSR0 (inputs)
Transmit and Receive Frame synchronization in-

Analog ports

VXI0-, VXI1-, VXI2-, VXI3- (inputs)
Inverting analog inputs of the transmit input am­plifiers of channels 0-3. They are referenced to an
internal reference voltage of about 2.4V.

GXO0, GXO1, GXO2, GXO3 (outputs)
Outputs of the transmit input amplifiers of chan­nels 0-3. They are referenced to an internal refer­ence voltage of about 2.4V

VRO0, VRO1, VRO2, VRO3 (ouputs)
Analog outputs of the receive amplifiers for chan­nels 0-3. They are referenced to an internal refer­ence voltage of about 2.4V

PCM Port

DX (ouput)
Transmit PCM data output. Serial PCM data is
shifted out on the rising edge of MCLK during the
assigned transmit time-slot. Tristated when the
assigned transmit time-slot is not active.

(ouput)

TSx

Open drain output that pulses low during the as-

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Pin Descriptions (continued)

expects its individual transmit and receive frame
signal. When it is HIGH, the 32 bit mode is select­ed; in this mode FSX0 and FSR0 are used as
framing signals and the TS are allocated consec­utively from these frames, starting from Ch0 to
Ch3. In this mode FSX1 and FSR1 become out­puts and produce 1 bit long frame signals with the
last bit of the 32 bit stream. These Frame signals
can be used to cascade another device in 32 bit
mode.

NF

Noise Filter Pin. For optimal noise rejection a
100nF capacitor must be connected between this
pin and the analog ground AGND0.

PT1, PT2, PT3, PT4 (inputs)
These pins are used by National for internal man­ufacturing test. They must be connected to digital
ground for normal device operation.

NC

All NC pins must be connected to nearest analog
ground, to reduce the device noise sensitivity.

Power Initialization

When power is first applied to the device, power­on reset circuitry initializes the device and places
it in the power down state. All non-essential cir­cuits are de-activated. PCM output DX and ana­log outputs VRO
impedance state, while FSX1 and FSR1 outputs
are held low (in case 32-bit mode is selected). In
the power down mode, power consumption is re­duced to a minimum, typically 2mW. The device
will remain in this state as long as no MCLK is ap­plied and no Frame Signal is applied (just FSX0
and FSR0 in case of 32-bit mode).
For each channel, when the PDN input is not ac­tive, MCLK is applied, and a FS (receive or trans­mit) pulse is running, the device enters the active
power up mode. The MCLK frequency is detected
with any available FS signal; the clock rate detec­tion may last for up to 4ms, after which the device
is ready for powering up. Analog and PCM output
signals will be available after a few frames; it will
take about 100ms until the first activated channel
is fully functional.
The device will only power up when at least one
of the FS signals and the MCLK signal are in a
valid frequency ratio.

are placed in the high

0-3

Functional Description

The TP3094 performs the complete CODEC/filter
functions for four voice channels using a digital
signal processing architecture. MCLK provides
the clock reference to the whole circuitry and the
bit clock for the PCM bus. Its value can be either

8.192MHz, 4.096MHz, 2.048MHz or 1.536/

1.544MHz, and it is automatically selected inter­nally. The TP3094 handles the conversion be­tween the analog signals on the subscriber line
and the PCM data samples on a PCM highway.
Digital filters are used to band-limit the voice sig­nals.
The device can work in a 8 bit mode where each
channel has an independently selected Time
Slot, or in the 32 bit mode, where the four chan­nels use four consecutive Time Slots. The time­division multiplexed PCM data is transferred to
the PCM highway through the standard serial
PCM bus.
Each channel has its dedicated Power Down in­put.

Power Down and Reset

When one channel is in Power Down Mode, the
DX output will remain in high impedance state
and the input on the DR will be ignored when its
FS signal is active; the analog output VRO will be
in high impedance.
Each channel will enter the power down mode
when at least one of the following conditions oc­curs

• The PDN signal is active for more than 16
MCLK cycles (and TST is not active at the
same time)

• More than 4 pulses of the respective FS are
missing.

• MCLK is missing for a 12us.

When the PDN input is active (HIGH) for at least
16 MCLK clock cycles, the channel will go into
power down mode and reset its state within a
frame sync. The channel will recover from Power
Down, after having detected the PDN signal inac­tive (LOW) for at least 16 MCLK clock cycles and
after 1 frame sync pulse.
This power down mode will work only in presence
of the master clock at the pin MCLK.

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When both the transmit and receive frame sync of
a channel are missing the channel will go into
Power Down Mode (if only one of them is missing
the channel will not go into Power Down). A max­imum of 32 frame sync pulses must be missing
for power down and the channel will achieve its
reset state after 32.5us. The channel will recover
from power down, within the time of 4ms after the
frame syncs (transmit or receive) will be active.
When the device is in 32-bit mode, missing FSX0,
FSR0 for 512us, will force all channels in power
down mode.

When the master clock MCLK is missing, all the
channels will go into the Global Power Down
Mode, with the lowest possible power consump­tion. The device will recover from this mode,
when the clock signal comes back (and at least
one frame sync is present), and then the active
channels will operate after less than 100ms.
The device will go into the same Global Power
Down Mode when all the frame syncs (of all the
channels, in case of 8bit mode, the FSX0, FSR0
in case of 32-bit mode) are not present or when
all 4 PDN signals are active. The recovery time
from this mode for the first active channel is less
than 100ms.

processing functions, such as PCM expansion
according to the ALaw or uLaw and signal filter­ing. Then, for each channel it drives the Digital to
Analog converter, through the proper interpola­tion stages and filters. Finally the signal is filtered
and buffered to the output receive pin. The maxi­mum output level voltage on the VRO pins on a
load of 5kOhm+100pF is 1.12Vrms.

PCM Interface

The PCM interface consists of the following sig­nals

• DX, DR - transmit and receive digital signals,
carrying the pcm samples

• FSX0-3, FSR0-3 - transmit and receive frame
signals

- output time slots signal, indicating the

• TSX
time slot occupied on the DX by the device

• PCMMode - PCM interface select

PCMMode = HIGH PCMMode = LOW

32 bit 8 bit

• A/uLaw - A-law/ u-law select signal

•

TABLE 1. A/uLaw Coding

A/uLaw = HIGH A/uLaw = LOW

A-law u-law

Transmit Section

The transmit section input is an operational ampli­fier, with provision for gain adjustment using two
external resistors. Only the inverting input is pro­vided (together with the output), this allows, be­side the adjustment of the gain, to implement the
echo balance function with external passive com­ponents.
The opamp drives the antialiasing input filter, fol­lowed by the A to D converter, which provides the
digital input to the signal processing unit.
The signal processing unit accepts the signal
samples from each channel input stage, performs
the necessary decimation and filtering function,
PCM compression and provides the eight bit
samples to the PCM interface block.
The analog input is dc biased at the value of 2.4V.
A DC decoupling is necessary between this input
and the SLIC output. The maximum analog signal
level, at the op-amp output, is 1.12Vrms.
Maximum recommended transmit gain is 20dB
(10x).

Receive Section

This section takes the 8 bit samples from the
PCM interface block and performs all the signal

• MCLK - bit clock signal

MCLK is both the system master clock and the
PCM bus bit clock, and it is selected internally to
be either 8.192MHz, 4.096MHz, 2.048MHz, or

1.536/ 1.544MHz.

The internal clock selection is perfomed, based
on the relative ratio between the frame signals
(FS) and the clock signals. For proper functional­ity all the channel FS must have the same valid
rate of 8kHz (giving a valid clock rate). In case
one of the frame syncs runs other than 8kHz, the
device will not function properly.
Each bit on DX is clocked out on the rising edges
of the bit clock (MCLK), starting from the Most
Significant Bit (Sign bit). Each bit on DR is
clocked in on the falling edges of the bit clock,
starting from the MSB.
The device may operate on to the PCM bus in two
modes, selected by the input pin PCMMode;
when PCMMode is “0V” the 8bit mode is selected
and when PCMMode is “+5V” the 32-bit mode is
selected.

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Functional Description (continued)

8-bit Mode

In the 8-bit mode, PCM data is transferred inde­pendently for each of the four channels. Each
channel has its dedicated transmit and receive
frame signals, which determine the time-slots to
be taken on the PCM bus. Both short sync and
long sync frame are supported.
All the channels must have the same FS format
(either short or long sync), in case a channel will
have a valid frame with different FS format, the
device will not function properly.
In the short sync, the frame signals must be one
bit long; with FSX high during a falling edge of
MCLK, the next rising edge of MCLK enables the
DX tristate output buffer, which will output the
sign bit. The following 7 rising edges clock out the
remaining 7 bits, and the next rising edge (9th)
disables the DX output. With FSR high during a
falling edge of MCLK, the next falling edge of
MCLK latches in the sign bit. The following 7 neg­ative edges of MCLK will then latch the remaining
7 bit of the incoming byte.
In the long sync frame, the Frame signals must be
at least three bits long. The DX output buffer is
enabled with the rising edge of FSX or on the ris­ing edge of MCLK, whichever comes later, and
the first bit (sign) is clocked out. The following 7
rising edges of MLCK clock out the remaining 7
bits. The DX output is disabled by the 9th rising
edge of MCLK. A rising edge on FSR will cause
the PCM data at DR to be latched in on the next
falling edges of MCLK.
For timing diagrams refer to Fig.2, Fig.4, Fig.5
and Fig.6.

32-bit Mode

In the 32-bit mode, the four PCM data bytes of the
four channels are treated as a single 32-bit data
word. The PCM transfer is started by the positive
pulses on the transmit or receive frame sync
(FSX0, FSR0) inputs. The following 32 negative
edges of MCLK will then latch the input PCM data
at DR, for all 4 channel starting from channel 0;
while the positive edges will clock out the transmit
PCM data at DX, from channel 0 to channel 3. In
this mode the pins FSX1 and FSR1 become the
frame signal carry-out signals, providing a single­bit-long frame pulse during the last bit of the 32­bit stream and allowing another TP3094 to be
connected in 32-bit mode.
In case any channel is powered down (through
the PDN pin) during its assigned time slot the DX
pin will be set in tristate and the DR signal will be

ignored.
In case all the channels are placed in power
down, the device will still generate the FS carry
output on FSX1, FSR1. For timing diagrams refer
to Fig.7 and Fig.8.

Test Modes

The TP3094 includes the following test modes

• digital loopback

• analog loopback

• DC conversion
These modes can be programmed per channel or
for all 4 channels simultaneously.
The device is programmed into any test mode by
exercising the pins TST, PDN0, PDN1, PDN2,
PDN3 together. The signals to this pins must be
stable for at least 16 MCLK cycles before the de­vice enters any selected test mode. When exiting
the test mode, the PDN must return to the previ­ous state to resume the original operating state.
During any test mode (TST=1), it will not be pos­sible to change the PU/PD state for any channel
not involved in the test mode configuration (e.g.
not in test mode). The channel(s) under test must
be placed in power up prior the test mode selec­tion, in case left in power down, any programmed
test mode will not be operational.
When the device exits the test mode, normal op­eration will return, and the PU/PD programmabil­ity will be available, by the state of the PDN
signals.

The programming of the test modes is according
to the table below.
The digital loopback is a bit true feedback from
the PCM highway to the PCM highway, per­formed exactly at the PCM internal interface.
Each byte is looped back from RX to TX on the
programmed time slot (FS). The analog output is
forced to 0Vac level (typically 2.4Vdc), with low
output impedance.

The analog loopback is performed from the out­put of the D/A converter (before the output ampli­fier) and the input of the A/D, so the RX signal is
looped back towards the TX direction, through the
device. The analog output is at 0Vac level, with
high output impedance.

In the DC conversion mode, the channel under
test is programmed to transfer any DC signal
(within the available range) in the TX direction,
from the analog GXO to the DX digital output, by

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