NATIONAL SEMICONDUCTOR TP3076N-G Datasheet

TP3076 COMBO

II Programmable PCM CODEC/Filter for ISDN

and Digital Phone Applications

General Description

The TP3076 is a second-generation combined PCM CODEC and Filter devices optimized for digital switching applications on subscriber line and trunk cards and digital phone applications. Using advanced switched capacitor techniques, COMBO II combines transmit bandpass and receive lowpass channel filters with a companding PCM encoder and decoder. The devices are A-law and µ-law selectable and employ a conventional serial PCM interface capable of being clocked up to 4.096 MHz. A number of programmable functions may be controlled via a serial control port.

Channel gains are programmable over a 25.4 dB range in each direction.

To enable COMBO II to interface to the SLIC control leads, a number of programmable latches are included; each may be configured as either an input or an output. The TP3076 provides 4 latches.

Features

n Complete CODEC and Filter system including:

— Transmit and receive PCM channel filters — µ-law or A-law companding coder and decoder — Receive power amplifier drives 300Ω — 4.096 MHz serial PCM data (max)

n Programmable functions:

— Transmit gain: 25.4 dB range, 0.1 dB steps — Receive gain: 25.4 dB range, 0.1 dB steps — Time-slot assignment; to 64 slots/frame — 4 interface latches — A or µ-law — Analog loopback — Digital loopback

n Direct interface to solid-state SLICs n Standard serial control interface n 80 mW operating power (typ) n 1.5 mW standby power (typ) n Designed for CCITT and LSSGR specifications n TTL and CMOS compatible digital interfaces

Note: See also AN-614 COMBO II application guide.

Block Diagram

TRI-STATE®and COMBO®are registered trademarks of National Semiconductor Corporation. MICROWIRE/PLUS

™

is a trademark of National Semiconductor Corporation.

DS009758-1

FIGURE 1.

April 1994

TP3076 COMBO II Programmable PCM CODEC/Filter for ISDN and Digital Phone Applications

Connection Diagram

Pin Descriptions

Pin Description

+5V±5%power supply.

−5V±5%power supply.

GND Ground. All analog and digital signals are

referenced to this pin.

Transmit Frame Sync input. Normally a pulse or squarewave with an 8 kHz repetition rate is applied to this input to define the start of the transmit time slot assigned to this device (non-delayed data timing mode), or the start of the transmit frame (delayed data timing mode using the internal time-slot assignment counter).

Receive Frame Sync input. Normally a pulse or squarewave with an 8 kHz repetition rate is applied to this input to define the start of the receive time slot assigned to this device (non-delayed data timing mode), or the start of the receive frame (delayed data timing mode using the internal time-slot assignment counter).

BCLK Bit clock input used to shift PCM data into and

out of the D

and DXpins. BCLK may vary from 64 kHz to 4.096 MHz in 8 kHz increments, and must be synchronous with MCLK.

MCLK Master clock input used by the switched

capacitor filters and the encoder and decoder sequencing logic. Must be 512 kHz,

1.536/1.544 MHz, 2.048 MHz or 4.096 MHz and synchronous with BCLK.

I The Transmit analog high-impedance input.

Voice frequency signals present on this input are encoded as an A-law or µ-law PCM bit stream and shifted out on the selected D

pin.

O The Receive analog power amplifier output,

capable of driving load impedances as low as 300Ω (depending on the peak overload level required). PCM data received on the assigned D

pin is decoded and appears at this output

as voice frequency signals.

Pin Description

1 This transmit data TRI-STATE®output

remains in the high impedance state except during the assigned transmit time slot on the assigned port, during which the transmit PCM data byte is shifted out on the rising edges of BCLK.

1 Normally this open drain output is floating in a

high impedance state except when a time-slot is active on the D

output, when the TSX1 output pulls low to enable a backplane line-driver.

1 This receive data input is inactive except

during the assigned receive time slot of the assigned port when the receive PCM data is shifted in on the falling edges of BCLK.

CCLK Control Clock input. This clock shifts serial

control information into CI or out from CO when the CS input is low, depending on the current instruction. CCLK may be asynchronous with the other system clocks.

CI Control Data Input pin. Serial control

information is shifted into COMBO II on this pin when CS is low. Byte 1 of control information is always written into COMBO II, while the direction of byte 2 data is determined by bit 2 of byte 1, as defined in

Table 1

CO Control Data Output pin. Serial control or

status information is shifted out of COMBO II on this pin when CS is low.

CS Chip Select input. When this pin is low, control

information can be written to or read from COMBO II via CI or CO.

IL3–IL0 Each Interface Latch I/O pin may be

individually programmed as an input or an output determined by the state of the corresponding bit in the Latch Direction Register (LDR). For pins configured as inputs, the logic state sensed on each input is latched into the Interface Latch Register (ILR) whenever control data is written to COMBO II, while CS is low, and the information is shifted out on the CO pin. When configured as outputs, control data written into the ILR appears at the corresponding IL pins.

Functional Description

POWER-ON INITIALIZATION

When power is first applied, power-on reset circuitry initializes the COMBO II and puts it into the power-down state. The gain control registers for the transmit and receive gain sections are programmed for no output, the power amp is disabled and the device is in the non-delayed timing mode. The Latch Direction Register (LDR) is pre-set with all IL pins programmed as inputs, placing the SLIC interface pins in a high impedance state. The CO pin is in TRI-STATE condition. Other initial states in the Control Register are indicated in Section 2.0.

DS009758-4

Order Number TP3076J

See NS Package Number J20A

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Functional Description (Continued)

The desired modes for all programmable functions may be initialized via the control port prior to a Power-up command.

POWER-DOWN STATE

Following a period of activity in the powered-up state the power-down state may be re-entered by writing any of the control instructions into the serial control port with the “P” bit set to “1” as indicated in

Table1

. It is recommended that the chip be powered down before writing any additional instructions. In the power-down state, all non-essential circuitry is de-activated and the D

1 output is in the high impedance

TRI-STATE condition. The data stored in the Gain Control registers, the LDR and

ILR, and all control bits remain unchanged in the power-down state unless changed by writing new data via the serial control port, which remains active. The outputs of the Interface Latches also remain active, maintaining the ability to monitor and control the SLIC.

TRANSMIT FILTER AND ENCODER

The Transmit section input, VF

I, is a high impedance input. No external components are necessary to set the gain. Following this is a programmable gain/attenuation amplifier which is controlled by the contents of the Transmit Gain Register (see Programmable Functions section). An active pre-filter then precedes the 3rd order high-pass and 5th or-

der low-pass switched capacitor filters. The A/D converter has a compressing characteristic according to the standard CCITT A or µ255 coding laws, which must be selected by a control instruction during initialization (see

Table1

and

Table

). A precision on-chip voltage reference ensures accurate and highly stable transmission levels. Any offset voltage arising in the gain-set amplifier, the filters or the comparator is canceled by an internal auto-zero circuit.

Each encode cycle begins immediately following the assigned Transmit time-slot. The total signal delay referenced to the start of the time-slot is approximately 165 µs (due to the Transmit Filter) plus 125 µs (due to encoding delay), which totals 290 µs. Data is shifted out on D

1 during the se-

lected time slot on eight rising edges of BCLK.

DECODER AND RECEIVER FILTER

PCM data is shifted into the Decoder’s Receive PCM Register via the D

1 pin during the selected time-slot on the 8 falling edges of BCLK. The Decoder consists of an expanding DAC with either A or µ255 law decoding characteristic, which is selected by the same control instruction used to select the Encode law during initialization. Following the Decoder is a 5th order low-pass switched capacitor filter with integral Sin x/x correction for the 8 kHz sample and hold. A programmable gain amplifier, which must be set by writing to the Receive Gain Register, is included, and finally a Power Amplifier capable of driving a 300Ω load to

3.5V,a 600Ω load to

3.8V or a 15 kΩ load to±4.0V at peak overload.

TABLE 1. Programmable Register Instructions

Function Byte 1 (Notes 1, 2, 3) Byte 2 (Note 1)

7654321076543210

Single Byte Power-Up/Down PXXXXX0X None Write Control Register P 000001X See

Table 2

Read-Back Control Register P 000011X See

Table 2

Write to Interface Latch Register P 000101X See

Table 4

Read Interface Latch Register P 000111X See

Table 4

Write Latch Direction Register P 001001X See

Table 3

Read Latch Direction Register P 001011X See

Table 3

Write Receive Gain Register P 010001X See

Table 8

Read Receive Gain Register P 010011X See

Table 8

Write Transmit Gain Register P 010101X See

Table 7

Read Transmit Gain Register P 010111X See

Table 7

Write Receive Time-Slot/Port P 100101X See

Table 6

Read-Back Receive Time-Slot/Port P 100111X See

Table 6

Write Transmit Time-Slot/Port P 101001X See

Table 6

Read-Back Transmit Time-Slot/Port P 101011X See

Table 6

Note 1: Bit 7 of bytes 1 and 2 is always the first bit clocked into or out from the CI or CO pin. X=don’t care. Note 2: “P” is the power-up/down control bit, see Power-up/Down Control section. (“0”=Power Up, “1”=Power Down) Note 3: Other register address codes are invalid and should not be used.

A decode cycle begins immediately after the assigned receive timeslot, and 10 µs later the Decoder DAC output is updated. The total signal delay is 10 µs plus 120 µs (filter delay) plus 62.5 µs (

⁄2frame) which gives approximately 190

µs.

PCM INTERFACE

The FS

and FSRframe sync inputs determine the beginning of the 8-bit transmit and receive time-slots respectively. They may have any duration from a single cycle of BCLK HIGH to one MCLK period LOW. Two different relationships may be established between the frame sync inputs and the actual time-slots on the PCM busses by setting bit 3 in the Control Register (see

Table 2

). Non-delayed data mode is

similar to long-frame timing on the TP3050/60 series of de-

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Functional Description (Continued)

vices (COMBO); time-slots begin nominally coincident with the rising edge of the appropriate FS input. The alternative is to use Delayed Data mode, which is similar to shortframe sync timing on COMBO, in which each FS input must be high at least a half-cycle of BCLK earlier than the timeslot. The Time-SlotAssignment circuit on the device can only be used with Delayed Data timing.

When using Time-Slot Assignment, the beginning of the first time-slot in a frame is identified by the appropriate FS input. The actual transmit and receive time-slots are then determined by the internal Time-Slot Assignment counters.

Transmit and Receive frames and time-slots may be skewed from each other by any number of BCLK cycles. During each assigned Transmit time-slot, the D

1 output shifts data out

from the PCM register on the rising edges of BCLK. TS

1 also pulls low for the first 71⁄2bit times of the time-slot to control the TRI-STATE Enable of a backplane line-driver. Serial PCM data is shifted into the D

1 input during each assigned

Receive time-slot on the falling edges of BCLK.

SERIAL CONTROL PORT

Control information and data are written into or read-back from COMBO II via the serial control port consisting of the control clock CCLK, the serial data input, CI, and output, CO, and the Chip Select input, CS. All control instructions require 2 bytes, as listed

Table1

, with the exception of a single byte power-up/down command. The Byte 1 bits are used as follows: bit 7 specifies power up or power down; bits 6, 5, 4 and 3 specify the register address, bit 2 specifies whether the instruction is read or write; bit 1 specifies a one or two byte instruction; and bit 0 is not used.

To shift control data into COMBO II, CCLK must be pulsed high 8 times while CS is low. Data on the CI input is shifted into the serial input register on the falling edge of each CCLK pulse. After all data is shifted in, the contents of the input shift register are decoded, and may indicate that a 2nd byte of control data will follow.This second byte may either be defined by a second byte-wide CS pulse or may follow the first contiguously,i.e, it is not mandatory for CS to return high between the first and second control bytes. At the end of CCLK8 in the 2nd control byte the data is loaded into the appropriate programmable register. CS may remain low continuously when programming successive registers, if desired. However, CS must be set high when no data transfers are in progress.

To readback Interface Latch data or status information from COMBO II, the first byte of the appropriate instruction is strobed while CS is low, as defined in

Table 1

. CS must be kept low, or be taken low again for a further 8 CCLK cycles, during which the data is shifted onto the CO pin on the rising edges of CCLK. When CS is high the CO pin is in the high-impedance TRI-STATE, enabling the CI and CO pins of many devices to be multiplexed together.

If CS returns high during either byte 1 or byte 2 before all eight CCLK pulses of that byte occur, both the bit count and byte count are reset and register contents are not affected. This prevents loss of synchronization in the control interface as well as corruption of register data due to processor interrupt or other problem. When CS returns low again, the device will be ready to accept bit 1 of byte 1 of a new instruction.

Programmable Functions

POWER-UP/DOWN CONTROL

Following power-on initialization, power-up and power-down control may be accomplished by writing any of the control instructions listed in

Table1

into COMBO II with the “P” bit set to “0” for power-up or “1” for power-down. Normally it is recommended that all programmable functions be initially programmed while the device is powered down. Power state control can then be included with the last programming instruction or the separate single-byte instruction. Any of the programmable registers may also be modified while the device is powered-up or down by setting the “P” bit as indicated. When the power-up or down control is entered as a single byte instruction, bit one (1) must be reset to a 0.

When a power-up command is given, all de-activated circuits are activated, but the TRI-STATEPCM output(s), D

1 will re-

main in the high impedance state until the second FS

pulse

after power-up.

CONTROL REGISTER INSTRUCTION

The first byte of a READ or WRITE instruction to the Control Register is as shown in

Table1

. The second byte has the fol-

lowing bit functions:

TABLE 2. Control Register Byte 2 Functions

Bit Number and Name

76543210 Function

1F0

MA IA DN DL AL PP

0 0 MCLK=512 kHz 0 1 MCLK=1.536 MHz

or 1.544 MHz 1 0 MCLK=2.048 MHz (Note 4) 1 1 MCLK=4.096 MHz

0 X Select µ255 Law (Note 4) 1 0 A-Law, Including

Even Bit

Inversion

1 1 A-Law, No Even Bit

Inversion

0 Delay Data Timing 1 Non-Delayed

Data Timing (Note 4)

0 0 Normal Operation (Note 4) 1 X Digital Loopback 0 1 Analog Loopback

0 Power Amp

Enabled in PDN

1 Power Amp

Disabled in PDN (Note 4)

Note 4: state at power-on initialization.

Master Clock Frequency Selection

A Master clock must be provided to COMBO II for operation of the filter and coding/decoding functions. The MCLK frequency must be either 512 kHz, 1.536 MHz, 1.544 MHz,

2.048 MHz, or 4.096 MHz and must be synchronous with BCLK. Bits F

and F0(see

Table2

) must be set during initial-

ization to select the correct internal divider.

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Programmable Functions (Continued)

Coding Law Selection

Bits “MA” and “IA” in

Table 2

permit the selection of µ255

coding or A-law coding, with or without even bit inversion.

Analog Loopback

Analog Loopback mode is entered by setting the “AL” and “DL” bits in the Control Register as shown in

Table 2

.Inthe

analog loopback mode, the Transmit input VF

I is isolated

from the input pin and internally connected to the VF

O output, forming a loop from the Receive PCM Register back to the Transmit PCM Register. The VF

O pin remains active, and the programmed settings of the Transmit and Receive gains remain unchanged, thus care must be taken to ensure that overload levels are not exceeded anywhere in the loop.

Digital Loopback

Digital Loopback mode is entered by setting the “AL” and “DL” bits in the Control Register as shown in

Table 2

. This mode provides another stage of path verification by enabling data written into the Receive PCM Register to be read back from that register in any Transmit time-slot at D

1. PCM de-

coding continues and analog output appears at VF

0. The output can be disabled by programming ‘No Output’ in the Receive Gain Register (see

Table 8

INTERFACE LATCH DIRECTIONS

Immediately following power-on, all Interface Latches assume they are inputs, and therefore all IL pins are in a high impedance state. Each IL pin may be individually programmed as a logic input or output by writing the appropriate instruction to the LDR, see

Table 1

and

Table 3

. For minimum power dissipation, unconnected latch pins should be programmed as outputs. For the TP3076, bits 2 and 3 should always be programmed as “1” (outputs).

Bits L

3–L0

must be set by writing the specific instruction to

the LDR with the L bits in the second byte set as follows:

TABLE 3. Byte 2 Functions of Latch Direction Register

Byte 2 Bit Number

76543210

L1L2L311XX

Bit IL Direction 0 Input 1 Output

X=Don’t Care

INTERFACE LATCH STATES

Interface Latches configured as outputs assume the state determined by the appropriate data bit in the 2-byte instruction written to the Interface Latch Register (ILR) as shown in

Table1

and

Table4

. Latches configured as inputs will sense the state applied by an external source, such as the Off-Hook detect output of a SLIC. All bits of the ILR, i.e. sensed inputs and the programmed state of outputs, can be read back in the 2nd byte of a READ from the ILR.

It is recommended that during initialization, the state of IL pins to be configured as outputs should be programmed first followed immediately by the Latch Direction Register.

TABLE 4. Interface Latch Data Bit Order

Bit Number

76543210

D1D2D3D4D5XX

TABLE 5. Coding Law Conventions

µ255 Law True A-Law with A-Law without

Even Bit Inversion Even Bit Inversion

MSB LSB MSB LSB MSB LSB

+Full Scale 10000000 10101010 111111111

0V 11111111 11010101 100000000

11111111 01010101 000000000

−Full Scale 00000000 00101010 011111111

Note 5: The MSB is always the first PCM bit shifted in or out of COMBO II.

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Programmable Functions (Continued)

TABLE 6. Time-Slot and Port Assignment Instruction

Bit Number and Name Function

7 6 5 43210

EN PS T

(Note 6) (Note 7)

0 1 X XXXXXDisable D

1 Output (Transmit Instruction)

Disable D

1 Input (Receive Instruction)

1 1 Assign One Binary Coded Time-Slot from 0–63 Enable D

1 Output (Transmit Instruction)

Assign One Binary Coded Time-Slot from 0–63 Enable D

1 Input (Transmit Instruction)

Note 6: The “PS” bit MUST be set to “1” for both transmit and receive for the TP3076. Note 7: T5 is the MSB of the time-slot assignment bit field. Time-slot bits should be set to “000000” for both transmit and receive when operating in non-delayed data

timing mode.

TIME-SLOT ASSIGNMENT

COMBO II can operate in either fixed time-slot or time-slot assignment mode for selecting the Transmit and Receive PCM time-slots. Following power-on, the device is automatically in Non-Delayed Timing mode, in which the time-slot always begins with the leading (rising) edge of frame sync inputs FS

and FSR. Time-Slot Assignment may only be used

with Delay Data timing; see

Figure 4

.FSXand FSRmay have any phase relationship with each other in BCLK period increments.

Alternatively, the internal time-slot assignment counters and comparators can be used to access any time-slot in a frame, using the frame sync inputs as marker pulses for the beginning of transmit and receive time-slot 0. In this mode, a frame may consist of up to 64 time-slots of 8 bits each. A time-slot is assigned by a 2-byte instruction as shown in

Table 1

and

Table 6

. The last 6 bits of the second byte indicate the selected time-slot from 0–63 using straight binary notation. When writing a time-slot and port assignment register,if the PCM interface is currently active, it is immediately deactivated to prevent possible bus clashes. A new assignment becomes active on the second frame following the end of the Chip-Select for the second control byte. Rewriting of the register contents should not be performed during the talking period of a connection to prevent waveform distortion caused by loss of a sample which will occur with each register write. The “EN” bit allows the PCM input, D

1, or output,

1, as appropriate, to be enabled or disabled.

Time-Slot Assignment mode requires that the FS

and FS

pulses conform to the delayed data timing format shown in

Figure 4

PORT SELECTION

On the TP3076, the “PS” bit MUST always be set to 1.

Table 6

shows the format for the second byte of both trans-

mit and receive time-slot and port assignment instructions.

TRANSMIT GAIN INSTRUCTION BYTE 2

The transmit gain can be programmed in 0.1 dB steps by writing to the Transmit Gain Register as defined in

Table 1

and

Table7

. This corresponds to a range of 0 dBm0 levels at

I between 1.375 Vrms and 0.074 Vrms (equivalent to

+5.0 dBm to −20.4 dBm in 600Ω). To calculate the binary code for byte 2 of this instruction for

any desired input 0 dBm0 level in Vrms, take the nearest integer to the decimal number given by:

200 x log

(V/0.07299)

and convert to the binary equivalent. Some examples are given in

Table 7

. A complete tabulation is given in Appendix

I of AN-614. It should be noted that the Transmit (idle channel) Noise and

Transmit Signal to Total Distortion are both specified with transmit gain set to 0 dB (gain register set to all ones). At high transmit gains there will be some degradation in noise performance for these parameters. See Application Note AN-614 for more information on this subject.

TABLE 7. Byte 2 of Transmit Gain Instruction

Bit Number 0 dBm0 Test Level (Vrms)

76543210 atVF

00000000 NoOutput (Note 8) 00000001 0.074 00000010 0.075

—— 11111110 1.359 11111111 1.375

Note 8: Analog signal path is cut off, but DXremains active and will output codes representing idle noise.

RECEIVE GAIN INSTRUCTION BYTE 2

The receive gain can be programmed in 0.1 dB steps by writing to the Receive Gain Register as defined in

Table 1

and

Table8

. Note the following restrictions on output drive capa-

bility:

1. 0 dBm0 levels ≤ 1.96 Vrms at VF

O may be driven into a load of ≥ 15 kΩ to GND; Receive Gain set to 0 dB (gain register set to all ones).

2. 0 dBm0 levels ≤ 1.85 Vrms at VF

O may be driven into a load of ≥ 600Ω to GND; Receive Gain set to 0.5 dB.

3. 0 dBm0 levels ≤ 1.71 Vrms at VF

O may be driven into a load of ≥ 300 Ω to GND. Receive Gain set to −1.2 dB.

To calculate the binary code for byte 2 of this instruction for any desired output 0 dBm0 level in Vrms, take the nearest integer to the decimal number given by:

200 x log

(V/0.1043)

and convert to the binary equivalent. Some examples are given in

Table8

.A complete tabulation is given in Appendix I

or AN-614.

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