NATIONAL SEMICONDUCTOR TP3054WM, TP3054N, TP3054N-X Datasheet

TP3054, TP3057
‘‘Enhanced’’ Serial Interface
CODEC/Filter COMBO

Family

É

TP3054, TP3057 ‘‘Enhanced’’ Serial Interface CODEC/Filter COMBO Family

August 1994

General Description

The TP3054, TP3057 family consists of m-law and A-law
monolithic PCM CODEC/filters utilizing the A/D and D/A
conversion architecture shown in
interface. The devices are fabricated using National’s ad­vanced double-poly CMOS process (microCMOS).

The encode portion of each device consists of an input gain
adjust amplifier, an active RC pre-filter which eliminates very
high frequency noise prior to entering a switched-capacitor
band-pass filter that rejects signals below 200 Hz and above
3400 Hz. Also included are auto-zero circuitry and a com­panding coder which samples the filtered signal and en­codes it in the companded m-law or A-law PCM format. The
decode portion of each device consists of an expanding
decoder, which reconstructs the analog signal from the
companded m-law or A-law code, a low-pass filter which
corrects for the sin x/x response of the decoder output and
rejects signals above 3400 Hz followed by a single-ended
power amplifier capable of driving low impedance loads.
The devices require two 1.536 MHz, 1.544 MHz or 2.048
MHz transmit and receive master clocks, which may be
asynchronous; transmit and receive bit clocks, which may
vary from 64 kHz to 2.048 MHz; and transmit and receive
frame sync pulses. The timing of the frame sync pulses and
PCM data is compatible with both industry standard formats.

Figure 1

, and a serial PCM

Connection Diagrams

Dual-In-Line Package

Features

Y

Complete CODEC and filtering system (COMBO)
including:
Ð Transmit high-pass and low-pass filtering
Ð Receive low-pass filter with sin x/x correction
Ð Active RC noise filters
Ð m-law or A-law compatible COder and DECoder
Ð Internal precision voltage reference
Ð Serial I/O interface
Ð Internal auto-zero circuitry

Y

m-law, 16-pinÐTP3054

Y

A-law, 16-pinÐTP3057

Y

Designed for D3/D4 and CCITT applications

Y

g

5V operation

Y

Low operating powerÐtypically 50 mW

Y

Power-down standby modeÐtypically 3 mW

Y

Automatic power-down

Y

TTL or CMOS compatible digital interfaces

Y

Maximizes line interface card circuit density

Y

Dual-In-Line or surface mount packages

Y

See also AN-370, ‘‘Techniques for Designing with
CODEC/Filter COMBO Circuits’’

Plastic Chip Carriers

Top View

Order Number TP3054J or TP3057J

See NS Package Number J16A

Order Number TP3054N or TP3057N

See NS Package Number N16A

Order Number TP3054WM or TP3057WM

See NS Package Number M16B

COMBOÉand TRI-STATEÉare registered trademarks of National Semiconductor Corporation.

C

1995 National Semiconductor Corporation RRD-B30M125/Printed in U. S. A.

TL/H/5510

TL/H/5510– 1

TL/H/5510– 10

Top View

Order Number TP3057V

See NS Package Number V20A

Block Diagram

Pin Description

Symbol Function

V

BB

GNDA Analog ground. All signals are referenced

VF

O Analog output of the receive power ampli-

R

V

CC

FS

R

D

R

BCLKR/CLKSEL The bit clock which shifts data into DRaf-

MCLK

/PDN Receive master clock. Must be

R

Negative power supply pin.

eb

V

BB

5Vg5%.

to this pin.

fier.

Positive power supply pin.

ea

V

CC

5Vg5%.

Receive frame sync pulse which enables
BCLK

to shift PCM data into DR.FSRis

R

an 8 kHz pulse train. See

Figures 2

and

for timing details.

Receive data input. PCM data is shifted
into D

following the FSRleading edge.

R

ter the FS
64 kHz to 2.048 MHz. Alternatively, may

leading edge. May vary from

R

be a logic input which selects either

1.536 MHz/1.544 MHz or 2.048 MHz for
master clock in synchronous mode and
BCLK

is used for both transmit and re-

X

ceive directions (see Table I).

1.536 MHz, 1.544 MHz or 2.048 MHz.
May be asynchronous with MCLK

X

, but

FIGURE 1 TL/H/5510– 2

Symbol Function

should be synchronous with MCLK
formance. When MCLK
ously low, MCLK
ing. When MCLK
high, the device is powered down.

MCLK

FS

3

Transmit master clock. Must be 1.536 MHz,

X

1.544 MHz or 2.048 MHz. May be asynchronous
with MCLK
synchronous operation.

Transmit frame sync pulse input which enables

X

BCLK
an 8 kHz pulse train, see

. Best performance is realized from

R

to shift out the PCM data on DX.FSXis

X

is connected continu-

R

is selected for all internal tim-

X

is connected continuously

R

X

Figures 2

for best per-

and3for

timing details.

BCLK

D

TS

GS

VF

The bit clock which shifts out the PCM data on

X

D

. May vary from 64 kHz to 2.048 MHz, but

X

must be synchronous with MCLK

The TRI-STATEÉPCM data output which is en-

X

abled by FS

Open drain output which pulses low during the

X

encoder time slot.

Analog output of the transmit input amplifier.

X

Used to externally set gain.

IbInverting input of the transmit input amplifier.

X

.

X

.

X

VFXIaNon-inverting input of the transmit input amplifi-

er.

2

Functional Description

POWER-UP

When power is first applied, power-on reset circuitry initializ­es the COMBO and places it into a power-down state. All
non-essential circuits are deactivated and the D
outputs are put in high impedance states. To power-up the
device, a logical low level or clock must be applied to the
MCLK

/PDN pin

R

ent. Thus, 2 power-down control modes are available. The
first is to pull the MCLK
hold both FS
will power-down approximately 1 ms after the last FS
FS

pulse. Power-up will occur on the first FSXor FS

R

pulse. The TRI-STATE PCM data output, DX, will remain in

and

FSXand/or FSRpulses must be pres-

/PDN pin high; the alternative is to

R

and FSRinputs continuously lowÐthe device

X

the high impedance state until the second FS

SYNCHRONOUS OPERATION

For synchronous operation, the same master clock and bit
clock should be used for both the transmit and receive di­rections. In this mode, a clock must be applied to MCLK
and the MCLKR/PDN pin can be used as a power-down
control. A low level on MCLK
and a high level powers down the device. In either case,
MCLK

will be selected as the master clock for both the

X

transmit and receive circuits. A bit clock must also be ap­plied to BCLK
select the proper internal divider for a master clock of 1.536

and the BCLKR/CLKSEL can be used to

X

/PDN powers up the device

R

MHz, 1.544 MHz or 2.048 MHz. For 1.544 MHz operation,
the device automatically compensates for the 193rd clock
pulse each frame.

With a fixed level on the BCLK
selected as the bit clock for both the transmit and receive

/CLKSEL pin, BCLKXwill be

R

directions. Table 1 indicates the frequencies of operation
which can be selected, depending on the state of BCLK
CLKSEL. In this synchronous mode, the bit clock, BCLK
may be from 64 kHz to 2.048 MHz, but must be synchro­nous with MCLK

.

X

Each FSXpulse begins the encoding cycle and the PCM
data from the previous encode cycle is shifted out of the
enabled D
bit clock periods, the TRI-STATE D
high impedance state. With an FS
latched via the D
BCLK
MCLK

output on the positive edge of BCLKX. After 8

X

input on the negative edge of BCLKX(or

R

if running). FSXand FSRmust be synchronous with

R

.

X/R

output is returned to a

X

pulse, PCM data is

R

TABLE I. Selection of Master Clock Frequencies

Master Clock

BCLKR/CLKSEL

Frequency Selected

TP3057 TP3054

Clocked 2.048 MHz 1.536 MHz or

0 1.536 MHz or 2.048 MHz

1.544 MHz

1 2.048 MHz 1.536 MHz or

and VFRO

X

pulse.

X

1.544 MHz

1.544 MHz

X

ASYNCHRONOUS OPERATION

For asynchronous operation, separate transmit and receive
clocks may be applied. MCLK

2.048 MHz for the TP3057, or 1.536 MHz, 1.544 MHz for the

and MCLKRmust be

X

TP3054, and need not be synchronous. For best transmis­sion performance, however, MCLK
with MCLK
logic levels to the MCLK
connect MCLK
Description). For 1.544 MHz operation, the device automati-

or

cally compensates for the 193rd clock pulse each frame.
FS

R

with MCLK
and must be synchronous with BCLK

, which is easily achieved by applying only static

X

X

starts each encoding cycle and must be synchronous

X

and BCLKX.FSRstarts each decoding cycle

X

/PDN pin. This will automatically

R

to all internal MCLKRfunctions (see Pin

clock, the logic levels shown in Table 1 are not valid in
asynchronous mode. BCLK
64 kHz to 2.048 MHz.

SHORT FRAME SYNC OPERATION

X

The COMBO can utilize either a short frame sync pulse or a

should be synchronous

R

. BCLKRmust be a

R

and BCLKRmay operate from

X

long frame sync pulse. Upon power initialization, the device
assumes a short frame mode. In this mode, both frame sync
pulses, FS
with timing relationships specified in
during a falling edge of BCLK
BCLK
output the sign bit. The following seven rising edges clock

and FSR, must be one bit clock period long,

X

enables the DXTRI-STATE output buffer, which will

X

Figure 2

, the next rising edge of

X

. With FSXhigh

out the remaining seven bits, and the next falling edge dis­ables the D
BCLK
of BCLK
edges latch in the seven remaining bits. All four devices
may utilize the short frame sync pulse in synchronous or

/

R

asynchronous operating mode.

,

X

output. With FSRhigh during a falling edge of

X

(BCLKXin synchronous mode), the next falling edge

R

latches in the sign bit. The following seven falling

R

LONG FRAME SYNC OPERATION

To use the long frame mode, both the frame sync pulses,
FS

and FSR, must be three or more bit clock periods long,

X

with timing relationships specified in
transmit frame sync, FS
short or long frame sync pulses are being used. For 64 kHz

, the COMBO will sense whether

X

Figure 3

. Based on the

operation, the frame sync pulse must be kept low for a mini­mum of 160 ns. The D
with the rising edge of FS
whichever comes later, and the first bit clocked out is the
sign bit. The following seven BCLK
the remaining seven bits. The D
falling BCLK
FS

X

receive frame sync pulse, FS
D

R

(BCLKXin synchronous mode). All four devices may utilize

X

going low, whichever comes later. A rising edge on the

to be latched in on the next eight falling edges of BCLK

TRI-STATE output buffer is enabled

X

or the rising edge of BCLKX,

X

rising edges clock out

X

output is disabled by the

edge following the eighth rising edge, or by

X

, will cause the PCM data at

R

R

the long frame sync pulse in synchronous or asynchronous
mode.

In applications where the LSB bit is used for signalling with
FS

two bit clock periods long, the decoder will interpret the

R

lost LSB as ‘‘(/2’’ to minimize noise and distortion.

3

Functional Description (Continued)

TRANSMIT SECTION

The transmit section input is an operational amplifier with
provision for gain adjustment using two external resistors,
see

Figure 4

in excess of 20 dB across the audio passband to be real­ized. The op amp drives a unity-gain filter consisting of RC
active pre-filter, followed by an eighth order switched-ca­pacitor bandpass filter clocked at 256 kHz. The output of
this filter directly drives the encoder sample-and-hold circuit.
The A/D is of companding type according to m-law
(TP3054) or A-law (TP3057) coding conventions. A preci­sion voltage reference is trimmed in manufacturing to pro­vide an input overload (t
table of Transmission Characteristics). The FS
pulse controls the sampling of the filter output, and then the
successive-approximation encoding cycle begins. The 8-bit
code is then loaded into a buffer and shifted out through D
at the next FSXpulse. The total encoding delay will be ap­proximately 165 ms (due to the transmit filter) plus 125 ms

. The low noise and wide bandwidth allow gains

) of nominally 2.5V peak (see

MAX

frame sync

X

(due to encoding delay), which totals 290 ms. Any offset
voltage due to the filters or comparator is cancelled by sign
bit integration.

RECEIVE SECTION

The receive section consists of an expanding DAC which
drives a fifth order switched-capacitor low pass filter
clocked at 256 kHz. The decoder is A-law (TP3057) or
m-law (TP3054) and the 5th order low pass filter corrects for
the sin x/x attenuation due to the 8 kHz sample/hold. The
filter is then followed by a 2nd order RC active post-filter/
power amplifer capable of driving a 600X load to a level of

7.2 dBm. The receive section is unity-gain. Upon the occur­rence of FS
falling edge of the next eight BCLK
the end of the decoder time slot, the decoding cycle begins,
and 10 ms later the decoder DAC output is updated. The

X

total decoder delay isE10 ms (decoder update) plus

, the data at the DRinput is clocked in on the

R

(BCLKX) periods. At

R

110 ms (filter delay) plus 62.5 ms((/2 frame), which gives
approximately 180 ms.

4

Absolute Maximum Ratings

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

V

to GNDA 7V

CC

VBBto GNDA

Voltage at any Analog Input

or Output V

Electrical Characteristics Unless otherwise noted, limits printed in BOLD characters are guaranteed for V

e

5.0Vg5%, V

are assured by correlation with other production tests and/or product design and characterization. All signals referenced to

BB

eb

5.0Vg5%; T

GNDA. Typicals specified at V

CC

a

0.3V to V

CC

e

0§Cto70§C by correlation with 100% electrical testing at T

A

e

5.0V, V

BB

BB

eb

b

7V

b

0.3V

5.0V, T

Symbol Parameter Conditions Min Typ Max Units

DIGITAL INTERFACE

V

IL

V

IH

V

OL

V

OH

I

IL

I

IH

I

OZ

Input Low Voltage 0.6 V

Input High Voltage 2.2 V

Output Low Voltage DX,I

Output High Voltage DX,I

SIG
TS

SIG

L

R,IL

X,IL

H

R,IH

e

eb

Input Low Current GNDAsV

Input High Current V

s

V

IH

Output Current in High Impedance DX, GNDAsV
State (TRI-STATE)

ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (ALL DEVICES)

IIXA Input Leakage Current

RIXA Input Resistance

b

2.5VsV

b

2.5VsV

ROXA Output Resistance Closed Loop, Unity Gain 1 3 X

RLXA Load Resistance GS

CLXA Load Capacitance GS

X

X

VOXA Output Dynamic Range GSX,R

AVXA Voltage Gain VFXIato GS

FUXA Unity Gain Bandwidth 1 2 MHz

VOSXA Offset Voltage

VCMXA Common-Mode Voltage CMRRXAl60 dB

CMRRXA Common-Mode Rejection Ratio DC Test 60 dB

PSRRXA Power Supply Rejection Ratio DC Test 60 dB

ANALOG INTERFACE WITH RECEIVE FILTER (ALL DEVICES)

RORF Output Resistance Pin VFRO13X

R

RF Load Resistance VFRO

L

e

CLRF Load Capacitance 500 pF

VOSRO Output DC Offset Voltage

POWER DISSIPATION (ALL DEVICES)

ICC0 Power-Down Current No Load (Note) 0.5 1.5 mA

IBB0 Power-Down Current No Load (Note) 0.05 0.3 mA

ICC1 Power-Up Active Current No Load 5.0 9.0 mA

IBB1 Power-Up Active Current No Load 5.0 9.0 mA

Note: I

and I

CC0

are measured after first achieving a power-up state.

BB0

Voltage at any Digital Input or

Output V

Operating Temperature Range

Storage Temperature Range

a

0.3V to GNDAb0.3V

CC

b

25§Ctoa125§C

b

65§Ctoa150§C

Lead Temperature (Soldering, 10 seconds) 300§C

ESD (Human Body Model) 2000V

Latch-Up Immunitye100 mA on any Pin

e

25§C. All other limits

A

e

25§C.

A

3.2 mA 0.4 V

e

1.0 mA 0.4 V

e

3.2 mA, Open Drain 0.4 V

3.2 mA 2.4 V

eb

1.0 mA 2.4 V

s

VIL, All Digital Inputs

IN

s

V

IN

CC

s

V

O

s

a

2.5V, VFXIaor VFXI

s

a

2.5V, VFXIaor VFXI

CC

b

10 10 mA

b

10 10 mA

b

10 10 mA

b

b

200 200 nA

b

10 MX

10 kX

50 pF

t

10 kX

L

X

g

2.5V 600 X

b

2.8 2.8 V

5000 V/V

b

20 20 mV

b

2.5 2.5 V

b

200 200 mV

CC

5