NATIONAL SEMICONDUCTOR TP11362AV, TP11362AN Datasheet

TP11362A
Quad Adaptive Differential PCM Processor

TP11362A Quad Adaptive Differential PCM Processor

March 1997

General Description

The TP11362A is a quad (4) channel Adaptive Differential
Pulse Code Modulation (ADPCM) transcoder, fully compat­ible to ITU G.726 recommendation in 40 kbps, 32 kbps,
24 kbps, 16 kbps and ANSI 32 kbps modes. The TP11362A
ADPCM processor can operate on up to 8 independent
channels in an 8 kHz frame. Each channel is individually
configured, supportingboth full and half duplex operation. All
input/output transfers occur on an interrupt basis using se­rial, double buffered data registers. Together with National’s
TP3054/57 COMBO
TP11362A forms complete ADPCM channels with Codec/
filtering.

®

or TP3070/71 COMBO II devices, the

Block Diagram

Features

n CCITT G.726 compatible at 40, 32, 24, 16 kbps
n ANSI T1.301 compatible at 32 kbps
n 8-channel half-duplex (encode or decode) or 4-channel

full-duplex operation in 8 kHz frame

n Each channel individually configurable
n Selectable µ-law or A-law PCM coding
n Asynchronous 8 MHz master clock operation
n TTL and CMOS compatible inputs and outputs
n 28-pin PLCC or 24-pin DIP packages
n Power consumption of typ. 6 mW at +5V per full-duplex

channel

n On-Chip Power-On-Reset
n −40˚C to +85˚C operating temperature range
n Single 5V supply

DS012877-1

FIGURE 1. Block Diagram

TRI-STATE®and COMBO®are registered trademarks of National Semiconductor Corporation.

© 1997 National Semiconductor Corporation DS012877 www.national.com

Connection Diagrams

Plastic Chip Carriers

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Top View

Order Number TP11362AV

See NS Package Number V28A

Pin Descriptions

TSI

Transmit PCM serial data input. TSI is an 8-bit PCM data
stream and is shifted into an 8-bit serial-to-parallel register
on the falling edges of PSCK while CE and TRB are high.
The last 8 bits of TSI are latched and transferred to the core
for processing at the falling edge of CE.

TSO

Transmit ADPCM TRI-STATE
data bit stream of 4- to 5-bit length is shifted out with the ris­ing edge of ASCK when CE is high following the processing
of a transmit channel. TSO is in TRI-STATE mode while CE
is low or while RSO output is active.

RSI

Receive ADPCM serial data input. A serial data bit stream of
4- to 5-bit length is shifted in with the falling edges of ASCK
while CE is high and TRB is low. The last 4 or 5 bits of RSI
are latched and transferred to the core for processing at the
falling edge of CE.

RSO

Receive PCM TRI-STATE serial data output. An 8-bit serial
PCM data stream is shifted out with the rising edges of
PSCK when CE is high following the processing of a receive
channel. RSO is in TRI-STATE mode while CE is low or while
TSO output is active.

PSCK

PCM serial clock input. PSCK is used to shift PCM data into
TSI or out of RSO while CE is active (high). The transfer de­pends on the logic state of TRB.

ASCK

ADPCM serial clock input. ASCK is used to shift ADPCM
data into RSI or out of TSO while CE is active (high). The
transfer depends on the logic state of TRB.

®

serial data output. A serial

Plastic Dual-In-Line

DS012877-3

Top View

Order Number TP11362AN

See NS Package Number N24A

CLK

Master clock input. CLK may be asynchronous to PSCK or
ASCK.

CE

Chip enable input. When CE is high, it enables data transfer.
The falling edge of CE latches and transfers the serial data
TSI or RSI to the core for processing and strobes the control
signals QSEL0, QSEL1, PCM1, EN and INIT. CE should
change state only when PSCK and ASCK are high. CE,
when low, sets the TSO and RSO outputs into TRI-STATE
mode.

TRB

Transmitter or receiver select. A logic low at TRB selects the
receiver of the channel processed. A logic high enables the
transmitter of the channel processed. TRB determines which
input register is enabled and which output register and out­put is enabled. TRB should be stable while CE is high.

EN

Channel enable input. EN is strobed in with the falling edge
of CE. A logic high at the falling edge of CE indicates that the
channel is active, and the ADPCM will process the data just
clocked in.

INIT

Channel initialization input. INIT is read at the falling edge of
CE.Alogic high at the falling edge of CE causes the ADPCM
processor to initialize the channel currently processing.

PCM1

PCM coding law select. A logic low at PCM1 selects 8-bit
µ-law, while a logic high selects 8-bit A-law with even bit in­version.

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Pin Descriptions (Continued)

QSEL0, QSEL1

ADPCM bit rate select inputs. The QSEL0 and QSE1 signals
are strobed in with the falling edge of CE. The QSEL0 and
QSEL1 select the conversion bit rate of the PCM data just
clocked in at the TSI input or the bit rate of the ADPCM data
just clocked in at the RSI input. See

Table 1

.

RSTB

Chip reset input.Alow to high transition at RSTB initiates the
reset sequence which initializes the channel variables for all
eight channels. A logic low applied to this pin sets the
transcoder into a low power dissipation mode. RSTB should
be pulled high for normal operation.

TST0, TST1, TST2

Test inputs for factory testing purposes. TST0–2 should be
tied low for normal operation.

V

CC1,VCC2

Positive power supply input pins. V
ceramic bypass capacitor should be connected between
V

and GND1, and V

CC1

and GND2.

CC2

=

±

5%. A 0.1 µF

5V

CC

GND1, GND2

Ground input pins.

NC

Not connected.

Functional Description

Adaptive Differential Pulse Code Modulation (ADPCM) is a
transcoding algorithm for voice and voice band data trans­mission. The use of ADPCM reduces the channel bandwidth
requirements from the standard 64 kbps PCM signal by a
factor of two or more. It is used for converting a 64 kbps
A-law or µ-law PCM channel to and from a 40, 32, 24 or
16 kbps channel. The 8-bit PCM signal is reduced to 2–5bits
ADPCM signal depending on the selected bit rate in the en­coder.

The TP11362A meets the ITU (CCITT) G.726 recommenda­tion for 40, 32, 24, and 16 kbps ADPCM, as well as ANSI
T1.301 for 32 kbps. Each channel can be operated with an
independently selectable bit rate determined by QSEL1 and
QSEL0 (see

The ADPCM encoder converts the 64 kbps A-law or µ-law
PCM input signal to a uniform PCM signal which is sub­tracted from an estimated signal obtained from an adaptive
predictor. A 31-, 15-, 7-, or 4-level non-uniform quantizer is
used to assign five, four, three or two binary digits, respec­tively, to the value of the difference signal for transmission.
The ADPCM decoder reconstructs the original PCM signal
by adding the received quantized signal to the signal estima­tion calculated by the predictor. A synchronous coding ad-

Table 1

).

TABLE 1. Bit Rate Selection

QSEL1 QSEL0 ADPCM Bit Rate

0 0 32 kbps
0 1 24 kbps
1 0 16 kbps
1 1 40 kbps

justment unit prevents cumulative distortion occurring on
synchronous tandem codings (ADPCM-PCM-ADPCM) un­der certain conditions.

The adaptive predictor consists of two independent predictor
structures. One uses a second order recursive filter which
models the poles, and the other uses a sixth order
non-recursive filter which models the zeros in the input sig­nal. This dual structure enables effective handling of both
speech and voice band data signals.

ADPCM PROCESSING

ADPCM to PCM Decoding Operation

When a logic “0” of TRB is latched in with the falling edge of
CE, the ADPCM processor is set to the decoding mode. Data
applied at the RSI input is sampled with the falling edge of
ASCK into a 5-bit ADPCM serial register. Within the next
cycle of CE, the decoder converts the ADPCM input data to
an 8-bit companded PCM data after 123 master clocks
(CLK). The 8-bit parallel PCM data is loaded into a
parallel-to-serial shift register and shifted out at the RSO out­put with the rising edges of PSCK.

PCM to ADPCM Encoding Operation

A logic “1” of TRB at the falling edge of CE sets the ADPCM
processor to the encoding mode. Data applied at the TSI in­put is sampled in an internal 8-bit PCM register with the fall­ing edge of PSCK. During the next cycle of CE, the encoder
converts the companded 8-bit PCM data into a 5-, 4-, 3- or
2-bit ADPCM data, which will be shifted out during the third
cycle of CE at the TSO output with the rising edges of ASCK.

The TP11362A requires one master clock signal CLK. The
master clock signal CLK is not required to be synchronous to
the serial I/O clocks ASCK or PSCK. The serial interface
uses the serial clocks ASCK and PSCK and chip enable CE
for receiving and transmitting data. The data is internally
synchronized to the master clock CLK. There is a lower limit
of the clock frequency for CLK resulting from the number of
clock cycles required for processing the data.

Table2

shows
the required clock cycles per channel depending on the se­lected mode.

TABLE 2. Processing Cycles

Mode of Operation CLK Cycles Needed

Decoder 123
Encoder 123
Initialized Channel 45
Disabled Channel 4

The sampling period (usually 125 µs for 8 kHz frame) divided
by the number of CLK cycles gives the required minimum
CLK period. A slightly higher CLK frequency is used in order
to allow for jitter and inaccuracies in the CLK rate. As an ex­ample, for a four channelADPCM codec, CLK frequency is 8
MHz as shown in the following calculations:

t

CLK

f

CLKmin

f

CLKnom

=

125 µs /(8

=

=

1/t

CLK

8.0 MHz

*

123)=127.03 ns

=

7.872 MHz

The period of CE must be equal to or greater than the re­quired number of CLK cycles times the period of CLK. CE
must be low for more than 4 CLK cycles.

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Functional Description (Continued)

The TP11362A is capable of processing eight independent
channels (half duplex) or four full-duplex PCM channels
within 125 µs (8 kHz).

The logic state of TRB at the falling edge of CE determines
which input register is active during that CE period and which
output register will be active in the following third CE period.

The input data is processed (PCM data encoded or ADPCM
data decoded) during the second cycle and shifted out in the
third cycle of CE while CE is high.

SERIAL I/O

Input data is transferred into the TP11362A on the falling
edge of the clock signal, while output data is transmitted on
the rising edge of the clock signal. PCM data is transferred
synchronously using PSCK, while ADPCM data is trans­ferred synchronously using ASCK. The clock signals ASCK
and PSCK should be high while CE changes. All serial data
is transferred with MSB first.
serial input and output structures, respectively.

PCM Serial Input Register

The serial PCM data to be encoded is shifted into the 8-bit
PCM input register with the falling edges of PSCK while CE
and TRB are high. The falling edge of CE latches the state of

Figure 2

and

Figure 3

show the

the input register and transfers the last 8 bits data prior to the
CE transition to the core for processing. The 8-bit PCM input
register is cleared asynchronously with RSTB going low.

ADPCM Serial Input Register

The ADPCM serial input register is a 5-bit shift register to
store the 5-bit data in the 40 kbps ADPCM mode. Serial input
data is latched in with the falling edges of ASCK while CE is
high and TRB is low. A minimum number of five low going
ASCK pulses must be available within the CE pulse when
operating in the 40 kbps mode. For the 32, 24 and 16 kbps
modes,ASCK must be pulsed low 4 times while CE is high to
read in the RSI data. The falling edge of CE latches the last
5 bits data in the 40 kbps mode or the last 4 bits data in the
32, 24, and 16 kbps modes prior to the CE transistion. See

Table3

for the position of the ADPCM data in the 5-bit input
register when 5 ASCK low going pulses occur while CE is
high and TRB is low. Bit 1 in
last bit in 32 and 40 kbps modes referenced to the negative
edge of CE.

Table3

is the LSB which is the

FIGURE 2. Serial Input Structure

ADPCM Output Register

The internal encoded parallel ADPCM data is loaded into the
5-bit ADPCM output register with the falling edge of CE sig­nal. The first MSB data is shifted out after the rising edge of
CE, subsequent ADPCM serial data is shifted out with the
rising edge of ASCK.
ADPCM output data. If more than 4 ASCK clocks are avail­able while CE is high in the 32, 24, and 16 kbps modes, the
ADPCM output data will recirculate starting with the MSB. In
the case of the 40 kbps mode, the ADPCM output pattern will
recirculate, starting with the MSB, with the fifth rising edge of
ASCK while CE is high.

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Table4

shows the transfer order of the

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PCM Output Register

The decoded 8-bit parallel PCM data is loaded into an 8-bit
parallel-to-serial output shift register with the falling edge of
CE. The MSB data is shifted out with the leading edge of CE,
and subsequent data are shifted out with the rising edges of
PSCK while CE is high. The 8-bit PCM data at the RSO out­put will recirculate with the MSB first after the seventh rising
edge of PSCK while CE is high.

Figure 4

shows the full duplex timing diagram for the 40 kbps
mode. For the 32, 24 and 16 kbps modes only fourASCK low
pulses are needed while CE is high.

TRB is alternate high and low in the full duplex mode at each
falling edge of CE for a transmit (encoder) operation followed

Functional Description (Continued)

by a receive (decoder) operation. For the encoding opera­tion, the PCM data is stored in the 8-bit shift register at the
falling edge of CE while TRB is high. The TP11362A pro­cesses the data within 123 CLK periods during the following
cycle of CE. The encoded ADPCM data is loaded into the
5-bit parallel-to-serial output register with the falling edge of
CE. The MSB data is shifted out first with the leading edge of
CE, and subsequent data is shifted out with the rising edge
of ASCK. For the decoding operation, the ADPCM data is

latched and transferred to the core at the falling edge of CE
while TRB is low. The data is processed within 123 CLK pe­riods and the decoded 8-bit PCM data is shifted out with the
MSB first.

PSCK and ASCK are the clocks for the PCM and ADPCM
data streams, respectively. They must be high during the
transition of CE. Note that PSCK and ASCK are shown as
gated clocks as an option to conserve power. PSCK and
ASCK need only be valid while CE is high.

FIGURE 3. Serial Output Structure

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